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[Qemu-commits] [qemu/qemu] e71ec2: target-ppc: Enable ISEL on POWER7
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[Qemu-commits] [qemu/qemu] e71ec2: target-ppc: Enable ISEL on POWER7 |
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Date: |
Fri, 26 Apr 2013 16:00:13 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e71ec2e93dad4446d245031382e30b377640d9ca
https://github.com/qemu/qemu/commit/e71ec2e93dad4446d245031382e30b377640d9ca
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Enable ISEL on POWER7
ISEL is a Power ISA 2.06 instruction and thus is available on POWER7.
Given this is trapped and emulated by the Linux kernel, I guess it went
unnoticed.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 3b961124bf8a0b490e4fc3a6a39e004500ae6967
https://github.com/qemu/qemu/commit/3b961124bf8a0b490e4fc3a6a39e004500ae6967
Author: Stuart Yoder <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/e500plat.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
Log Message:
-----------
PPC: e500: advertise 4.2 MPIC only if KVM supports EPR
Older KVM versions don't support EPR which breaks guests when we announce
MPIC variants that support EPR.
Catch that case and expose only MPIC version 2.0 which tells the guest that
we don't support the EPR capability yet.
Signed-off-by: Stuart Yoder <address@hidden>
[agraf: Add comment, route cap check through kvm_ppc.c]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2cf3eb6df552cee74b52de9989e270b74e42847e
https://github.com/qemu/qemu/commit/2cf3eb6df552cee74b52de9989e270b74e42847e
Author: Fabien Chouteau <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/spapr.c
M target-ppc/cpu.h
M target-ppc/machine.c
M target-ppc/translate_init.c
Log Message:
-----------
PPC: Remove env->hreset_excp_prefix
This value is not needed if we use correctly the MSR[IP] bit.
excp_prefix is always 0x00000000, except when the MSR[IP] bit is
implemented and set to 1, in that case excp_prefix is 0xfff00000.
The handling of MSR[IP] was already implemented but not used at reset
because the value of env->msr was changed "manually".
The patch uses the function hreg_store_msr() to set env->msr, this
ensures a good handling of MSR[IP] at reset, and therefore a good value
for excp_prefix.
Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 8e7a6db96566fe4162edaeb3e8b62fc8004d1598
https://github.com/qemu/qemu/commit/8e7a6db96566fe4162edaeb3e8b62fc8004d1598
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: fix nego and subf*o instructions
The overflow computation of nego and subf*o instructions has been broken
in commit ffe30937. Contrary to other targets, the instruction is subtract
from an not subtract on PowerPC.
This patch fixes the issue by using the correct argument in the xor
computation. Thanks to Peter Maydell for the hint.
With this change the PPC emulation passes the Gwenole Beauchesne
testsuite again.
Signed-off-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 09d9828ace37ead29d510a7e24e63c2f15cd4b1c
https://github.com/qemu/qemu/commit/09d9828ace37ead29d510a7e24e63c2f15cd4b1c
Author: Fabien Chouteau <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
PPC: fix hreset_vector for 60x, 7x0, 7x5, G2, MPC8xx, MPC5xx, 7400 and 7450
According to the different user's manuals, the vector offset for system
reset (both /HRESET and /SRESET) is 0x00100.
This patch may break support of some executables, as the power-on start
address may change. For a specific board, if the power-on start address
is different than HRESET vector (i.e. 0x00000100 or 0xfff00100), this
should be fixed in board's initialization code.
Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 2bc173224adc0fc318f2bd6fcf65dfdbc7d51123
https://github.com/qemu/qemu/commit/2bc173224adc0fc318f2bd6fcf65dfdbc7d51123
Author: Fabien Chouteau <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
PPC: Add breakpoint registers for 603 and e300
Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 752d634ecc74c76eb5e32db0e536d84c2d6aa3d8
https://github.com/qemu/qemu/commit/752d634ecc74c76eb5e32db0e536d84c2d6aa3d8
Author: Richard Henderson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Fix narrow-mode add/sub carry output
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself was
fixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need to
produce the full 64-bit addition.
Simplify the conditions at the top of the functions for when we need a
new temporary. Only plain addition is important enough to warrent avoiding
the temporary, and the extra tcg move op that would come with it.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Tested-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: cae7f586419ad261f55ef8700bf8f3fa5b4879d4
https://github.com/qemu/qemu/commit/cae7f586419ad261f55ef8700bf8f3fa5b4879d4
Author: Alexander Graf <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M linux-headers/asm-powerpc/kvm.h
M linux-headers/linux/kvm.h
Log Message:
-----------
linux-headers: Update to kvm/queue
Based on kvm.git queue branch with commit e1e2e605.
Signed-off-by: Alexander Graf <address@hidden>
Commit: 31f2cb8ff415e376b05335dcf63ba38c00f29e5e
https://github.com/qemu/qemu/commit/31f2cb8ff415e376b05335dcf63ba38c00f29e5e
Author: Bharat Bhushan <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/ppc_booke.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
Log Message:
-----------
Enable kvm emulated watchdog
Enable the KVM emulated watchdog if KVM supports (use the
capability enablement in watchdog handler). Also watchdog exit
(KVM_EXIT_WATCHDOG) handling is added.
Watchdog state machine is cleared whenever VM state changes to running.
This is to handle the cases like return from debug halt etc.
Signed-off-by: Bharat Bhushan <address@hidden>
[agraf: rebase to current code base, fix non-kvm cases]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 20f649dd22dae13301c906c27a8768a318591ae8
https://github.com/qemu/qemu/commit/20f649dd22dae13301c906c27a8768a318591ae8
Author: Alexander Graf <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/mac_newworld.c
Log Message:
-----------
PPC: mac newworld: fix cpu NIP reset value
On -M mac99, we can run 970 CPUs. However, these CPUs define the initial
instruction pointer they start execution at as part of their bootup protocol,
so effectively it's up to the board to decide where they start.
This went unnoticed, because they used to boot at the same location our flash
was mapped to, but due to the recent reset changes our 970 CPUs want to reset
to 0x100 now, which is always a 0 instruction.
Set the initial IP to something reasonable for -M mac99.
Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Fabien Chouteau <address@hidden>
Commit: c8ff5daa09516272117eb23cd00da5d188ba73eb
https://github.com/qemu/qemu/commit/c8ff5daa09516272117eb23cd00da5d188ba73eb
Author: Alexander Graf <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M translate-all.c
Log Message:
-----------
PPC: Fix compile with profiling enabled
When using profiling, we rely on profile_getclock() being available
at our disposal. Somehow that function got moved from an indirect
include we used to have in translate-init.c, so that we were now
left not properly compiling anymore.
Add an explicit include to timer.h which defines profile_getclock,
so that we can compile again.
Signed-off-by: Alexander Graf <address@hidden>
Commit: f36951c19f15f3c053a31234bd2c297d86c1a052
https://github.com/qemu/qemu/commit/f36951c19f15f3c053a31234bd2c297d86c1a052
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
pseries: Fix incorrect calculation of RMA size in certain configurations
For the pseries machine, we need to advertise to the guest the size of its
RMA - that is the amount of memory it can access with the MMU off. For HV
KVM, this is constrained by the hardware limitations on the virtual RMA of
one hash PTE per PTE group in the hash page table. We already had code to
calculate this, but it was assuming the VRMA page size was the same as the
(host) backing page size for guest RAM.
In the case of a host kernel configured for 64k base page size, but running
on hardware (or firmware) which only allows 4k pages, the hose will do all
its allocations with a 64k page size, but still use 4k hardware pages for
actual mappings. Usually that's transparent to things running under the
host, but in the case of the maximum VRMA size it's not.
This patch refines the RMA size calculation to instead use the largest
available hardware page size (as reported by the SMMU_INFO call) which is
less than or equal to the backing page size. This now gives the correct
RMA size in all cases I've tested.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 0cbad81f70546b58f08de3225f1eca7a8b869b09
https://github.com/qemu/qemu/commit/0cbad81f70546b58f08de3225f1eca7a8b869b09
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/spapr.c
M target-ppc/cpu-qom.h
M target-ppc/kvm.c
M target-ppc/translate_init.c
Log Message:
-----------
pseries: Fixes and enhancements to L1 cache properties
PAPR requires that the device tree's CPU nodes have several properties
with information about the L1 cache. We already create two of these
properties, but with incorrect names - "[id]cache-block-size" instead
of "[id]-cache-block-size" (note the extra hyphen).
We were also missing some of the required cache properties. This
patch adds the [id]-cache-line-size properties (which have the same
values as the block size properties in all current cases). We also
add the [id]-cache-size properties.
Adding the cache sizes requires some extra infrastructure in the
general target-ppc code to (optionally) set the cache sizes for
various CPUs. The CPU family descriptions in translate_init.c can set
these sizes - this patch adds correct information for POWER7, I'm
leaving other CPU types to people who have a physical example to
verify against. In addition, for -cpu host we take the values
advertised by the host (if available) and use those to override the
information based on PVR.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 702763fa322ea69dde92517735507e0ac3879b5d
https://github.com/qemu/qemu/commit/702763fa322ea69dde92517735507e0ac3879b5d
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Add more stubs for POWER7 PMU registers
In addition to the performance monitor registers found on nearly all
6xx chips, the POWER7 has two additional counters (PMC5 & PMC6) and an
extra control register (MMCRA). This patch adds stub support for them to
qemu - the registers won't do anything, but with this change won't cause
illegal instruction traps accessing them. They're also registered with
their ONE_REG ids, so their value will be kept in sync with KVM where
appropriate.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: e03c902cb617414dae49d77a810f6957ff7affac
https://github.com/qemu/qemu/commit/e03c902cb617414dae49d77a810f6957ff7affac
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/xics.c
Log Message:
-----------
pseries: Fix some small errors in XICS logic
Under certain circumstances the emulation for the pseries "XICS" interrupt
controller was clearing a pending interrupt from the XISR register, without
also clearing the corresponding priority variable. This will cause
problems later when can trigger sanity checks in the under-development
in-kernel XICS implementation.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9b00ea4906a618756bcd10f09d432780eab87782
https://github.com/qemu/qemu/commit/9b00ea4906a618756bcd10f09d432780eab87782
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
target-ppc: Synchronize VPA state with KVM
For PAPR guests, KVM tracks the various areas registered with the
H_REGISTER_VPA hypercall. For full emulation, of course, these are tracked
within qemu. At present these values are not synchronized. This is a
problem for reset (qemu's reset of the VPA address is not pushed to KVM)
and will also be a problem for savevm / migration.
The kernel now supports accessing the VPA state via the ONE_REG interface,
this patch adds code to qemu to use that interface to keep the qemu and
KVM ideas of the VPA state synchronized.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: fd506b4f61cd22793f8c54a9adf5c69345792501
https://github.com/qemu/qemu/commit/fd506b4f61cd22793f8c54a9adf5c69345792501
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/char/spapr_vty.c
M hw/net/spapr_llan.c
M hw/nvram/spapr_nvram.c
M hw/ppc/spapr_vio.c
M hw/scsi/spapr_vscsi.c
Log Message:
-----------
pseries: Convert VIO code to QOM style type safe(ish) casts
Curerntly the pseries VIO device code contains quite a few explicit
uses of DO_UPCAST and plain C casts. This is (obviously) type unsafe,
and not the conventional way of doing things in the QOM model. This
patch converts the code to use the QOM convention of per-type macros
to do verified casts with OBJECT_CHECK().
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: c4eda5b7234265313b09c2c9f9fdd3a960db97db
https://github.com/qemu/qemu/commit/c4eda5b7234265313b09c2c9f9fdd3a960db97db
Author: David Gibson <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M hw/ppc/spapr_vio.c
Log Message:
-----------
pseries: Generate device paths for VIO devices
This patch implements a get_dev_path qdev hook for the pseries paravirtual
VIO bus. With upcoming savevm support, this will become very important for
scsi disks hanging of VIO virtual SCSI adapters. scsibus_get_dev_path
uses the get_dev_path of the parent adapter if available, but otherwise
just uses a local channel/target/lun number to identify the device. So if
two disks are present in the system having the same target and lun on
seperate VIO scsi adapters, savevm cannot distinguish them. Since the
conventional way of using VSCSI adapters is to have just one disk per
adapter, such a conflict is very likely.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: db72c9f256ae70b30c5d5985234f085df4226c55
https://github.com/qemu/qemu/commit/db72c9f256ae70b30c5d5985234f085df4226c55
Author: Tristan Gingold <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/fpu_helper.c
Log Message:
-----------
powerpc: correctly handle fpu exceptions.
Raise the exception on the first occurence, do not wait for the next
floating point operation.
Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 414f5d1448fef9aad6d37f1d40d1158396573447
https://github.com/qemu/qemu/commit/414f5d1448fef9aad6d37f1d40d1158396573447
Author: Alexander Graf <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/mem_helper.c
Log Message:
-----------
PPC: Fix dcbz for linux-user on 970
The default with linux-user for dcbz on 970 is to emulate 32 byte clears.
However, redoing the dcbzl support we added a check to not honor the bit
in HID5 that sets this.
Remove the #ifdef check on linux user, so that we get 32 byte clears again.
Reported-by: Riku Voipio <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: bf45a2e67cab8fcccb24e389bbd4ef68866a1cff
https://github.com/qemu/qemu/commit/bf45a2e67cab8fcccb24e389bbd4ef68866a1cff
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/fpu_helper.c
M target-ppc/helper.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,
this can be implemented in TCG instead of using softfloat.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 88770fec6c8daeb96c1f5cdbedff9df173431fd6
https://github.com/qemu/qemu/commit/88770fec6c8daeb96c1f5cdbedff9df173431fd6
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M disas.c
Log Message:
-----------
disas: Disassemble all ppc insns for the guest
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 9c2627b09d1bdee8a58730bbf48c76be48bd659f
https://github.com/qemu/qemu/commit/9c2627b09d1bdee8a58730bbf48c76be48bd659f
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: add instruction flags for Book I 2.05
.. and enable it on POWER7 CPU.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: fcfda20f2f5df30d88d087d443c1c08649df8827
https://github.com/qemu/qemu/commit/fcfda20f2f5df30d88d087d443c1c08649df8827
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate cmpb instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 725bcec2885d4f6df78e24fb54459c9efb97abd5
https://github.com/qemu/qemu/commit/725bcec2885d4f6df78e24fb54459c9efb97abd5
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate prtyw and prtyd instructions
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
[agraf: fix 32-bit host compile, simplify code]
Signed-off-by: Alexander Graf <address@hidden>
Commit: f03328882f8008fc299d5f8ae33b9a80571fea3c
https://github.com/qemu/qemu/commit/f03328882f8008fc299d5f8ae33b9a80571fea3c
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate fcpsgn instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 199f830d19576c77a5ed8fec81c218258d73f1dd
https://github.com/qemu/qemu/commit/199f830d19576c77a5ed8fec81c218258d73f1dd
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate lfiwax instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
[agraf: fix tcg debug error]
Signed-off-by: Alexander Graf <address@hidden>
Commit: 05050ee8049f9fe75ffcac4a5aa053b5631653bf
https://github.com/qemu/qemu/commit/05050ee8049f9fe75ffcac4a5aa053b5631653bf
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate load doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 44bc0c4d3e90bfa1fafdbcc19d023d2d4b119eed
https://github.com/qemu/qemu/commit/44bc0c4d3e90bfa1fafdbcc19d023d2d4b119eed
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: emulate store doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd register
pairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 7d08d85645def18eac2a9d672c1868a35e0bcf79
https://github.com/qemu/qemu/commit/7d08d85645def18eac2a9d672c1868a35e0bcf79
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/fpu_helper.c
M target-ppc/translate.c
Log Message:
-----------
target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a new
W field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with
up to 16 bits. The mtfsf/mtfsfi instructions do not have the W bit
marked as invalid anymore. Instead this is checked in the helper, which
therefore needs to access to the insns/insns_flags2. They are added in
the DisasContext struct. Finally change all accesses to the opcode fields
through extract helpers, prefixed with FP for consistency.
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Commit: 076bfd7c65ce08c18d0c375e3779be25206ee2b7
https://github.com/qemu/qemu/commit/076bfd7c65ce08c18d0c375e3779be25206ee2b7
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M disas.c
M hw/char/spapr_vty.c
M hw/net/spapr_llan.c
M hw/nvram/spapr_nvram.c
M hw/ppc/e500plat.c
M hw/ppc/mac_newworld.c
M hw/ppc/ppc_booke.c
M hw/ppc/spapr.c
M hw/ppc/spapr_vio.c
M hw/ppc/xics.c
M hw/scsi/spapr_vscsi.c
M linux-headers/asm-powerpc/kvm.h
M linux-headers/linux/kvm.h
M target-ppc/cpu-qom.h
M target-ppc/cpu.h
M target-ppc/fpu_helper.c
M target-ppc/helper.h
M target-ppc/int_helper.c
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M target-ppc/machine.c
M target-ppc/mem_helper.c
M target-ppc/translate.c
M target-ppc/translate_init.c
M translate-all.c
Log Message:
-----------
Merge branch 'ppc-for-upstream' of git://github.com/agraf/qemu
* 'ppc-for-upstream' of git://github.com/agraf/qemu: (30 commits)
target-ppc: add support for extended mtfsf/mtfsfi forms
target-ppc: emulate store doubleword pair instructions
target-ppc: emulate load doubleword pair instructions
target-ppc: emulate lfiwax instruction
target-ppc: emulate fcpsgn instruction
target-ppc: emulate prtyw and prtyd instructions
target-ppc: emulate cmpb instruction
target-ppc: add instruction flags for Book I 2.05
disas: Disassemble all ppc insns for the guest
target-ppc: optimize fabs, fnabs, fneg
PPC: Fix dcbz for linux-user on 970
powerpc: correctly handle fpu exceptions.
pseries: Generate device paths for VIO devices
pseries: Convert VIO code to QOM style type safe(ish) casts
target-ppc: Synchronize VPA state with KVM
pseries: Fix some small errors in XICS logic
target-ppc: Add more stubs for POWER7 PMU registers
pseries: Fixes and enhancements to L1 cache properties
pseries: Fix incorrect calculation of RMA size in certain configurations
PPC: Fix compile with profiling enabled
...
Commit: 909eedb74f88d1d6d9e6bbdc34875772e7a8a5ab
https://github.com/qemu/qemu/commit/909eedb74f88d1d6d9e6bbdc34875772e7a8a5ab
Author: Aurelien Jarno <address@hidden>
Date: 2013-04-26 (Fri, 26 Apr 2013)
Changed paths:
M target-ppc/translate.c
Log Message:
-----------
target-ppc: slightly optimize lfiwax
Signed-off-by: Aurelien Jarno <address@hidden>
Compare: https://github.com/qemu/qemu/compare/75f6e8b0f121...909eedb74f88
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