[Qemu-commits] [qemu/qemu] 6d9571: target-arm: A64: Implement SIMD 3-reg

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[Qemu-commits] [qemu/qemu] 6d9571: target-arm: A64: Implement SIMD 3-reg

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 6d9571: target-arm: A64: Implement SIMD 3-reg-same shift a...
Date:	Tue, 11 Feb 2014 04:00:05 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6d9571f7d842a2112937fb161a5c077ca4cac757
      
https://github.com/qemu/qemu/commit/6d9571f7d842a2112937fb161a5c077ca4cac757
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns

Implement the SIMD 3-reg-same instructions SQADD, UQADD,
SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
SQRSHL, UQRSHL; these are all simple calls to existing
Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
for the 3-reg-same-scalar category (but not the others
because they can have non-size-64 operands and the
scalar_3reg_same function doesn't support that yet.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 8b12a0cfc1449b1a0768705e61df5235bf93160d
      
https://github.com/qemu/qemu/commit/8b12a0cfc1449b1a0768705e61df5235bf93160d
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns

Implement the SIMD 3-reg-same instructions where the size == 3 case
is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,
UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,
SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.)
This completes the non-pairwise integer instructions in this category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0173a00521e3d66afbeb0d0b19e78ac68095b7e7
      
https://github.com/qemu/qemu/commit/0173a00521e3d66afbeb0d0b19e78ac68095b7e7
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD

Implement the pairwise integer operations in the 3-reg-same SIMD group:
ADDP, SMAXP, SMINP, UMAXP and UMINP.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: c1de788ab9584e9629d6e9004d8cddd428b6cbe4
      
https://github.com/qemu/qemu/commit/c1de788ab9584e9629d6e9004d8cddd428b6cbe4
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR

We have macros for marking TCGv values as unused, checking if they
are unused and comparing them to each other. However these only exist
for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 3720a7ea364607a19b26745c40e648a1c0e20523
      
https://github.com/qemu/qemu/commit/3720a7ea364607a19b26745c40e648a1c0e20523
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement scalar pairwise ops

Implement the instructions in the scalar pairwise group (C3.6.8).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: c0b2b5fa3651caff0b33621583a3709a8875e85f
      
https://github.com/qemu/qemu/commit/c0b2b5fa3651caff0b33621583a3709a8875e85f
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement remaining integer scalar-3-same insns

Implement the remaining integer instructions in the scalar-three-reg-same
group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,
SQDMULH, SQRDMULH.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: effa8e06435e6a47a3a21e50fd638b6fb29e616a
      
https://github.com/qemu/qemu/commit/effa8e06435e6a47a3a21e50fd638b6fb29e616a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc

Implement the simple 64 bit integer operations from the SIMD
scalar 2-register misc group (C3.6.12): the comparisons against
zero, plus ABS and NEG.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 45aecc6dbb9e282bd880d155f80018a192c90ff2
      
https://github.com/qemu/qemu/commit/45aecc6dbb9e282bd880d155f80018a192c90ff2
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add skeleton decode for SIMD 2-reg misc group

Add a skeleton decode for the SIMD 2-reg misc group.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 94b6c911c644de8621b7be48b0fa0f9c2b7a2122
      
https://github.com/qemu/qemu/commit/94b6c911c644de8621b7be48b0fa0f9c2b7a2122
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement 2-register misc compares, ABS, NEG

Implement the simple 2-register-misc operations we can share
with the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,
SQNEG also fall into this category, but aren't implemented in
the scalar-2-register case yet either.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 86cbc418ce764b877c2db8993f1f7a05d9be7702
      
https://github.com/qemu/qemu/commit/86cbc418ce764b877c2db8993f1f7a05d9be7702
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT

Implement the 2-reg-misc CNT, NOT and RBIT instructions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: d980fd59a49b06f8431fdb418068c2acc0fce8d5
      
https://github.com/qemu/qemu/commit/d980fd59a49b06f8431fdb418068c2acc0fce8d5
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add narrowing 2-reg-misc instructions

Add the narrowing integer instructions in the 2-reg-misc class.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 39d8211893efdc5cbcd6a8f51a65e33eac6fa3da
      
https://github.com/qemu/qemu/commit/39d8211893efdc5cbcd6a8f51a65e33eac6fa3da
  Author: Alex Bennée <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add 2-reg-misc REV* instructions

Add the byte-reverse operations REV64, REV32 and REV16 from the
two-reg-misc group.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: f93d0138959918f896b91b43c99a56a50a2e8463
      
https://github.com/qemu/qemu/commit/f93d0138959918f896b91b43c99a56a50a2e8463
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group

Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 239c20c7c87816402acdb118a5295acda9d25c5c
      
https://github.com/qemu/qemu/commit/239c20c7c87816402acdb118a5295acda9d25c5c
  Author: Will Newton <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 64bit VCVTB and VCVTT

Add support for the AArch32 floating-point half-precision to double-
precision conversion VCVTB and VCVTT instructions.

Signed-off-by: Will Newton <address@hidden>
[PMM: fixed a minor missing-braces style issue]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8d999995e45c1002aa11f269c98f2e93e6f8c42a
      
https://github.com/qemu/qemu/commit/8d999995e45c1002aa11f269c98f2e93e6f8c42a
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  arm_gic: Fix GIC pending behavior

The existing implementation of the pending behavior in gic_set_irq,
gic_complete_irq, and the distributor pending set/clear registers does
not follow the semantics of the GICv2.0 specs, but may implement the
11MPCore support.  Therefore, maintain the existing semantics for
11MPCore and v7M NVIC and change the behavior to be in accordance with
the GICv2.0 specs for "generic implementations" (s->revision == 1 ||
s->revision == 2).

Generic implementations distinguish between setting a level-triggered
interrupt pending through writes to the GICD_ISPENDR and when hardware
raises the interrupt line.  Writing to the GICD_ICPENDR will not cause
the interrupt to become non-pending if the line is still active, and
conversely, if the line is deactivated but the interrupt is marked as
pending through a write to GICD_ISPENDR, the interrupt remains pending.
Handle this situation in the GIC_TEST_PENDING (which now becomes a
static inline named gic_test_pending) and let the 'pending' field
correspond only to the latched state of the D-flip flop in the GICv2.0
specs Figure 4-10.

The following changes are added:

gic_test_pending:
Make this a static inline and split out the 11MPCore from the generic
behavior.  For the generic behavior, consider interrupts pending if:
    ((s->irq_state[irq].pending & (cm) != 0) ||
       (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm))

gic_set_irq:
Split out the 11MPCore from the generic behavior.  For the generic
behavior, always GIC_SET_LEVEL() on positive level, but only
GIC_SET_PENDING for edge-triggered interrupts and always simply
GIC_CLEAR_LEVEL() on negative level.

gic_complete_irq:
Only resample the line for line-triggered interrupts on an 11MPCore.
Generic implementations will sample the line directly in
gic_test_pending().

Signed-off-by: Christoffer Dall <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 40d225009efe17cad647b4b7424b77a3ace232f1
      
https://github.com/qemu/qemu/commit/40d225009efe17cad647b4b7424b77a3ace232f1
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic: Keep track of SGI sources

Right now the arm gic emulation doesn't keep track of the source of an
SGI (which apparently Linux guests don't use, or they're fine with
assuming CPU 0 always).

Add the necessary matrix on the GICState structure and maintain the data
when setting and clearing the pending state of an IRQ and make the state
visible to the guest.

Note that we always choose to present the source as the lowest-numbered
CPU in case multiple cores have signalled the same SGI number to a core
on the system.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aa7d461ae9dd79d35999f4710743cdf9dec88cef
      
https://github.com/qemu/qemu/commit/aa7d461ae9dd79d35999f4710743cdf9dec88cef
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic: Support setting/getting binary point reg

Add a binary_point field to the gic emulation structure and support
setting/getting this register now when we have it.  We don't actually
support interrupt grouping yet, oh well.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1b1d277cdaac98f25be249e7819aac781a35530
      
https://github.com/qemu/qemu/commit/a1b1d277cdaac98f25be249e7819aac781a35530
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M include/migration/vmstate.h

  Log Message:
  -----------
  vmstate: Add uint32 2D-array support

Add support for saving VMState of 2D arrays of uint32 values.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a9d477c4e3d614409a48d12f34624c2dd9f1ec2d
      
https://github.com/qemu/qemu/commit/a9d477c4e3d614409a48d12f34624c2dd9f1ec2d
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic: Add GICC_APRn state to the GICState

The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation.  This patch adds the missing state.

Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels.  This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3dc9fd5ac892b88b956d8c90c0e8de14c08e0fc
      
https://github.com/qemu/qemu/commit/c3dc9fd5ac892b88b956d8c90c0e8de14c08e0fc
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M rules.mak

  Log Message:
  -----------
  rules.mak: Support .cc as a C++ source file suffix

The A64 disassembler libvixl uses .cc as its suffix for
C++ source files, so add support for it (we already support
.cpp).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 3144f78b3f8d517d32641a7b606b67e7b3cc16f7
      
https://github.com/qemu/qemu/commit/3144f78b3f8d517d32641a7b606b67e7b3cc16f7
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M rules.mak

  Log Message:
  -----------
  rules.mak: Link with C++ if we have a C++ compiler

If we have a C++ compiler available, link with it, because we might be
linking some C++ files in. This allows us to include C++ object files
in the QEMU binary proper.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 878a735d009d1e90e96d6c5c6f9471aa4ec2ba65
      
https://github.com/qemu/qemu/commit/878a735d009d1e90e96d6c5c6f9471aa4ec2ba65
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    A disas/libvixl/LICENCE
    A disas/libvixl/README
    A disas/libvixl/a64/assembler-a64.h
    A disas/libvixl/a64/constants-a64.h
    A disas/libvixl/a64/cpu-a64.h
    A disas/libvixl/a64/decoder-a64.cc
    A disas/libvixl/a64/decoder-a64.h
    A disas/libvixl/a64/disasm-a64.cc
    A disas/libvixl/a64/disasm-a64.h
    A disas/libvixl/a64/instructions-a64.cc
    A disas/libvixl/a64/instructions-a64.h
    A disas/libvixl/globals.h
    A disas/libvixl/platform.h
    A disas/libvixl/utils.cc
    A disas/libvixl/utils.h

  Log Message:
  -----------
  disas: Add subset of libvixl sources for A64 disassembler

Add the subset of the libvixl sources that are needed for the
A64 disassembler support. These sources come from
https://github.com/armvixl/vixl commit 578645f14e122d2b
which is VIXL release 1.1.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 37fd5b53ba688e2a32d3966870361e667381ca95
      
https://github.com/qemu/qemu/commit/37fd5b53ba688e2a32d3966870361e667381ca95
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M disas/libvixl/a64/instructions-a64.h
    M disas/libvixl/globals.h
    M disas/libvixl/utils.h

  Log Message:
  -----------
  disas/libvixl: Fix upstream libvixl compilation issues

Fix various minor issues with upstream libvixl so that it will compile
successfully on the platforms QEMU cares about:
 * remove unused GBytes constant (it clashes with the glib headers)
 * fix suffixes on constants to use 'LL' for 64 bit constants so
   we can compile on 32 bit hosts

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 999b53ec8794f203964db3ecf939a3da5c4bc843
      
https://github.com/qemu/qemu/commit/999b53ec8794f203964db3ecf939a3da5c4bc843
  Author: Claudio Fontana <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M configure
    M disas.c
    M disas/Makefile.objs
    A disas/arm-a64.cc
    A disas/libvixl/Makefile.objs
    M include/disas/bfd.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  disas: Implement disassembly output for A64

Use libvixl to implement disassembly output in debug
logs for A64, for use with both AArch64 hosts and targets.

Signed-off-by: Claudio Fontana <address@hidden>
[PMM:
 * added support for target disassembly
 * switched to custom QEMUDisassembler so the output format
   matches what QEMU expects
 * make sure we correctly fall back to "just print hex"
   if we didn't build the AArch64 disassembler because of
   lack of a C++ compiler
 * rename from 'aarch64' to 'arm-a64' because this is a
   disassembler for the A64 instruction set
 * merge aarch64.c and aarch64-cxx.cc into one C++ file
 * simplify the aarch64.c<->aarch64-cxx.cc interface]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4e57af85272f98c28ccaaace040d2abb0ec85c4
      
https://github.com/qemu/qemu/commit/c4e57af85272f98c28ccaaace040d2abb0ec85c4
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M include/qemu/fifo8.h
    M util/fifo8.c

  Log Message:
  -----------
  util/fifo8: implement push/pop of multiple bytes

The patch adds functions fifo8_push_all() and fifo8_pop_buf() which
can be used respectively to push the content of a memory buffer to the
fifo and to pop multiple bytes obtaining a pointer to the fifo backing
buffer.

In addition, it implements fifo8_num_free() and fifo8_num_used() which
allow to check if a multi-byte operation can be performed.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 58892d4782bf516e8356e3adfe4fc9b10c397b2f
      
https://github.com/qemu/qemu/commit/58892d4782bf516e8356e3adfe4fc9b10c397b2f
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M util/fifo8.c

  Log Message:
  -----------
  util/fifo8: clear fifo head upon reset

To improve the predictability of fifo8_pop_buf(), the fifo head is set
to the start of data buffer upon a reset so that the first call to the
function will be able to retrieve all data in the fifo.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 22f90bcb2be021bb894438ddfeb10c75fa7502d8
      
https://github.com/qemu/qemu/commit/22f90bcb2be021bb894438ddfeb10c75fa7502d8
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/net/Makefile.objs
    A hw/net/allwinner_emac.c
    A include/hw/net/allwinner_emac.h

  Log Message:
  -----------
  hw/net: add support for Allwinner EMAC Fast Ethernet controller

This patch adds support for the Fast Ethernet MAC found on Allwinner
SoCs, together with a basic emulation of Realtek RTL8201CP PHY.

Since there is no public documentation of the Allwinner controller, the
implementation is based on Linux kernel driver.

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: db7dfd4c7e4450b10048a53ce67bcac6305ad383
      
https://github.com/qemu/qemu/commit/db7dfd4c7e4450b10048a53ce67bcac6305ad383
  Author: Beniamino Galvani <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/arm/allwinner-a10.c
    M hw/arm/cubieboard.c
    M include/hw/arm/allwinner-a10.h

  Log Message:
  -----------
  hw/arm/allwinner-a10: initialize EMAC

Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf
      
https://github.com/qemu/qemu/commit/69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf
  Author: Sebastian Huber <address@hidden>
  Date:   2014-02-08 (Sat, 08 Feb 2014)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  arm/zynq: Add software system reset via SCLR

Support software-driven system reset via the register in the SCLR.

Signed-off-by: Sebastian Huber <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8fa7574904793396694fa88834751a93bcdf4e10
      
https://github.com/qemu/qemu/commit/8fa7574904793396694fa88834751a93bcdf4e10
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-11 (Tue, 11 Feb 2014)

  Changed paths:
    M configure
    M default-configs/arm-softmmu.mak
    M disas.c
    M disas/Makefile.objs
    A disas/arm-a64.cc
    A disas/libvixl/LICENCE
    A disas/libvixl/Makefile.objs
    A disas/libvixl/README
    A disas/libvixl/a64/assembler-a64.h
    A disas/libvixl/a64/constants-a64.h
    A disas/libvixl/a64/cpu-a64.h
    A disas/libvixl/a64/decoder-a64.cc
    A disas/libvixl/a64/decoder-a64.h
    A disas/libvixl/a64/disasm-a64.cc
    A disas/libvixl/a64/disasm-a64.h
    A disas/libvixl/a64/instructions-a64.cc
    A disas/libvixl/a64/instructions-a64.h
    A disas/libvixl/globals.h
    A disas/libvixl/platform.h
    A disas/libvixl/utils.cc
    A disas/libvixl/utils.h
    M hw/arm/allwinner-a10.c
    M hw/arm/cubieboard.c
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M hw/intc/gic_internal.h
    M hw/misc/zynq_slcr.c
    M hw/net/Makefile.objs
    A hw/net/allwinner_emac.c
    M include/disas/bfd.h
    M include/hw/arm/allwinner-a10.h
    M include/hw/intc/arm_gic_common.h
    A include/hw/net/allwinner_emac.h
    M include/migration/vmstate.h
    M include/qemu/fifo8.h
    M rules.mak
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M tcg/tcg.h
    M util/fifo8.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140208' 
into staging

target-arm queue:
 * more A64 Neon instructions
 * AArch32 VCVTB and VCVTT ARMv8 instructions
 * fixes to inaccuracies in GIC emulation
 * libvixl disassembler for A64
 * Allwinner SoC ethernet controller
 * zynq software system reset support

# gpg: Signature made Sat 08 Feb 2014 15:53:05 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140208: (29 commits)
  arm/zynq: Add software system reset via SCLR
  hw/arm/allwinner-a10: initialize EMAC
  hw/net: add support for Allwinner EMAC Fast Ethernet controller
  util/fifo8: clear fifo head upon reset
  util/fifo8: implement push/pop of multiple bytes
  disas: Implement disassembly output for A64
  disas/libvixl: Fix upstream libvixl compilation issues
  disas: Add subset of libvixl sources for A64 disassembler
  rules.mak: Link with C++ if we have a C++ compiler
  rules.mak: Support .cc as a C++ source file suffix
  arm_gic: Add GICC_APRn state to the GICState
  vmstate: Add uint32 2D-array support
  arm_gic: Support setting/getting binary point reg
  arm_gic: Keep track of SGI sources
  arm_gic: Fix GIC pending behavior
  target-arm: Add support for AArch32 64bit VCVTB and VCVTT
  target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
  target-arm: A64: Add 2-reg-misc REV* instructions
  target-arm: A64: Add narrowing 2-reg-misc instructions
  target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/702f6df9602a...8fa757490479
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