[Qemu-commits] [qemu/qemu] bd1643: ahci: fix sysbus support

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: bd16430777cc3d25930e479fdbe290d92cec0888
      
https://github.com/qemu/qemu/commit/bd16430777cc3d25930e479fdbe290d92cec0888
  Author: Rob Herring <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M hw/ide/ahci.c

  Log Message:
  -----------
  ahci: fix sysbus support

Non-PCI AHCI support is broken due to assertion failures when trying
to convert AHCIState to a PCIDevice pointer as AHCIState can have
different container structs. Fix this by using the non-asserting object
cast and checking the returned pointer is not NULL.

The AddressSpace pointer is also being initialized to NULL and causing
dma_memory_map call to fail. Fix this by initializing to
address_space_memory for sysbus instances.

Also correct AHCI_VMSTATE to use the correct container SysbusAHCIState
for sysbus instances.

Signed-off-by: Rob Herring <address@hidden>
Message-id: address@hidden
[PMM: added linebreaks to fix overlong lines]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 22709e90a270a36418f1b1d5d3277016eec1edc2
      
https://github.com/qemu/qemu/commit/22709e90a270a36418f1b1d5d3277016eec1edc2
  Author: Rob Herring <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M hw/char/pl011.c

  Log Message:
  -----------
  pl011: reset the fifo when enabled or disabled

Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re-configured. This combined with the rx timeout interrupt not being
modeled results in no more rx interrupts.

Disabling the fifo is the recommended way to clear the tx fifo in the
TRM (section 3.3.8). The behavior in this case for the rx fifo is
undefined in the TRM, but having fifo contents to be maintained during
configuration changes is not likely expected behavior. Reseting the
fifo state when the fifo size is changed is the simplest solution.

Signed-off-by: Rob Herring <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ce8f0905a59232982c8a220169e11c14c73e7dea
      
https://github.com/qemu/qemu/commit/ce8f0905a59232982c8a220169e11c14c73e7dea
  Author: Rob Herring <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M hw/char/pl011.c

  Log Message:
  -----------
  pl011: fix UARTRSR accesses corrupting the UARTCR value

Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.

Signed-off-by: Rob Herring <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f72dbf3d2629be75d50b4c98816c360d82e8a848
      
https://github.com/qemu/qemu/commit/f72dbf3d2629be75d50b4c98816c360d82e8a848
  Author: Rob Herring <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M hw/char/pl011.c

  Log Message:
  -----------
  pl011: fix incorrect logic to set the RXFF flag

The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.

Signed-off-by: Rob Herring <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0a79bc87c3acf8364abf2d47b261fa898db15885
      
https://github.com/qemu/qemu/commit/0a79bc87c3acf8364abf2d47b261fa898db15885
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add saturating int ops (SQNEG/SQABS)

This mostly re-uses the existing NEON helpers with an additional two for
the 64 bit case. I also took the opportunity to add TCG_CALL_NO_RWG
options to the helpers as they don't modify globals (saturation flags
are in the CPU Environment).

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 09e037354b6f940c18f417f23355cffd23f4fde5
      
https://github.com/qemu/qemu/commit/09e037354b6f940c18f417f23355cffd23f4fde5
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)

Add the saturating accumulate operations USQADD and SUQADD
to the A64 instruction set. This completes coverage of A64 Neon.
These operations (which are unsigned + signed -> signed and
signed + unsigned -> unsigned) don't exist in the A32/T32
instruction set, so require a complete new set of helper functions.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 319c66d5abfb30553895589d24b70043639ad06d
      
https://github.com/qemu/qemu/commit/319c66d5abfb30553895589d24b70043639ad06d
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-19 (Wed, 19 Mar 2014)

  Changed paths:
    M hw/char/pl011.c
    M hw/ide/ahci.c
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140319' 
into staging

target-arm queue:
 * last few A64 Neon instructions
 * fix some PL011 UART bugs causing occasional serial lockups
 * fix the non-PCI AHCI device

# gpg: Signature made Wed 19 Mar 2014 12:00:59 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140319:
  target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
  target-arm: A64: Add saturating int ops (SQNEG/SQABS)
  pl011: fix incorrect logic to set the RXFF flag
  pl011: fix UARTRSR accesses corrupting the UARTCR value
  pl011: reset the fifo when enabled or disabled
  ahci: fix sysbus support

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/059b3527f022...319c66d5abfb