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[Qemu-commits] [qemu/qemu] 739b7a: bitops: provide an inline implementat


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 739b7a: bitops: provide an inline implementation of find_f...
Date: Wed, 18 Jun 2014 11:30:04 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 739b7a90754924a0f023e8bb865d247ad0a60311
      
https://github.com/qemu/qemu/commit/739b7a90754924a0f023e8bb865d247ad0a60311
  Author: Aurelien Jarno <address@hidden>
  Date:   2014-06-18 (Wed, 18 Jun 2014)

  Changed paths:
    M include/qemu/bitops.h

  Log Message:
  -----------
  bitops: provide an inline implementation of find_first_bit

find_first_bit has started to be used heavily in TCG code. The current
implementation based on find_next_bit is not optimal and can't be
optimized be the compiler if the bit array has a fixed size, which is
the case most of the time.

This new implementation does not use find_next_bit and is yet small
enough to be inlined.

Cc: Corentin Chary <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: d279279e2b5cd40dbcc863fb66a695990f304077
      
https://github.com/qemu/qemu/commit/d279279e2b5cd40dbcc863fb66a695990f304077
  Author: Petar Jovanovic <address@hidden>
  Date:   2014-06-18 (Wed, 18 Jun 2014)

  Changed paths:
    M linux-user/mips/target_cpu.h
    M linux-user/syscall.c
    M target-mips/cpu.h
    M target-mips/machine.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: implement UserLocal Register

>From MIPS documentation (Volume III):

UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.

The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.

This register only exists if the Config3-ULRI register field is set.

Privileged software may write this register with arbitrary information and
make it accessible to unprivileged software via register 29 (ULR) of the
RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a
1 to enable unprivileged access to the register.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2edaf21b939e...d279279e2b5c

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