[Qemu-commits] [qemu/qemu] 277c7a: PPC: KVM: Fix g3beige and mac99 when HV is loaded

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 277c7a4d717aedbcb253ca152ae4da67e4162470
      
https://github.com/qemu/qemu/commit/277c7a4d717aedbcb253ca152ae4da67e4162470
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  PPC: KVM: Fix g3beige and mac99 when HV is loaded

On PPC we have 2 different styles of KVM: PR and HV. HV can only virtualize
sPAPR guests while PR can virtualize everything that's reasonably close to
the host hardware platform.

As long as only one kernel module (PR or HV) is loaded, the "default" kvm type
is the module that's loaded. So if your hardware only supports PR mode you can
easily spawn a Mac VM.

However, if both HV and PR are loaded we default to HV mode. And in that case
the Mac machines have to explicitly ask for PR mode to get a working VM.

Fix this up by explicitly having the Mac machines ask for PR style KVM. This
fixes bootup of Mac VMs on systems where bot HV and PR kvm modules are loaded
for me.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2e14072f9e859272c7b94b8e189bd30bb4954aa1
      
https://github.com/qemu/qemu/commit/2e14072f9e859272c7b94b8e189bd30bb4954aa1
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  ppc: spapr-rtas - implement os-term rtas call

PAPR compliant guest calls this in absence of kdump. This finally
reaches the guest and can be handled according to the policies set by
higher level tools(like taking dump) for further analysis by tools like
crash.

Linux kernel calls ibm,os-term when extended property of os-term is set.
This makes sure that a return to the linux kernel is gauranteed.

Signed-off-by: Nikunj A Dadhania <address@hidden>
[agraf: reduce RTAS_TOKEN_MAX]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: fbdc200ac2d0d29e88ee6af9b77810c0f84265a6
      
https://github.com/qemu/qemu/commit/fbdc200ac2d0d29e88ee6af9b77810c0f84265a6
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Fix Stack Pointer Bug in PPC setup_rt_frame

The code that sets the stack frame back pointer is incorrect for
the setup_rt_frame() code; qemu will abort (SIGSEGV) in some
environments.  The setup_frame code  was fixed in commit
beb526b12134a6b6744125deec5a7fe24a8f92e3 but the setup_rt_frame
code was not.

Make the setup_rt_frame code consistent with the setup_frame
code.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7678108b134fc14d0a94fd13c0dd1129525c12d7
      
https://github.com/qemu/qemu/commit/7678108b134fc14d0a94fd13c0dd1129525c12d7
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Split PPC Trampoline Encoding from Register Save

Split the encoding of the PowerPC sigreturn trampoline from the saving of
register state onto the signal handler stack.  This will make it easier
in subsequent patches to deal with variations in the stack frame layouts between
32 and 64 bit PowerPC.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 61e75fecef17aff4b0ecef26b300b90de410aaa2
      
https://github.com/qemu/qemu/commit/61e75fecef17aff4b0ecef26b300b90de410aaa2
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Enable Signal Handlers on PPC64

Enable the 64-bit PowerPC signal handling code that was previously
disabled via #ifdefs.  Specifically:

  - Move the target_mcontext (register save area) structure and
    append it to the 64-bit target_sigcontext structure.  This
    provides the space on the stack for saving and restoring
    context.
  - Define the target_rt_sigframe for 64-bit.
  - Adjust the setup_frame and setup_rt_frame routines to properly
    select the target_mcontext area and trampoline within the stack
    frame; tthis is different for 32-bit and 64-bit implementations.
  - Adjust the do_setcontext stub for 64-bit so that it compiles
    without warnings.

The 64-bit signal handling code is still not functional after this
change; but the 32-bit code is.  Subsequent changes will address
specific issues with the 64-bit code.

Signed-off-by: Tom Musta <address@hidden>
[agraf: fix build on 32bit hosts, ppc64abi32]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8d6ab333ebf2751d2467bd7dae94a04742052e26
      
https://github.com/qemu/qemu/commit/8d6ab333ebf2751d2467bd7dae94a04742052e26
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Properly Dereference PPC64 ELFv1 Signal Handler Pointer

Properly dereference 64-bit PPC ELF V1 ABIT function pointers to signal 
handlers.
On this platform, function pointers are pointers to structures and the first 64
bits of such a structure contains the function's entry point.  The second 64 
bits
contains the TOC pointer, which must be placed into GPR 2.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 19774ec5c4019d1802b497d702e1eefd3c193e84
      
https://github.com/qemu/qemu/commit/19774ec5c4019d1802b497d702e1eefd3c193e84
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Implement do_setcontext for PPC64

Eliminate the stub for the do_setcontext() function for TARGET_PPC64.  The
implementation re-uses the existing TARGET_PPC32 code with the only change
being the computation of the address of the register save area.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 145855801a002aaf1310630df41425a6bc39cf47
      
https://github.com/qemu/qemu/commit/145855801a002aaf1310630df41425a6bc39cf47
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Handle PPC64 ELFv2 Function Pointers

Function pointers in the 64-bit ELFv2 PowerPC ABI are actual (internal)
entry point addresses.  However, when invoking a function via a function
pointer, GPR 12 must also be set to this address so that the TOC may be
handled properly.

Add this support to the invocation of a signal handler.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7d0cd464a756f3d47f308d7c47eb888b573a9fe4
      
https://github.com/qemu/qemu/commit/7d0cd464a756f3d47f308d7c47eb888b573a9fe4
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr_hcall.c

  Log Message:
  -----------
  hw/ppc/spapr_hcall.c: Fix typo in function names

Fix a typo in the names of a couple of functions
(s/resouce/resource/).

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ef9514431d33e52eb611f799670ca86618c1b7d9
      
https://github.com/qemu/qemu/commit/ef9514431d33e52eb611f799670ca86618c1b7d9
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h

  Log Message:
  -----------
  spapr: add uuid/host details to device tree

Useful for identifying the guest/host uniquely within the
guest. Adding following properties to the guest root node.

vm,uuid - uuid of the guest
host-model - Host model number
host-serial - Host machine serial number
hypervisor type - Tells its "kvm"

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 261265cc912b375649fcdf7aded0f87359dba544
      
https://github.com/qemu/qemu/commit/261265cc912b375649fcdf7aded0f87359dba544
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/mac_newworld.c
    M include/hw/ppc/ppc.h

  Log Message:
  -----------
  PPC: mac99: Move NVRAM to page boundary when necessary

When running KVM we have to adhere to host page boundaries for memory slots.
Unfortunately the NVRAM on mac99 is a 4k RAM hole inside of an MMIO flash
area.

So if our host is configured with 64k page size, we can't use the mac99 target
with KVM. This is a real shame, as this limitation is not really an issue - we
can easily map NVRAM somewhere else and at least Linux and Mac OS X use it
at their new location.

So in that emergency case when it's about failing to run at all and moving NVRAM
to a place it shouldn't be at, choose the latter.

This patch enables -M mac99 with KVM on 64k page size hosts.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: a21a7a701252717f05defee8a1a33d72c28fabb7
      
https://github.com/qemu/qemu/commit/a21a7a701252717f05defee8a1a33d72c28fabb7
  Author: Gonglei <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: fix possible memory leak

get_boot_devices_list() will malloc memory, spapr_finalize_fdt
doesn't free it.

Signed-off-by: Chenliang <address@hidden>
Signed-off-by: Gonglei <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 26a8c353bf0ffb485f4a68bea97efcef7d2bbaa3
      
https://github.com/qemu/qemu/commit/26a8c353bf0ffb485f4a68bea97efcef7d2bbaa3
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Move DT memory node rendering to a helper

This moves recurring bits of code related to address@hidden nodes
creation to a helper.

This makes use of the new helper for address@hidden

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 81014ac2b88b5fd275c33b463efe306668e920ed
      
https://github.com/qemu/qemu/commit/81014ac2b88b5fd275c33b463efe306668e920ed
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Use DT memory node rendering helper for other nodes

This finishes refactoring by using the spapr_populate_memory_node helper
for all nodes and removing leftovers from spapr_populate_memory().

This is not a part of the previous patch because the patches look
nicer apart.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7db8a127e373e468d1f61e46e01e50d1aa33e827
      
https://github.com/qemu/qemu/commit/7db8a127e373e468d1f61e46e01e50d1aa33e827
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Refactor spapr_populate_memory() to allow memoryless nodes

Current QEMU does not support memoryless NUMA nodes, however
actual hardware may have them so it makes sense to have a way
to emulate them in QEMU. This prepares SPAPR for that.

This moves 2 calls of spapr_populate_memory_node() into
the existing loop over numa nodes so first several nodes may
have no memory and this still will work.

If there is no numa configuration, the code assumes there is just
a single node at 0 and it has all the guest memory.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6010818c30ce9c796b4e22fd261fc6fea1cecbfc
      
https://github.com/qemu/qemu/commit/6010818c30ce9c796b4e22fd261fc6fea1cecbfc
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Split memory nodes to power-of-two blocks

Linux kernel expects nodes to have power-of-two size and
does WARN_ON if this is not the case:
[    0.041456] WARNING: at drivers/base/memory.c:115
which is:

===
        /* Validate blk_sz is a power of 2 and not less than section size */
        if ((block_sz & (block_sz - 1)) || (block_sz < MIN_MEMORY_BLOCK_SIZE)) {
        WARN_ON(1);
   block_sz = MIN_MEMORY_BLOCK_SIZE;
        }
===

This splits memory nodes into set of smaller blocks with
a size which is a power of two. This makes sure the start
address of every node is aligned to the node size.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: squash windows compile fix in]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b082d65a30078d176f8d1fbb3b99e1449fa2fcff
      
https://github.com/qemu/qemu/commit/b082d65a30078d176f8d1fbb3b99e1449fa2fcff
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Add a helper for node0_size calculation

In multiple places there is a node0_size variable calculation
which assumes that NUMA node #0 and memory node #0 are the same
things which they are not. Since we are going to change it and
do not want to change it in multiple places, let's make a helper.

This adds a spapr_node0_size() helper and makes use of it.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c3b4f589d86ae4a6b9f6c1e0587998bc525833da
      
https://github.com/qemu/qemu/commit/c3b4f589d86ae4a6b9f6c1e0587998bc525833da
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Fix ibm, associativity for memory nodes

We want the associtivity lists of memory and CPU nodes to match but
memory nodes have incorrect domain#3 which is zero for CPU so they won't
match.

This clears domain#3 in the list to match CPUs associtivity lists.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ea87616d6c44d998affef3d3b9fdfc49d14b8150
      
https://github.com/qemu/qemu/commit/ea87616d6c44d998affef3d3b9fdfc49d14b8150
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/core/loader.c
    M include/hw/loader.h

  Log Message:
  -----------
  loader: Add load_image_size() to replace load_image()

A subsequent patch to ppc/spapr needs to load the RTAS blob into
qemu memory rather than target memory (so it can later be copied
into the right spot at machine reset time).

I would use load_image() but it is marked deprecated because it
doesn't take a buffer size as argument, so let's add load_image_size()
that does.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[aik: fixed errors from checkpatch.pl]
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b7d1f77adaab790d20232df261d4e2ff6a77f556
      
https://github.com/qemu/qemu/commit/b7d1f77adaab790d20232df261d4e2ff6a77f556
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Locate RTAS and device-tree based on real RMA

We currently calculate the final RTAS and FDT location based on
the early estimate of the RMA size, cropped to 256M on KVM since
we only know the real RMA size at reset time which happens much
later in the boot process.

This means the FDT and RTAS end up right below 256M while they
could be much higher, using precious RMA space and limiting
what the OS bootloader can put there which has proved to be
a problem with some OSes (such as when using very large initrd's)

Fortunately, we do the actual copy of the device-tree into guest
memory much later, during reset, late enough to be able to do it
using the final RMA value, we just need to move the calculation
to the right place.

However, RTAS is still loaded too early, so we change the code to
load the tiny blob into qemu memory early on, and then copy it into
guest memory at reset time. It's small enough that the memory usage
doesn't matter.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[aik: fixed errors from checkpatch.pl, defined RTAS_MAX_ADDR]
Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: fix compilation on 32bit hosts]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3c902d4469304a9fd78cbef8a927d44b847cde3f
      
https://github.com/qemu/qemu/commit/3c902d4469304a9fd78cbef8a927d44b847cde3f
  Author: Bharat Bhushan <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  ppc: debug stub: Get trap instruction opcode from KVM

Get trap instruction opcode from KVM and this opcode will
be used for setting software breakpoint in following patch

Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c371c2e3e0d7ad979dc2bb9763223287fabdcc24
      
https://github.com/qemu/qemu/commit/c371c2e3e0d7ad979dc2bb9763223287fabdcc24
  Author: Bharat Bhushan <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  ppc: synchronize excp_vectors for injecting exception

This patch synchronizes env->excp_vectors[] with env->iovr[].
This is required for using the existing interrupt injection mechanism
for kvm.

Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8a0548f94edecb96acb9b7fb9106ccc821c4996f
      
https://github.com/qemu/qemu/commit/8a0548f94edecb96acb9b7fb9106ccc821c4996f
  Author: Bharat Bhushan <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  ppc: Add software breakpoint support

This patch allow insert/remove software breakpoint.

When QEMU is not able to handle debug exception then we inject
program exception to guest because for software breakpoint QEMU
uses a ehpriv-1 instruction;
So there cannot be any reason that we are in qemu with exit reason
KVM_EXIT_DEBUG  for guest set debug exception, only possibility is
guest executed ehpriv-1 privilege instruction and that's why we are
injecting program exception.

Signed-off-by: Bharat Bhushan <address@hidden>
[agraf: make deflect comment booke/book3s agnostic]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 88365d17d586bcf0d9f4432447db345f72278a2a
      
https://github.com/qemu/qemu/commit/88365d17d586bcf0d9f4432447db345f72278a2a
  Author: Bharat Bhushan <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  ppc: Add hw breakpoint watchpoint support

This patch adds hardware breakpoint and hardware watchpoint support
for ppc.

On BOOKE architecture we cannot share debug resources between QEMU
and guest because:
    When QEMU is using debug resources then debug exception must
    be always enabled. To achieve this we set MSR_DE and also set
    MSRP_DEP so guest cannot change MSR_DE.

    When emulating debug resource for guest we want guest
    to control MSR_DE (enable/disable debug interrupt on need).

    So above mentioned two configuration cannot be supported
    at the same time. So the result is that we cannot share
    debug resources between QEMU and Guest on BOOKE architecture.

In the current design QEMU gets priority over guest,
this means that if QEMU is using debug resources then guest
cannot use them and if guest is using debug resource then
qemu can overwrite them.

When QEMU is not able to handle debug exception then we inject program
exception to guest. Yes program exception NOT debug exception and the
reason is:
 1) QEMU and guest not sharing debug resources
 2) For software breakpoint QEMU uses a ehpriv-1 instruction;

 So there cannot be any reason that we are in qemu with exit reason
 KVM_EXIT_DEBUG  for guest set debug exception, only possibility is
 guest executed ehpriv-1 privilege instruction and that's why we are
 injecting program exception.

Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9674a356267ee9cf8230775f88c90c299a4affc9
      
https://github.com/qemu/qemu/commit/9674a356267ee9cf8230775f88c90c299a4affc9
  Author: Nikunj A Dadhania <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc/spapr: Fix MAX_CPUS to 255

MAX_CPUS 256 is inconsistent with qemu supporting upto 255 cpus. This
MAX_CPUS number was percolated back to "virsh capabilities" with wrong
max_cpus.

Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a7f23d0f8bfbe76864a6427c0e21fe794ab9b7ef
      
https://github.com/qemu/qemu/commit/a7f23d0f8bfbe76864a6427c0e21fe794ab9b7ef
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: rlwinm

The rlwinm specification includes the ROTL32 operation, which is defined
to be a left rotation of two copies of the least significant 32 bits of
the source GPR.

The current implementation is incorrect on 64-bit implementations in that
it rotates a single copy of the least significant 32 bits, padding with
zeroes in the most significant bits.

Fix the code to properly implement this ROTL32 operation.

Example:
R3 = F7487D82EC6F75DF
rlwinm 3,3,5,12,4

R3 expected : 8DEEBBFD880EBBFD
R3 actual   : 00000000880EBBFD (without this fix)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1c0a150f4bb60ce9af7b4b10f0deabdea1b22f93
      
https://github.com/qemu/qemu/commit/1c0a150f4bb60ce9af7b4b10f0deabdea1b22f93
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: rlwnm

The rlwnm specification includes the ROTL32 operation, which is defined
to be a left rotation of two copies of the least significant 32 bits of
the source GPR.

The current implementation is incorrect on 64-bit implementations in that
it rotates a single copy of the least significant 32 bits, padding with
zeroes in the most significant bits.

Fix the code to properly implement this ROTL32 operation.

Example:

R3 = 0000000000000002
R4 = 7FFFFFFFFFFFFFFF
rlwnm 3,3,4,31,16
R3 expected : 0000000100000001
R3 actual   : 0000000000000001 (without this patch)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6ea7b35c0294b1cc462e3225c4672de31300ed79
      
https://github.com/qemu/qemu/commit/6ea7b35c0294b1cc462e3225c4672de31300ed79
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: rlwimi

The rlwimi specification includes the ROTL32 operation, which is defined
to be a left rotation of two copies of the least significant 32 bits of
the source GPR.

The current implementation is incorrect on 64-bit implementations in that
it rotates a single copy of the least significant 32 bits, padding with
zeroes in the most significant bits.

Fix the code to properly implement this ROTL32 operation.

Also fix the special case of MB=31 and ME=0 to copy the entire contents
of the source GPR.

Examples:

R3 FFFFFFFFFFFFFFF0
rlwimi 3,3,29,14,1
R3 expected : 1FFFFFFE3FFFFFFE
R3 actual   : 000000003FFFFFFE (without this patch)

R3 ED7EB4DD824F0853
rlwimi 3,3,10,31,0
R3 expected : 3C214E09024F0853
R3 actual   : 00000000024F0853 (without this patch)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f11ebbf8d4308795129bc6651cf701b61b812abf
      
https://github.com/qemu/qemu/commit/f11ebbf8d4308795129bc6651cf701b61b812abf
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: mullwo

On 64-bit implementations, the mullwo result is the 64 bit product of
the signed 32 bit operands.  Fix the implementation to properly deposit
the upper 32 bits into the target register.

Example:

R3 0407DED115077586
R4 53778DF3CA992E09
mullwo 3,3,4
R3 expected : FB9D02730D7735B6
R3 actual   : 000000000D7735B6 (without this patch)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1fa74845f2bab36bfa37108b9054b53c1b8264b9
      
https://github.com/qemu/qemu/commit/1fa74845f2bab36bfa37108b9054b53c1b8264b9
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: mullw

For 64-bit implementations, the mullw result is the 64 bit product
of the sign-extended least significant 32 bits of the source
registers.

Fix the code to properly sign extend the source operands and produce
a 64 bit product.

Example:
R3 00000000002F37A0
R4 41C33D242F816715
mullw 3,3,4
R3 expected : 0008C3146AE0F020
R3 actual   : 000000006AE0F020 (without this patch)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9824d01d5d789a57d27360c0f5e8ee44955eb1d7
      
https://github.com/qemu/qemu/commit/9824d01d5d789a57d27360c0f5e8ee44955eb1d7
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/int_helper.c

  Log Message:
  -----------
  target-ppc: Bug Fix: mulldo OV Detection

Fix the code to properly detect overflow; the 128 bit signed
product must have all zeroes or all ones in the first 65 bits
otherwise OV should be set.

Example:

R3 45F086A5D5887509
R4 0000000000000002
mulldo 3,3,4

Should set XER[OV].

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 34a0fad10210a3e639a8e68323c923494047eefc
      
https://github.com/qemu/qemu/commit/34a0fad10210a3e639a8e68323c923494047eefc
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Bug Fix: srawi

For 64 bit implementations, the special case of a shift by zero
should result in the sign extension of the least significant 32 bits
of the source GPR (not a direct copy of the 64 bit source GPR).

Example:

R3 A6212433228F41DC
srawi 3,3,0
R3 expected : 00000000228F41DC
R3 actual   : A6212433228F41DC (without this patch)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4bc02e230d1e0fd41d2a892d81dcad56e3b3702d
      
https://github.com/qemu/qemu/commit/4bc02e230d1e0fd41d2a892d81dcad56e3b3702d
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/int_helper.c

  Log Message:
  -----------
  target-ppc: Bug Fix: srad

Fix the check for carry in the srad helper to properly construct
the mask -- a "1ULL" must be used (instead of "1") in order to
get the desired result.

Example:

R3 8000000000000000
R4 F3511AD4A2CD4C38
srad 3,3,4

Should *not* set XER[CA] but does without this patch.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7d0a07fa926436baf1238dcf68a55ea96cf5b9ab
      
https://github.com/qemu/qemu/commit/7d0a07fa926436baf1238dcf68a55ea96cf5b9ab
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c

  Log Message:
  -----------
  KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd

We now can call KVM_CHECK_EXTENSION on the kvm fd or on the vm fd, whereas
the vm version is more accurate when it comes to PPC KVM.

Add a helper to make the vm version available that falls back to the non-vm
variant if the vm one is not available yet to stay compatible.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6fd33a750214a866772dd77573cfa24c27ad956d
      
https://github.com/qemu/qemu/commit/6fd33a750214a866772dd77573cfa24c27ad956d
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  PPC: KVM: Use vm check_extension for pv hcall

To find out whether we support the KVM hypercall interface we need to ask KVM
on the VM level rather than the global KVM level, because Book3S HV KVM does
not support it and we play conservative when both HV and PR are loaded.

So instead, use the VM helper that falls back to global KVM enumeration. That
should cover all cases.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: d696760b43ca46c070f74fe12d90f38904232467
      
https://github.com/qemu/qemu/commit/d696760b43ca46c070f74fe12d90f38904232467
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/misc/macio/macio.c

  Log Message:
  -----------
  PPC: mac99: Fix core99 timer frequency

There is a special timer in the mac99 machine that we recently started
to emulate. Unfortunately we emulated it in the wrong frequency.

This patch adapts the frequency Mac OS X uses to evaluate results from
this timer, making calculations it bases off of it work.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: a8b0503701ed8de9353834b0955260f4d9f08640
      
https://github.com/qemu/qemu/commit/a8b0503701ed8de9353834b0955260f4d9f08640
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/nvram/mac_nvram.c
    M hw/ppc/mac.h

  Log Message:
  -----------
  PPC: mac_nvram: Remove unused functions

The macio_nvram_read and macio_nvram_write functions are never called,
just remove them.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: b19eae18c1cdf053fd85a39902cf77d8b561ef76
      
https://github.com/qemu/qemu/commit/b19eae18c1cdf053fd85a39902cf77d8b561ef76
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/nvram/mac_nvram.c

  Log Message:
  -----------
  PPC: mac_nvram: Allow 2 and 4 byte accesses

The NVRAM in our Core99 machine really supports 2byte and 4byte accesses
just as well as 1byte accesses. In fact, Mac OS X uses those.

Add support for higher register size granularities.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2d9907a3332888e43bc73fe9b98a32f8de662526
      
https://github.com/qemu/qemu/commit/2d9907a3332888e43bc73fe9b98a32f8de662526
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/nvram/mac_nvram.c

  Log Message:
  -----------
  PPC: mac_nvram: Split NVRAM into OF and OSX parts

Mac OS X (at least with -M mac99) searches for a valid NVRAM partition
of a special Apple type. If it can't find that partition in the first
half of NVRAM, it will look at the second half.

There are a few implications from this. The first is that we need to
split NVRAM into 2 halves - one for Open Firmware use, the other one for
Mac OS X. Without this split Mac OS X will just loop endlessly over the
second half trying to find a partition.

The other implication is that we should provide a specially crafted Mac
OS X compatible NVRAM partition on the second half that Mac OS X can
happily use as it sees fit.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: caae6c961107c4c55731a86572f9a1f53837636b
      
https://github.com/qemu/qemu/commit/caae6c961107c4c55731a86572f9a1f53837636b
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  PPC: Mac: Move tbfreq into local variable

We already expose the real CPU's tb frequency to the guest via fw_cfg. Soon
we will need to also expose it to the MacIO, so let's move it to a variable
that we can leverage every time we need the frequency.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: b981289c493c7ddabc1cdf7de99daa24642c7739
      
https://github.com/qemu/qemu/commit/b981289c493c7ddabc1cdf7de99daa24642c7739
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c

  Log Message:
  -----------
  PPC: Cuda: Use cuda timer to expose tbfreq to guest

Mac OS X calibrates a number of frequencies on bootup based on reading
tb values on bootup and comparing them to via cuda timer values.

The only variable we can really steer well (thanks to KVM) is the cuda
frequency. So let's use that one to fake Mac OS X into believing the
bus frequency is tbfreq * 4. That way Mac OS X will automatically
calculate the correct timebase frequency.

With this patch and the patch set I posted earlier I can successfully
run Mac OS X 10.2, 10.3 and 10.4 guests with -M mac99 on TCG and KVM.

Suggested-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 32420522482ffc20f8e9423af4f41f4e05ce3a56
      
https://github.com/qemu/qemu/commit/32420522482ffc20f8e9423af4f41f4e05ce3a56
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Fix config space corruption

When disabling MSI/MSIX via "ibm,change-msi" RTAS call, no check was made
if MSI or MSIX is actually supported and the MSI message was reset
unconditionally. If this happened on a device which does not support MSI
(but does support MSIX, otherwise "ibm,change-msi" would not be called),
this device would have PCIDevice::msi_cap field (MSI capability offset)
set to zero and writing a vector would actually clear PCI status.

This clears MSI message only if MSI or MSIX is present on a device.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 439ce1401bac1687c711cb6acf4ee8f3f457c05e
      
https://github.com/qemu/qemu/commit/439ce1401bac1687c711cb6acf4ee8f3f457c05e
  Author: Anton Blanchard <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/net/spapr_llan.c

  Log Message:
  -----------
  spapr-vlan: Don't touch last entry in buffer list

The last 8 bytes of the buffer list is defined to contain the number
of dropped frames. At the moment we use it to store rx entries,
which trips up ethtool -S:

rx_no_buffer: 9223380832981355136

Fix this by skipping the last buffer list entry.

Signed-off-by: Anton Blanchard <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ab92678d0a24e7ef8d4d93d18e5c0df8619874fe
      
https://github.com/qemu/qemu/commit/ab92678d0a24e7ef8d4d93d18e5c0df8619874fe
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Special Case of rlwimi Should Use Deposit

The special case of rlwimi where MB <= ME and SH = 31-ME can be implemented
with a single TCG deposit operation.  This replaces the less general case
of SH = MB = 0 and ME = 31.

Signed-off-by: Tom Musta <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8979c2f602357129fdf07a5cf8484ca430928b47
      
https://github.com/qemu/qemu/commit/8979c2f602357129fdf07a5cf8484ca430928b47
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Optimize rlwinm MB=0 ME=31

Optimize the special case of rlwinm where MB=0 and ME=31.  This can
be implemented as a 32-bit ROTL.

Signed-off-by: Tom Musta <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 57fca134bb64926f00ab8b14cdb8d345f395e07f
      
https://github.com/qemu/qemu/commit/57fca134bb64926f00ab8b14cdb8d345f395e07f
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Optimize rlwnm MB=0 ME=31

Optimize the special case of rlwnm where MB=0 and ME=31.  This can
be implemented using a ROTL.

Suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 03039e5ef0b92cb3ec89ff2caa5b57fa6bf12a88
      
https://github.com/qemu/qemu/commit/03039e5ef0b92cb3ec89ff2caa5b57fa6bf12a88
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Clean Up mullw

Eliminate the unecessary ext32s TCG operation and make the multiplication
operation explicitly 32 bit.

Signed-off-by: Tom Musta <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 269778769d4d24c511bc3d5f95eeb2e92dcf1868
      
https://github.com/qemu/qemu/commit/269778769d4d24c511bc3d5f95eeb2e92dcf1868
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Clean up mullwo

Simplify the implementation of mullwo.  For 64 bit CPUs, the result is
the concatenation of the upper and lower parts of the muls2_i32 operation,
which may be slightly better than deposit.  For 32 bit CPUs, the lower part
of the muls_i32 operation is moved into the target GPR.

Signed-off-by: Tom Musta <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 22ffad31d453a82aa290bf196f904580198e8e66
      
https://github.com/qemu/qemu/commit/22ffad31d453a82aa290bf196f904580198e8e66
  Author: Tom Musta <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Implement mulldo with TCG

Optimize mulldo by using the muls2_i64 operation rather than a helper.  
Eliminate
the obsolete helper code.

Signed-off-by: Tom Musta <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8c46f7ec85a4dd9663489b2fa2b425cd7b3653e1
      
https://github.com/qemu/qemu/commit/8c46f7ec85a4dd9663489b2fa2b425cd7b3653e1
  Author: Greg Kurz <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr_pci: map the MSI window in each PHB

On sPAPR, virtio devices are connected to the PCI bus and use MSI-X.
Commit cc943c36faa192cd4b32af8fe5edb31894017d35 has modified MSI-X
so that writes are made using the bus master address space and follow
the IOMMU path.

Unfortunately, the IOMMU address space address space does not have an
MSI window: the notification is silently dropped in unassigned_mem_write
instead of reaching the guest... The most visible effect is that all
virtio devices are non-functional on sPAPR since then. :(

This patch does the following:
1) map the MSI window into the IOMMU address space for each PHB
   - since each PHB instantiates its own IOMMU address space, we
     can safely map the window at a fixed address (SPAPR_PCI_MSI_WINDOW)
   - no real need to keep the MSI window setup in a separate function,
     the spapr_pci_msi_init() code moves to spapr_phb_realize().

2) kill the global MSI window as it is not needed in the end

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4a761ffa37d20a5d3ecbb95b45b4c42e54c8f18e
      
https://github.com/qemu/qemu/commit/4a761ffa37d20a5d3ecbb95b45b4c42e54c8f18e
  Author: Alexander Graf <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M default-configs/ppc64-softmmu.mak

  Log Message:
  -----------
  PPC: Fix default config ordering and add eTSEC for ppc64

We messed up the ordering in our default configs for PPC. The top entries
are generic entries, then come sections that indicate that features are only
in because of a special feature (such as PReP).

Fix the ordering again and while at it add eTSEC support to the ppc64 target
so that we can spawn eTSEC adapters with qemu-system-ppc64.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 85423d90c7bdbbae3d97ed3a12b5db79d00a3fb0
      
https://github.com/qemu/qemu/commit/85423d90c7bdbbae3d97ed3a12b5db79d00a3fb0
  Author: Anton Blanchard <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hypervisor property clashes with hypervisor node

dtc fails on a recent QEMU snapshot:

ERROR (name_properties): "name" property in /hypervisor#1 is incorrect 
("hypervisor" instead of base node name)

Looking at the device tree we have a hypervisor property:

# lsprop hypervisor
hypervisor       "kvm"

But we also have a hypervisor node, with a name that doesn't match:

# lsprop hypervisor#1/
name             "hypervisor"
compatible       "linux,kvm"
linux,phandle    7e5eb5d8 (2120136152)

Commit c08ce91d309c (spapr: add uuid/host details to device tree)
looks to have collided with an earlier patch. Remove the hypervisor
property.

Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2d6838e86ce942f886401818b48d77e575a5f7de
      
https://github.com/qemu/qemu/commit/2d6838e86ce942f886401818b48d77e575a5f7de
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-08 (Mon, 08 Sep 2014)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M default-configs/ppc64-softmmu.mak
    M hw/core/loader.c
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    M hw/net/spapr_llan.c
    M hw/nvram/mac_nvram.c
    M hw/ppc/mac.h
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M include/hw/loader.h
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/ppc.h
    M include/hw/ppc/spapr.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M linux-user/signal.c
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2014-09-08

Alexander Graf (11):
      PPC: KVM: Fix g3beige and mac99 when HV is loaded
      PPC: mac99: Move NVRAM to page boundary when necessary
      KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd
      PPC: KVM: Use vm check_extension for pv hcall
      PPC: mac99: Fix core99 timer frequency
      PPC: mac_nvram: Remove unused functions
      PPC: mac_nvram: Allow 2 and 4 byte accesses
      PPC: mac_nvram: Split NVRAM into OF and OSX parts
      PPC: Mac: Move tbfreq into local variable
      PPC: Cuda: Use cuda timer to expose tbfreq to guest
      PPC: Fix default config ordering and add eTSEC for ppc64

Alexey Kardashevskiy (7):
      spapr: Move DT memory node rendering to a helper
      spapr: Use DT memory node rendering helper for other nodes
      spapr: Refactor spapr_populate_memory() to allow memoryless nodes
      spapr: Split memory nodes to power-of-two blocks
      spapr: Add a helper for node0_size calculation
      spapr: Fix ibm, associativity for memory nodes
      spapr_pci: Fix config space corruption

Anton Blanchard (2):
      spapr-vlan: Don't touch last entry in buffer list
      hypervisor property clashes with hypervisor node

Benjamin Herrenschmidt (2):
      loader: Add load_image_size() to replace load_image()
      spapr: Locate RTAS and device-tree based on real RMA

Bharat Bhushan (4):
      ppc: debug stub: Get trap instruction opcode from KVM
      ppc: synchronize excp_vectors for injecting exception
      ppc: Add software breakpoint support
      ppc: Add hw breakpoint watchpoint support

Gonglei (1):
      spapr: fix possible memory leak

Greg Kurz (1):
      spapr_pci: map the MSI window in each PHB

Nikunj A Dadhania (3):
      ppc: spapr-rtas - implement os-term rtas call
      spapr: add uuid/host details to device tree
      ppc/spapr: Fix MAX_CPUS to 255

Peter Maydell (1):
      hw/ppc/spapr_hcall.c: Fix typo in function names

Tom Musta (20):
      linux-user: Fix Stack Pointer Bug in PPC setup_rt_frame
      linux-user: Split PPC Trampoline Encoding from Register Save
      linux-user: Enable Signal Handlers on PPC64
      linux-user: Properly Dereference PPC64 ELFv1 Signal Handler Pointer
      linux-user: Implement do_setcontext for PPC64
      linux-user: Handle PPC64 ELFv2 Function Pointers
      target-ppc: Bug Fix: rlwinm
      target-ppc: Bug Fix: rlwnm
      target-ppc: Bug Fix: rlwimi
      target-ppc: Bug Fix: mullwo
      target-ppc: Bug Fix: mullw
      target-ppc: Bug Fix: mulldo OV Detection
      target-ppc: Bug Fix: srawi
      target-ppc: Bug Fix: srad
      target-ppc: Special Case of rlwimi Should Use Deposit
      target-ppc: Optimize rlwinm MB=0 ME=31
      target-ppc: Optimize rlwnm MB=0 ME=31
      target-ppc: Clean Up mullw
      target-ppc: Clean up mullwo
      target-ppc: Implement mulldo with TCG

# gpg: Signature made Mon 08 Sep 2014 11:51:15 BST using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found

* remotes/agraf/tags/signed-ppc-for-upstream: (52 commits)
  hypervisor property clashes with hypervisor node
  PPC: Fix default config ordering and add eTSEC for ppc64
  spapr_pci: map the MSI window in each PHB
  target-ppc: Implement mulldo with TCG
  target-ppc: Clean up mullwo
  target-ppc: Clean Up mullw
  target-ppc: Optimize rlwnm MB=0 ME=31
  target-ppc: Optimize rlwinm MB=0 ME=31
  target-ppc: Special Case of rlwimi Should Use Deposit
  spapr-vlan: Don't touch last entry in buffer list
  spapr_pci: Fix config space corruption
  PPC: Cuda: Use cuda timer to expose tbfreq to guest
  PPC: Mac: Move tbfreq into local variable
  PPC: mac_nvram: Split NVRAM into OF and OSX parts
  PPC: mac_nvram: Allow 2 and 4 byte accesses
  PPC: mac_nvram: Remove unused functions
  PPC: mac99: Fix core99 timer frequency
  PPC: KVM: Use vm check_extension for pv hcall
  KVM: Add helper to run KVM_CHECK_EXTENSION on vm fd
  target-ppc: Bug Fix: srad
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f102f224556f...2d6838e86ce9