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[Qemu-commits] [qemu/qemu] 609ac1: tcg-sparc: Support addsub2_i64
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[Qemu-commits] [qemu/qemu] 609ac1: tcg-sparc: Support addsub2_i64 |
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Date: |
Tue, 30 Sep 2014 05:30:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 609ac1e16473e7dfc4dc54becde4b1902dbdf919
https://github.com/qemu/qemu/commit/609ac1e16473e7dfc4dc54becde4b1902dbdf919
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Support addsub2_i64
Signed-off-by: Richard Henderson <address@hidden>
Commit: 90379ca84ebe94b0adc08794d90ea1e196b2a724
https://github.com/qemu/qemu/commit/90379ca84ebe94b0adc08794d90ea1e196b2a724
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M disas/sparc.c
M include/elf.h
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Use ADDXC in addsub2_i64
On T4 and newer Sparc chips we have an add-with-carry insn
that takes its input from %xcc instead of %icc.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 321b6c058544c136341bf9cc6055f127f307f03e
https://github.com/qemu/qemu/commit/321b6c058544c136341bf9cc6055f127f307f03e
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Fix setcond_i32 uninitialized value
We failed to swap c1 and c2 correctly for NE c2 == 0.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 9d6a7a8542b17f5a98a60268d1c185bc81edb1a7
https://github.com/qemu/qemu/commit/9d6a7a8542b17f5a98a60268d1c185bc81edb1a7
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Use ADDXC in setcond_i64
Similar to the ADDC tricks we use in setcond_i32.
Signed-off-by: Richard Henderson <address@hidden>
Commit: c470b663f71ccbaa90006acb797a847c290329f9
https://github.com/qemu/qemu/commit/c470b663f71ccbaa90006acb797a847c290329f9
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M disas/sparc.c
M tcg/sparc/tcg-target.c
Log Message:
-----------
tcg-sparc: Rename ADDX/SUBX insns
The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9.
Standardizing on the v9 name makes things less confusing.
Signed-off-by: Richard Henderson <address@hidden>
Commit: de8301e542325fbc8accafbd8a3b50ae2554503e
https://github.com/qemu/qemu/commit/de8301e542325fbc8accafbd8a3b50ae2554503e
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M disas/sparc.c
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
Log Message:
-----------
tcg-sparc: Use UMULXHI instruction
Signed-off-by: Richard Henderson <address@hidden>
Commit: 9c53889ba3b7bda8c8e7dcee253e0a54fc4288f9
https://github.com/qemu/qemu/commit/9c53889ba3b7bda8c8e7dcee253e0a54fc4288f9
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M tcg/aarch64/tcg-target.c
M tcg/tcg-be-ldst.h
Log Message:
-----------
tcg-aarch64: Use 32-bit loads for qemu_ld_i32
The "old" qemu_ld opcode did not specify the size of the result,
and so we had to assume full register width. With the new opcodes,
we can narrow the result.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 58099c80664a2feed354f2ff8014350180becb5d
https://github.com/qemu/qemu/commit/58099c80664a2feed354f2ff8014350180becb5d
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M include/qemu/compiler.h
Log Message:
-----------
qemu/compiler: Define QEMU_ARTIFICIAL
The combination of always_inline + artificial allows tiny inline
functions to be written that do not interfere with debugging.
In particular, gdb will not step into an artificial function.
The always_inline attribute was introduced in gcc 4.2,
and the artificial attribute was introduced in gcc 4.3.
Signed-off-by: Richard Henderson <address@hidden>
Commit: b6c73a6d45b63926066aa71702d6017e7e43724a
https://github.com/qemu/qemu/commit/b6c73a6d45b63926066aa71702d6017e7e43724a
Author: Richard Henderson <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M tcg/tcg.h
Log Message:
-----------
tcg: Always enable TCGv type checking
Instead of using structures, which imply some amount of overhead
on certain ABIs, use pointer types.
This actually reduces the size of the binaries vs a NON-debug
build on ppc64 and x86_64, due to a reduction in the number of
sign-extension insns.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 45c270b1ea7987ab93e41ab095dd77370523e6b3
https://github.com/qemu/qemu/commit/45c270b1ea7987ab93e41ab095dd77370523e6b3
Author: Peter Maydell <address@hidden>
Date: 2014-09-30 (Tue, 30 Sep 2014)
Changed paths:
M disas/sparc.c
M include/elf.h
M include/qemu/compiler.h
M tcg/aarch64/tcg-target.c
M tcg/sparc/tcg-target.c
M tcg/sparc/tcg-target.h
M tcg/tcg-be-ldst.h
M tcg/tcg.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/tcg-next-201400729' into
staging
tcg updates
# gpg: Signature made Mon 29 Sep 2014 19:58:04 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
* remotes/rth/tags/tcg-next-201400729:
tcg: Always enable TCGv type checking
qemu/compiler: Define QEMU_ARTIFICIAL
tcg-aarch64: Use 32-bit loads for qemu_ld_i32
tcg-sparc: Use UMULXHI instruction
tcg-sparc: Rename ADDX/SUBX insns
tcg-sparc: Use ADDXC in setcond_i64
tcg-sparc: Fix setcond_i32 uninitialized value
tcg-sparc: Use ADDXC in addsub2_i64
tcg-sparc: Support addsub2_i64
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/29429c7244c7...45c270b1ea79
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