[Qemu-commits] [qemu/qemu] 800675: target-mips: Correct the handling of register #72 ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 800675f11742b6080e40d17b8d5f35d3a5fc5724
      
https://github.com/qemu/qemu/commit/800675f11742b6080e40d17b8d5f35d3a5fc5724
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/gdbstub.c

  Log Message:
  -----------
  target-mips: Correct the handling of register #72 on writes

Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it.  This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: c7d4d98ae7057467f48c02a11ad9120021976089
      
https://github.com/qemu/qemu/commit/c7d4d98ae7057467f48c02a11ad9120021976089
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/gdbstub.c

  Log Message:
  -----------
  target-mips: Make CP1.FIR read-only here too

CP1.FIR is read-only in hardware so gdbstub must respect it.  We already
respect it for CTC1 instructions, so do it here too.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 36b86e0dc2be93fc538fe7e11e0fda1a198f0135
      
https://github.com/qemu/qemu/commit/36b86e0dc2be93fc538fe7e11e0fda1a198f0135
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Add 5KEc and 5KEf MIPS64r2 processors

Add the 5KEc and 5KEf processors from MIPS Technologies that are the
original implementation of the MIPS64r2 ISA.

Silicon for these processors has never been taped out and no soft cores
were released even.  They do exist though, a CP0.PRId value has been
assigned and experimental RTLs produced at the time the MIPS64r2 ISA has
been finalized.  The settings introduced here faithfully reproduce that
hardware.

As far the implementation goes these processors are the same as the 5Kc
and the 5Kf CPUs respectively, except implementing the MIPS64r2 rather
than the original MIPS64 instruction set.  There must have been some
updates to the CP0 architecture as mandated by the ISA, such as the
addition of the EBase register, although I am not sure about the exact
details, no documentation has ever been produced for these processors.
The remaining parts of the microarchitecture, in particular the
pipeline, stayed unchanged.  Or to put it another way, the difference
between a 5K and a 5KE CPU corresponds to one between a 4K and a 4KE
CPU, except for the 64-bit rather than 32-bit ISA.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 8280b12c0e4b515d707509dde4ddde05d9bda4ef
      
https://github.com/qemu/qemu/commit/8280b12c0e4b515d707509dde4ddde05d9bda4ef
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/cpu.h

  Log Message:
  -----------
  target-mips: Make CP0.Config4 and CP0.Config5 registers signed

Make the data type used for the CP0.Config4 and CP0.Config5 registers
and their mask signed, for consistency with the remaining 32-bit CP0
registers, like CP0.Config0, etc.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 11f5ea105c06bec72e9bc9a700fa65d60afb5ec3
      
https://github.com/qemu/qemu/commit/11f5ea105c06bec72e9bc9a700fa65d60afb5ec3
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors

Add the M14K and M14Kc processors from MIPS Technologies that are the
original implementation of the microMIPS ISA.  They are dual instruction
set processors, implementing both the microMIPS and the standard MIPSr32
ISA.

These processors correspond to the M4K and 4KEc CPUs respectively,
except with support for the microMIPS instruction set added, support for
the MCU ASE added and two extra interrupt lines, making a total of 8
hardware interrupts plus 2 software interrupts.  The remaining parts of
the microarchitecture, in particular the pipeline, stayed unchanged.

The presence of the microMIPS ASE is is reflected in the configuration
added.  We currently have no support for the MCU ASE, including in
particular the ACLR, ASET and IRET instructions in either encoding, and
we have no support for the extra interrupt lines, including bits in
CP0.Status and CP0.Cause registers, so these features are not marked,
making our support diverge from real hardware.

Signed-off-by: Sandra Loosemore <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4386f08767240080334539ac0b07a8bfe30bffe9
      
https://github.com/qemu/qemu/commit/4386f08767240080334539ac0b07a8bfe30bffe9
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Enable vectored interrupt support for the 74Kf CPU

Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d75de74967f631a7d0b538d4b88f96f9c426bfe2
      
https://github.com/qemu/qemu/commit/d75de74967f631a7d0b538d4b88f96f9c426bfe2
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix formatting in `decode_extended_mips16_opc'

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85
      
https://github.com/qemu/qemu/commit/6225a4a0e39cb24e7b9e1d4d2c1a3e6eaee18e85
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: Fix formatting in `mips_defs'

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d2bfa6e6222baa0218bd0658499d38bac56ac34c
      
https://github.com/qemu/qemu/commit/d2bfa6e6222baa0218bd0658499d38bac56ac34c
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix formatting in `decode_opc'

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2b09f94cdbf5c54e2278d7f3aed2eceff3494790
      
https://github.com/qemu/qemu/commit/2b09f94cdbf5c54e2278d7f3aed2eceff3494790
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers

Move the call to `update_fcr31' in `helper_float_cvtw_s' after the
exception flag check, for consistency with the remaining helpers that do
it last too.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 51fdea945ae7adae8d7e4a1624e35bb7f714b58f
      
https://github.com/qemu/qemu/commit/51fdea945ae7adae8d7e4a1624e35bb7f714b58f
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Remove unused `FLOAT_OP' macro

Remove the `FLOAT_OP' macro, unused since commit
b6d96beda3a6cbf20a2d04a609eff78adebd8859 [Use temporary registers for
the MIPS FPU emulation.].

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 8fc605b8aa257feb3e69d44794a765bd492b573b
      
https://github.com/qemu/qemu/commit/8fc605b8aa257feb3e69d44794a765bd492b573b
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Restore the order of helpers

Restore the order of helpers that used to be: unary operations (generic,
then MIPS-specific), binary operations (generic, then MIPS-specific),
compare operations.  At one point FMA operations were inserted at a
random place in the file, disregarding the preexisting order, and later
on even more operations sprinkled across the file.  Revert the mess by
moving FMA operations to a new ternary class inserted after the binary
class and move the misplaced unary and binary operations to where they
belong.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: c3577479815f5bcf9d38993967bca2115af245d8
      
https://github.com/qemu/qemu/commit/c3577479815f5bcf9d38993967bca2115af245d8
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c
    M translate-all.c

  Log Message:
  -----------
  target-mips: Correct MIPS16/microMIPS branch size calculation

Correct MIPS16/microMIPS branch size calculation in PC adjustment
needed:

- to set the value of CP0.ErrorEPC at the entry to the reset exception,

- for the purpose of branch reexecution in the context of device I/O.

Follow the approach taken in `exception_resume_pc' for ordinary, Debug
and NMI exceptions.

MIPS16 and microMIPS branches can be 2 or 4 bytes in size and that has
to be reflected in calculation.  Original MIPS ISA branches, which is
where this code originates from, are always 4 bytes long, just as all
original MIPS ISA instructions.

Signed-off-by: Nathan Froyd <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: f88f79ec9df06d26d84e1d2e0c02d2634b4d8583
      
https://github.com/qemu/qemu/commit/f88f79ec9df06d26d84e1d2e0c02d2634b4d8583
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Correct the handling of writes to CP0.Status for MIPSr6

Correct these issues with the handling of CP0.Status for MIPSr6:

* only ignore the bit pattern of 0b11 on writes to CP0.Status.KSU, that
  is for processors that do implement Supervisor Mode, let the bit
  pattern be written to CP0.Status.UM:R0 freely (of course the value
  written to read-only CP0.Status.R0 will be discarded anyway); this is
  in accordance to the relevant architecture specification[1],

* check the newly written pattern rather than the current contents of
  CP0.Status for the KSU bits being 0b11,

* use meaningful macro names to refer to CP0.Status bits rather than
  magic numbers.

References:

[1] "MIPS Architecture For Programmers, Volume III: MIPS64 / microMIPS64
    Privileged Resource Architecture", MIPS Technologies, Inc., Document
    Number: MD00091, Revision 6.00, March 31, 2014, Table 9.45 "Status
    Register Field Descriptions", pp. 210-211.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 81a423e6c6d3ccaa79de4e58024369c660c1eeb4
      
https://github.com/qemu/qemu/commit/81a423e6c6d3ccaa79de4e58024369c660c1eeb4
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/gdbstub.c
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Correct the writes to Status and Cause registers via gdbstub

Make writes to CP0.Status and CP0.Cause have the same effect as
executing corresponding MTC0 instructions would in Kernel Mode.  Also
ignore writes in the user emulation mode.

Currently for requests from the GDB stub we write all the bits across
both registers, ignoring any read-only locations, and do not synchronise
the environment to evaluate side effects.  We also write these registers
in the user emulation mode even though a real kernel presents them as
read only.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 7215d7e7aea85699bf516c3e8d84f6a22584da35
      
https://github.com/qemu/qemu/commit/7215d7e7aea85699bf516c3e8d84f6a22584da35
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP

Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by
using register addition operations.

This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands
to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying
`rs' to `rd' verbatim.  This is not the case with OPC_ADDIU where a
sign-extension from bit #31 is made, unless in the uninteresting case of
`rs' being 0, losing the upper 32 bits of the value copied for any
proper 64-bit values.

This also serves as an optimization as one op is produced in generated
code rather than two (again, unless `rs' is 0, where it doesn't change
anything).

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 27e1fb13f21e132011673f0a39e17bcc97583633
      
https://github.com/qemu/qemu/commit/27e1fb13f21e132011673f0a39e17bcc97583633
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Output CP0.Config2-5 in the register dump

Include CP0.Config2 through CP0.Config5 registers in the register dump
produced with the `info registers' monitor command.  Align vertically
with the registers already output.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 90f12d735d66ac1196d9a2bced039a432eefc03d
      
https://github.com/qemu/qemu/commit/90f12d735d66ac1196d9a2bced039a432eefc03d
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix CP0.Config3.ISAOnExc write accesses

Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors.  This
bit is mandatory for any processor that implements the microMIPS
instruction set.  This bit is r/w for processors that implement both the
standard MIPS and the microMIPS instruction set.  This bit is r/o and
hardwired to 1 if only the microMIPS instruction set is implemented.

There is no other bit ever writable in CP0.Config3 so defining a
corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I
think an overkill.  Therefore make the ability to write the bit rely on
the presence of ASE_MICROMIPS set in the instruction flags.

The read-only case of the microMIPS instruction set being implemented
only can be added when we add support for such a configuration.  We do
not currently have such support, we have no instruction flag that would
control the presence of the standard MIPS instruction set nor any
associated code in instruction decoding.

This change is needed to boot a microMIPS Linux kernel successfully,
otherwise it hangs early on as interrupts are enabled and then the
exception handler invoked loops as its first instruction is interpreted
in the wrong execution mode and triggers another exception right away.
And then over and over again.

We already check the current setting of the CP0.Config3.ISAOnExc in
`set_hflags_for_handler' to set the ISA bit correctly on the exception
handler entry so it is the ability to set it that is missing only.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d9224450208e0de62323b64ace91f98bc31d6e2c
      
https://github.com/qemu/qemu/commit/d9224450208e0de62323b64ace91f98bc31d6e2c
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Tighten ISA level checks

Tighten ISA level checks down to MIPS II that many of our instructions
are missing.  Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: c48245f0c62405f27266fcf08722d8c290520418
      
https://github.com/qemu/qemu/commit/c48245f0c62405f27266fcf08722d8c290520418
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Correct 32-bit address space wrapping

Make sure the address space is unconditionally wrapped on 32-bit
processors, that is ones that do not implement at least the MIPS III
ISA.

Also make MIPS16 SAVE and RESTORE instructions use address calculation
rather than plain arithmetic operations for stack pointer manipulation
so that their semantics for stack accesses follows the architecture
specification.  That in particular applies to user software run on
64-bit processors with the CP0.Status.UX bit clear where the address
space is wrapped to 32 bits.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: cbb26c9a122c3f71fb53989817d406a2f6d08662
      
https://github.com/qemu/qemu/commit/cbb26c9a122c3f71fb53989817d406a2f6d08662
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/gdbstub.c

  Log Message:
  -----------
  target-mips: gdbstub: Clean up FPU register handling

Rewrite the FPU register access parts of `mips_cpu_gdb_read_register'
and `mips_cpu_gdb_write_register' for consistency between each other.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1d725ae952a14b30c84b7bc81b218b8ba77dd311
      
https://github.com/qemu/qemu/commit/1d725ae952a14b30c84b7bc81b218b8ba77dd311
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Also apply the CP0.Status mask to MTTC0

Make CP0.Status writes made with the MTTC0 instruction respect this
register's mask just like all the other places.  Also preserve the
current values of masked out bits.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 74797f40dc3e17633fea614f08c828020f755b28
      
https://github.com/qemu/qemu/commit/74797f40dc3e17633fea614f08c828020f755b28
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: Use the 5KEf processor for 64-bit emulation

Replace the 20Kc original MIPS64 ISA processor used for 64-bit user
emulation with the 5KEf processor that implements the MIPS64r2 ISA,
complementing the choice of the 24Kf processor for 32-bit emulation.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: bb962386b82c1b0e9e12fdb6b9bb62106bf1f822
      
https://github.com/qemu/qemu/commit/bb962386b82c1b0e9e12fdb6b9bb62106bf1f822
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/gdbstub.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Add missing calls to synchronise SoftFloat status

Add missing calls to synchronise the SoftFloat status with the CP1.FSCR:

+ for the rounding and flush-to-zero modes upon processor reset,

+ for the flush-to-zero mode on FSCR updates through the GDB stub.

Refactor code accordingly and remove the redundant RESTORE_ROUNDING_MODE
macro.

Signed-off-by: Thomas Schwinge <address@hidden>
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1a4d570017bf35d99340781ecb59dd3772464031
      
https://github.com/qemu/qemu/commit/1a4d570017bf35d99340781ecb59dd3772464031
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/msa_helper.c

  Log Message:
  -----------
  target-mips: Use local float status pointer across MSA macros

Reduce line wrapping throughout MSA helper macros by using a local float
status pointer rather than referring to the float status through the
environment each time.  No functional change.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 66991d1103562591eba6b801049720976317fe61
      
https://github.com/qemu/qemu/commit/66991d1103562591eba6b801049720976317fe61
  Author: Maciej W. Rozycki <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix DisasContext's ulri member initialization

Set DisasContext's ulri member to 0 or 1 as with other bool members.

Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 00fb4a118142650e7fa3d5007b197bc11fec6ea9
      
https://github.com/qemu/qemu/commit/00fb4a118142650e7fa3d5007b197bc11fec6ea9
  Author: Leon Alrae <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: convert single case switch into if statement

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>


  Commit: 8e5f7570448185297917d82d61ffbe27eff47a01
      
https://github.com/qemu/qemu/commit/8e5f7570448185297917d82d61ffbe27eff47a01
  Author: Leon Alrae <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M disas/mips.c

  Log Message:
  -----------
  disas/mips: remove unused mips_msa_control_names_numeric[32]

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>


  Commit: 8ef39152636d27b0d3340fcf030c3edb85a436cb
      
https://github.com/qemu/qemu/commit/8ef39152636d27b0d3340fcf030c3edb85a436cb
  Author: Leon Alrae <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M disas/mips.c

  Log Message:
  -----------
  disas/mips: disable unused mips16_to_32_reg_map[]

This array is used by print_mips16_insn_arg() which is guarded by #if 0.
Therefore doing the same with the array as it generates clang warnings.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: d4fa5354a246a1c6cb538a5d8ebcc21206d502fb
      
https://github.com/qemu/qemu/commit/d4fa5354a246a1c6cb538a5d8ebcc21206d502fb
  Author: Leon Alrae <address@hidden>
  Date:   2014-12-16 (Tue, 16 Dec 2014)

  Changed paths:
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: remove excp_names[] from linux-user as it is unused

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>


  Commit: 84afc4dd56648ac302c7b5a917e95ca7b1239695
      
https://github.com/qemu/qemu/commit/84afc4dd56648ac302c7b5a917e95ca7b1239695
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-17 (Wed, 17 Dec 2014)

  Changed paths:
    M disas/mips.c
    M linux-user/main.c
    M target-mips/cpu.h
    M target-mips/gdbstub.c
    M target-mips/helper.c
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c
    M translate-all.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into staging

* remotes/lalrae/tags/mips-20141216: (30 commits)
  target-mips: remove excp_names[] from linux-user as it is unused
  disas/mips: disable unused mips16_to_32_reg_map[]
  disas/mips: remove unused mips_msa_control_names_numeric[32]
  target-mips: convert single case switch into if statement
  target-mips: Fix DisasContext's ulri member initialization
  target-mips: Use local float status pointer across MSA macros
  target-mips: Add missing calls to synchronise SoftFloat status
  linux-user: Use the 5KEf processor for 64-bit emulation
  target-mips: Also apply the CP0.Status mask to MTTC0
  target-mips: gdbstub: Clean up FPU register handling
  target-mips: Correct 32-bit address space wrapping
  target-mips: Tighten ISA level checks
  target-mips: Fix CP0.Config3.ISAOnExc write accesses
  target-mips: Output CP0.Config2-5 in the register dump
  target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP
  target-mips: Correct the writes to Status and Cause registers via gdbstub
  target-mips: Correct the handling of writes to CP0.Status for MIPSr6
  target-mips: Correct MIPS16/microMIPS branch size calculation
  target-mips: Restore the order of helpers
  target-mips: Remove unused `FLOAT_OP' macro
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/339aaf5b7f26...84afc4dd5664