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[Qemu-commits] [qemu/qemu] f4aef4: target-tricore: Add instructions of R
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[Qemu-commits] [qemu/qemu] f4aef4: target-tricore: Add instructions of RRR1 opcode fo... |
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Mon, 16 Mar 2015 12:30:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f4aef476afc4cab9bb594975401f6902a57aa9b9
https://github.com/qemu/qemu/commit/f4aef476afc4cab9bb594975401f6902a57aa9b9
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
M target-tricore/tricore-opcodes.h
Log Message:
-----------
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as
first opcode
Add helpers:
* sub64_ssov: subs two 64 bit values and saturates the result.
* subr_h/_ssov: subs two halfwords from two words in q-format with rounding
/ and saturates each result independetly.
Add microcode generator:
* gen_sub64_d: adds two 64 bit values.
* gen_msub_h/s_h: multiply four halfwords, sub each result left justfied
from two word values / and saturate each result.
* gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied
from two words values in q-format / and saturate each
result.
* gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left
justfied from two halftwords/words values in q-format
/ and saturate each result.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 62e47b2e6d17020b78a676e086bf98cfeba595b7
https://github.com/qemu/qemu/commit/62e47b2e6d17020b78a676e086bf98cfeba595b7
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
M target-tricore/tricore-opcodes.h
Log Message:
-----------
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as
first opcode
Add helpers:
* msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a
64 bit q-format number and saturate.
* msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit
result.
* msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a
32 bit
q-format number and saturate.
* msubr_q: multiply two 32 bit q-format numbers and sub the result from a
32 bit
q-format number.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 068fac77c81b5d227903d0b7ecd108edff4eb0eb
https://github.com/qemu/qemu/commit/068fac77c81b5d227903d0b7ecd108edff4eb0eb
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
M target-tricore/tricore-opcodes.h
Log Message:
-----------
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as
first opcode
Add helpers helper_subadr_h/_ssov which subs one halfword and adds one
halfword, rounds / and saturates each half word independently.
Add microcode helper functions:
* gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the
first one word and add the second one word
/ and saturate each resulting word independetly.
* gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified
and sub from the first one word and add to
the second one word / and saturate each resulting
word independetly.
* gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified
and sub from the first one word and add to
the second one word, round both results / and
saturate each resulting word independetly.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 4d108fe33a3f04c9b9e5af1410b1e835d59de003
https://github.com/qemu/qemu/commit/4d108fe33a3f04c9b9e5af1410b1e835d59de003
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: Add instructions of RRRR opcode format
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: eb989d2545832deff386b23c904fc26f78303637
https://github.com/qemu/qemu/commit/eb989d2545832deff386b23c904fc26f78303637
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: Add instructions of RRRW opcode format
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: b724b012a4ea9877c5ddad254df63735a945618c
https://github.com/qemu/qemu/commit/b724b012a4ea9877c5ddad254df63735a945618c
Author: Bastian Koppelmann <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/cpu.h
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
Log Message:
-----------
target-tricore: Add instructions of SYS opcode format
This adds only the non trap instructions.
Signed-off-by: Bastian Koppelmann <address@hidden>
Commit: 17b11a1406fdc43b5022f32a6fbfcb005a353b38
https://github.com/qemu/qemu/commit/17b11a1406fdc43b5022f32a6fbfcb005a353b38
Author: Peter Maydell <address@hidden>
Date: 2015-03-16 (Mon, 16 Mar 2015)
Changed paths:
M target-tricore/cpu.h
M target-tricore/helper.h
M target-tricore/op_helper.c
M target-tricore/translate.c
M target-tricore/tricore-opcodes.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150316'
into staging
TriCore RRR1, RRRR, RRRW, and SYS instructions
# gpg: Signature made Mon Mar 16 15:55:24 2015 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"
* remotes/bkoppelmann/tags/pull-tricore-20150316:
target-tricore: Add instructions of SYS opcode format
target-tricore: Add instructions of RRRW opcode format
target-tricore: Add instructions of RRRR opcode format
target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as
first opcode
target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as
first opcode
target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as
first opcode
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/9575234db19d...17b11a1406fd
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