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[Qemu-commits] [qemu/qemu] fd5ecf: target-tricore: Add ISA v1.3.1 cpu an

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] fd5ecf: target-tricore: Add ISA v1.3.1 cpu and fix tc1796 ...
Date: Fri, 22 May 2015 09:30:08 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: fd5ecf31d4c48651de97c1aaf8771762753de9a7
      
https://github.com/qemu/qemu/commit/fd5ecf31d4c48651de97c1aaf8771762753de9a7
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/cpu.c

  Log Message:
  -----------
  target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 6d2afc8a5edc042e4e7c2ceb49f7cabe02aae793
      
https://github.com/qemu/qemu/commit/6d2afc8a5edc042e4e7c2ceb49f7cabe02aae793
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/cpu.c
    M target-tricore/cpu.h

  Log Message:
  -----------
  target-tricore: introduce ISA v1.6.1 feature

The aurix platform contains of several different cpu models and uses
the 1.6.1 ISA. This patch changes the generic aurix model to the more
specific tc27x cpu model and sets specific features.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: fcecf12684e1169653df72ed307ec2a82ca69b18
      
https://github.com/qemu/qemu/commit/fcecf12684e1169653df72ed307ec2a82ca69b18
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 62872ebc38d700ea30b0cd861e40703dccdcae2a
      
https://github.com/qemu/qemu/commit/62872ebc38d700ea30b0cd861e40703dccdcae2a
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add CMPSWP instructions of the v1.6.1 ISA

Those instruction were introduced in the new Aurix platform.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: ddd8cebe3106bdfb2681d8d283296199fd6c7417
      
https://github.com/qemu/qemu/commit/ddd8cebe3106bdfb2681d8d283296199fd6c7417
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add SWAPMSK instructions of the v1.6.1 ISA

Those instruction were introduced in the new Aurix platform.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e5c96c82bc529674b61eacd221734abc2674e264
      
https://github.com/qemu/qemu/commit/e5c96c82bc529674b61eacd221734abc2674e264
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA

This instruction was introduced by the new Aurix platform.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: bc3551c43308dd77bc1cc9a4e39962b2afd4dffc
      
https://github.com/qemu/qemu/commit/bc3551c43308dd77bc1cc9a4e39962b2afd4dffc
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add SYS_RESTORE instruction of the v1.6 ISA

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 9e14a7b24f4cff93da664fdcfecad41fbd229e2b
      
https://github.com/qemu/qemu/commit/9e14a7b24f4cff93da664fdcfecad41fbd229e2b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add FCALL instructions of the v1.6 ISA

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0e045f43c45f675711c3f6836118dc7eabcc2411
      
https://github.com/qemu/qemu/commit/0e045f43c45f675711c3f6836118dc7eabcc2411
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add FRET instructions of the v1.6 ISA

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 9371557115a734412974f8d4096cbe8a62ca2731
      
https://github.com/qemu/qemu/commit/9371557115a734412974f8d4096cbe8a62ca2731
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: bb2fa17f182ee0b45b53474f76679944fc891f04
      
https://github.com/qemu/qemu/commit/bb2fa17f182ee0b45b53474f76679944fc891f04
  Author: Peter Maydell <address@hidden>
  Date:   2015-05-22 (Fri, 22 May 2015)

  Changed paths:
    M target-tricore/cpu.c
    M target-tricore/cpu.h
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150522' 
into staging

TriCore v1.6.1 ISA and missing v1.6 instructions

# gpg: Signature made Fri May 22 16:02:45 2015 BST using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20150522:
  target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
  target-tricore: add FRET instructions of the v1.6 ISA
  target-tricore: add FCALL instructions of the v1.6 ISA
  target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
  target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
  target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
  target-tricore: add CMPSWP instructions of the v1.6.1 ISA
  target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
  target-tricore: introduce ISA v1.6.1 feature
  target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8b6db32a4ec4...bb2fa17f182e
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