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[Qemu-commits] [qemu/qemu] 7871ab: target-mips: Fix exceptions while UX=

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 7871ab: target-mips: Fix exceptions while UX=0
Date: Tue, 24 Nov 2015 10:00:09 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7871abb94c2f4adc39f2487f6edf5e69ba872a65
  Author: James Hogan <address@hidden>
  Date:   2015-11-24 (Tue, 24 Nov 2015)

  Changed paths:
    M target-mips/helper.c

  Log Message:
  target-mips: Fix exceptions while UX=0

Commit 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit address
wrapping") added a new hflag MIPS_HFLAG_AWRAP, which indicates that
64-bit addressing is disallowed in the current mode, so hflag users
don't need to worry about the complexities of working that out, for
example checking both MIPS_HFLAG_KSU and MIPS_HFLAG_UX.

However when exceptions are taken outside of exception level,
mips_cpu_do_interrupt() manipulates the env->hflags directly rather than
using compute_hflags() to update them, and this code wasn't updated
accordingly. As a result, when UX is cleared, MIPS_HFLAG_AWRAP is set,
but it doesn't get cleared on entry back into kernel mode due to an
exception. Kernel mode then cannot access the 64-bit segments resulting
in a nested exception loop. The same applies to errors and debug

Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
flag when necessary, according to compute_hflags().

Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
Signed-off-by: James Hogan <address@hidden>
Cc: Leon Alrae <address@hidden>
Cc: Aurelien Jarno <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>

  Commit: f93c3a8d0c0c1038dbe1e957eb8ab92671137975
  Author: Leon Alrae <address@hidden>
  Date:   2015-11-24 (Tue, 24 Nov 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/op_helper.c

  Log Message:
  target-mips: flush QEMU TLB when disabling 64-bit addressing

CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
Kernel/Supervisor/User Segments. If bit is cleared an access to
corresponding segment should generate Address Error Exception.

However, the guest may still be able to access some pages belonging to
the disabled 64-bit segment because we forget to flush QEMU TLB.

This patch fixes it.

Signed-off-by: Leon Alrae <address@hidden>

  Commit: 4b6eda626fdb8bf90472c6868d502a2ac09abeeb
  Author: Peter Maydell <address@hidden>
  Date:   2015-11-24 (Tue, 24 Nov 2015)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/op_helper.c

  Log Message:
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20151124' into staging

MIPS patches 2015-11-24

* Fixes for enabling/disabling 64-bit addressing

# gpg: Signature made Tue 24 Nov 2015 14:54:35 GMT using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"

* remotes/lalrae/tags/mips-20151124:
  target-mips: flush QEMU TLB when disabling 64-bit addressing
  target-mips: Fix exceptions while UX=0

Signed-off-by: Peter Maydell <address@hidden>

Compare: https://github.com/qemu/qemu/compare/d9636b6c2b53...4b6eda626fdb

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