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[Qemu-commits] [qemu/qemu] 9d6ba7: target-ppc: Use sensible POWER8/POWER
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[Qemu-commits] [qemu/qemu] 9d6ba7: target-ppc: Use sensible POWER8/POWER8E versions |
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Date: |
Tue, 02 Feb 2016 03:00:06 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9d6ba75df26d699a6e23d4817983bd029898f5c7
https://github.com/qemu/qemu/commit/9d6ba75df26d699a6e23d4817983bd029898f5c7
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/cpu-models.c
M target-ppc/cpu-models.h
Log Message:
-----------
target-ppc: Use sensible POWER8/POWER8E versions
We never released anything older than POWER8 DD2.0 and POWER8E DD2.1,
so let's use these versions, without that some firmware or Linux code
might fail to use some HW features that were non functional in earlier
internal only spins of the chip.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6a9620e60cc1b16dba9ee9d9d8cb374e4303c072
https://github.com/qemu/qemu/commit/6a9620e60cc1b16dba9ee9d9d8cb374e4303c072
Author: Mark Cave-Ayland <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/machine.c
Log Message:
-----------
target-ppc: use cpu_write_xer() helper in cpu_post_load
Otherwise some internal xer variables fail to get set post-migration.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 03c1280bf5dbb0b0f6125d17b8eebe9b9e97c8d8
https://github.com/qemu/qemu/commit/03c1280bf5dbb0b0f6125d17b8eebe9b9e97c8d8
Author: Mark Cave-Ayland <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ide/macio.c
M hw/ppc/mac.h
Log Message:
-----------
macio: use the existing IDEDMA aiocb to hold the active DMA aiocb
Currently the aiocb is held within MACIOIDEState, however the IDE core code
assumes that the current actvie DMA aiocb is held in aiocb in a few places,
e.g. ide_bus_reset() and ide_reset().
Switch over to using IDEDMA aiocb to store the aiocb for the current active
DMA request so that bus resets and restarts are handled correctly. As a
consequence we can now use ide_set_inactive() rather than handling its
functionality ourselves.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: John Snow <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bb37a8e8a3a7adef2ff395d3daf7384004441340
https://github.com/qemu/qemu/commit/bb37a8e8a3a7adef2ff395d3daf7384004441340
Author: Mark Cave-Ayland <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ide/macio.c
Log Message:
-----------
macio: add dma_active to VMStateDescription
Make sure that we include the value of dma_active in the migration stream.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Acked-by: John Snow <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 627be2f2836239e5fe437acdd96a8197d824af58
https://github.com/qemu/qemu/commit/627be2f2836239e5fe437acdd96a8197d824af58
Author: Mark Cave-Ayland <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/misc/macio/mac_dbdma.c
Log Message:
-----------
mac_dbdma: add DBDMA controller state to VMStateDescription
Make sure that we include the DBDMA controller state in the migration
stream.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ff57eae5f119ce2c6fbaab1313e3487969533fb9
https://github.com/qemu/qemu/commit/ff57eae5f119ce2c6fbaab1313e3487969533fb9
Author: Mark Cave-Ayland <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/misc/macio/cuda.c
Log Message:
-----------
cuda: add missing fields to VMStateDescription
Include some fields missed from the previous VMState conversion to the
migration stream, as well as the new SR_INT delay timer.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c920f7b42fc7834bae73a5fd146f58db18bb3f58
https://github.com/qemu/qemu/commit/c920f7b42fc7834bae73a5fd146f58db18bb3f58
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Small fixes to rtas_ibm_get_system_parameter, remove rtas_st_buffer
rtas_st_buffer() appears in spapr.h as though it were a widely used helper,
but in fact it is only used for saving data in a format used by
rtas_ibm_get_system_parameter(). This changes it to a local helper more
specifically for that function.
While we're there fix a couple of small defects in
rtas_ibm_get_system_parameter:
- For the string value SPLPAR_CHARACTERISTICS, it wasn't including the
terminating \0 in the length which it should according to LoPAPR
7.3.16.1
- It now checks that the supplied buffer has at least enough space for
the length of the returned data, and returns an error if it does not.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: f201987b843910ae929c5ed66700d910b29e9c15
https://github.com/qemu/qemu/commit/f201987b843910ae929c5ed66700d910b29e9c15
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Remove rtas_st_buffer_direct()
rtas_st_buffer_direct() is a not particularly useful wrapper around
cpu_physical_memory_write(). All the callers are in
rtas_ibm_configure_connector, where it's better handled by local helper.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 27ac3e06d59a2c37cdc5997f65ff82e104ec798a
https://github.com/qemu/qemu/commit/27ac3e06d59a2c37cdc5997f65ff82e104ec798a
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Remove abuse of rtas_ld() in h_client_architecture_support
h_client_architecture_support() uses rtas_ld() for general purpose memory
access, despite the fact that it's not an RTAS routine at all and rtas_ld
makes things more awkward.
Clean this up by replacing rtas_ld() calls with appropriate ldXX_phys()
calls.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: 16c25aef5362c6dd99c54fec78936ec3c10dc513
https://github.com/qemu/qemu/commit/16c25aef5362c6dd99c54fec78936ec3c10dc513
Author: Bharata B Rao <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Don't create ibm,dynamic-reconfiguration-memory w/o DR LMBs
If guest doesn't have any dynamically reconfigurable (DR) logical memory
blocks (LMB), then we shouldn't create ibm,dynamic-reconfiguration-memory
device tree node.
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f9ab1e87edae8a72ae2a65fad658a77ad15d4da0
https://github.com/qemu/qemu/commit/f9ab1e87edae8a72ae2a65fad658a77ad15d4da0
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M target-ppc/cpu.h
M target-ppc/translate_init.c
Log Message:
-----------
ppc: Clean up error handling in ppc_set_compat()
Current ppc_set_compat() returns -1 for errors, and also (unconditionally)
reports an error message. The caller in h_client_architecture_support()
may then report it again using an outdated fprintf().
Clean this up by using the modern error reporting mechanisms. Also add
strerror(errno) to the error message.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 569f49671dde92bb2bf55d4d2f32537e04c3c7c8
https://github.com/qemu/qemu/commit/569f49671dde92bb2bf55d4d2f32537e04c3c7c8
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error handling of spapr_cpu_init()
Currently spapr_cpu_init() is hardcoded to handle any errors as fatal.
That works for now, since it's only called from initial setup where an
error here means we really can't proceed.
However, we'll want to handle this more flexibly for cpu hotplug in future
so generalize this using the error reporting infrastructure. While we're
at it make a small cleanup in a related part of ppc_spapr_init() to use
error_report() instead of an old-style explicit fprintf().
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 7c150d6f04f23dbcb4402bd5e16a8c86757a727a
https://github.com/qemu/qemu/commit/7c150d6f04f23dbcb4402bd5e16a8c86757a727a
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error handling in spapr_validate_node_memory()
Use error_setg() and return an error, rather than using an explicit exit().
Also improve messages, and be more explicit about which constraint failed.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Bharata B Rao <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 14c6a8949799573570b62cf50c519a3b34a2499b
https://github.com/qemu/qemu/commit/14c6a8949799573570b62cf50c519a3b34a2499b
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error handling in spapr_vga_init()
Use error_setg() to return an error rather than an explicit exit().
Previously it was an exit(0) instead of a non-zero exit code, which was
simply a bug. Also improve the error message.
While we're at it change the type of spapr_vga_init() to bool since that's
how we're using it anyway.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: adf9ac50dbb183f83c4f430738e0271a1a2039aa
https://github.com/qemu/qemu/commit/adf9ac50dbb183f83c4f430738e0271a1a2039aa
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_rtas.c
Log Message:
-----------
pseries: Clean up error handling in spapr_rtas_register()
The errors detected in this function necessarily indicate bugs in the rest
of the qemu code, rather than an external or configuration problem.
So, a simple assert() is more appropriate than any more complex error
reporting.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 1e49182d05016756be3c7c43a4934f5104717512
https://github.com/qemu/qemu/commit/1e49182d05016756be3c7c43a4934f5104717512
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error handling in xics_system_init()
Use the error handling infrastructure to pass an error out from
try_create_xics() instead of assuming &error_abort - the caller is in a
better position to decide on error handling policy.
Also change the error handling from an &error_abort to &error_fatal, since
this occurs during the initial machine construction and could be triggered
by bad configuration rather than a program error.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: d54e4d7659ebecd0e1fa7ffc3e954197e09f8a1f
https://github.com/qemu/qemu/commit/d54e4d7659ebecd0e1fa7ffc3e954197e09f8a1f
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error reporting in ppc_spapr_init()
This function includes a number of explicit fprintf()s for errors.
Change these to use error_report() instead.
Also replace the single exit(EXIT_FAILURE) with an explicit exit(1), since
the latter is the more usual idiom in qemu by a large margin.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 98a5d100c2dfcc2b6daefd8c176eb34055e5b38d
https://github.com/qemu/qemu/commit/98a5d100c2dfcc2b6daefd8c176eb34055e5b38d
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Clean up error reporting in htab migration functions
The functions for migrating the hash page table on pseries machine type
(htab_save_setup() and htab_load()) can report some errors with an
explicit fprintf() before returning an appropriate error code. Change some
of these to use error_report() instead. htab_save_setup() is omitted for
now to avoid conflicts with some other in-progress work.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Commit: 3a4b791b4c13e02537a5cc572fa3de70bc5f68da
https://github.com/qemu/qemu/commit/3a4b791b4c13e02537a5cc572fa3de70bc5f68da
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/kvm.c
Log Message:
-----------
target-ppc: kvm: fix floating point registers sync on little-endian hosts
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits
of the 32 first VSX registers. So if you have:
VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00
then
FPR31 = (uint64) 0x0102030405060708
The kernel stores the VSX registers in the fp_state struct following the
host endian element ordering.
On big-endian:
fp_state.fpr[31][0] = 0x0102030405060708
fp_state.fpr[31][1] = 0x090a0b0c0d0e0f00
On little-endian:
fp_state.fpr[31][0] = 0x090a0b0c0d0e0f00
fp_state.fpr[31][1] = 0x0102030405060708
The KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls preserve this ordering, but
QEMU considers it as big-endian and always copies element [0] to the
fpr[] array and element [1] to the vsr[] array. This does not work with
little-endian hosts, and you will get:
(qemu) p $f31
0x90a0b0c0d0e0f00
instead of:
(qemu) p $f31
0x102030405060708
This patch fixes the element ordering for little-endian hosts.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 376dbce0e3abe456fb8c7a3cd40dc369f8b33d30
https://github.com/qemu/qemu/commit/376dbce0e3abe456fb8c7a3cd40dc369f8b33d30
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/gdbstub.c
Log Message:
-----------
target-ppc: rename and export maybe_bswap_register()
This helper will be used to support FP, Altivec and VSX registers when
the guest is little-endian.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 385abeb3e356452eace44f3fe15e18c2532dcaa7
https://github.com/qemu/qemu/commit/385abeb3e356452eace44f3fe15e18c2532dcaa7
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: gdbstub: fix float registers for little-endian guests
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 87601e2d5c22d9c1fef0e09978d377f46336c1db
https://github.com/qemu/qemu/commit/87601e2d5c22d9c1fef0e09978d377f46336c1db
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: gdbstub: introduce avr_need_swap()
This helper will be used to support Altivec registers in little-endian guests.
This patch does not change functionnality.
Note: I had to put the helper some lines away from the gdb_*_avr_reg()
routines to get a more readable patch.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ea499e71506c91aa259a7fdccf1d6b2022f5b530
https://github.com/qemu/qemu/commit/ea499e71506c91aa259a7fdccf1d6b2022f5b530
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: gdbstub: fix altivec registers for little-endian guests
Altivec registers are 128-bit wide. They are stored in memory as two
64-bit values that must be byteswapped when the guest is little-endian.
Let's reuse the ppc_maybe_bswap_register() helper for this.
We also need to fix the ordering of the 64-bit elements according to
the target endianness, for both system and user mode.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 95f5b540abd964ac3bc9c63434d07681a5a175eb
https://github.com/qemu/qemu/commit/95f5b540abd964ac3bc9c63434d07681a5a175eb
Author: Greg Kurz <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: gdbstub: fix spe registers for little-endian guests
Let's reuse the ppc_maybe_bswap_register() helper, like we already do
with the general registers.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1438eff302cbc6c85d477fd7181b8a9aeea2efd7
https://github.com/qemu/qemu/commit/1438eff302cbc6c85d477fd7181b8a9aeea2efd7
Author: Anton Blanchard <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M configure
A gdb-xml/power-vsx.xml
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: gdbstub: Add VSX support
Add the XML and functions to get and set VSX registers.
Signed-off-by: Anton Blanchard <address@hidden>
(fixed little-endian guests)
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ecbc25fa86ce44cf5aea94adaf79ea8428f12f4b
https://github.com/qemu/qemu/commit/ecbc25fa86ce44cf5aea94adaf79ea8428f12f4b
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
pseries: Allow TCG h_enter to work with hotplugged memory
The implementation of the H_ENTER hypercall for PAPR guests needs to
enforce correct access attributes on the inserted HPTE. This means
determining if the HPTE's real address is a regular RAM address (which
requires attributes for coherent access) or an IO address (which requires
attributes for cache-inhibited access).
At the moment this check is implemented with (raddr < machine->ram_size),
but that only handles addresses in the base RAM area, not any hotplugged
RAM.
This patch corrects the problem with a new helper.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Commit: ff472a5badf8e6d964455de39ca67ea3a7758dea
https://github.com/qemu/qemu/commit/ff472a5badf8e6d964455de39ca67ea3a7758dea
Author: Alyssa Milburn <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/misc/macio/cuda.c
Log Message:
-----------
cuda.c: return error for unknown commands
This avoids MacsBug hanging at startup in the absence of ADB mouse
input, by replying with an error (which is also what MOL does) when
it sends an unknown command (0x1c).
Signed-off-by: Alyssa Milburn <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 98ae3b27d57b59c6dc9a74e6351e339523c16def
https://github.com/qemu/qemu/commit/98ae3b27d57b59c6dc9a74e6351e339523c16def
Author: Programmingkid <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/pci-host/uninorth.c
Log Message:
-----------
uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register
Darwin/OS X use the undocumented kMacRISCPCIAddressSelect (0x48) to
configure PCI memory space size for mac99 machines. Without this
register, warnings similar to below are emitted to the console during boot:
AppleMacRiscPCI: bad range 2(80000000:01000000)
AppleMacRiscPCI: bad range 2(81000000:00001000)
AppleMacRiscPCI: bad range 2(81080000:00080000)
Based upon the algorithm in Darwin's AppleMacRiscPCI.cpp driver, set the
kMacRISCPCIAddressSelect register so that Darwin considers the PCI
memory space to be at 0x80000000 (size 0x10000000) which matches that
currently used by QEMU and OpenBIOS.
Signed-off-by: John Arbuckle <address@hidden>
Tested-by: Mark Cave-Ayland <address@hidden>
[commit message and comment revised as suggested by Mark Cave-Ayland]
Signed-off-by: David Gibson <address@hidden>
Commit: 512fe19330f60ebcb79a3f440411d3a1c7f6e11a
https://github.com/qemu/qemu/commit/512fe19330f60ebcb79a3f440411d3a1c7f6e11a
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/kvm_ppc.h
Log Message:
-----------
target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
This stub function is in the !KVM ifdef in target-ppc/kvm_ppc.h. However
no such function exists on the KVM side, or is ever used.
I think this originally referenced a function which read host page size
information from /proc, for we we now use the KVM GET_SMMU_INFO extension
instead.
In any case, it has no function now, so remove it.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: 7ef23068bfa413605de8ae7e3e654d9198369fa8
https://github.com/qemu/qemu/commit/7ef23068bfa413605de8ae7e3e654d9198369fa8
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
M target-ppc/kvm.c
M target-ppc/mmu-hash32.c
M target-ppc/mmu-hash32.h
M target-ppc/mmu-hash64.c
M target-ppc/mmu-hash64.h
M target-ppc/mmu_helper.c
Log Message:
-----------
target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to PowerPCCPU
Like a lot of places these files include a mixture of functions taking
both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step
closer to cleaning this up by standardizing on PowerPCCPU, except for the
helper_* functions which are called with the CPUPPCState * from tcg.
Callers and some related functions are updated as well, the boundaries of
what's changed here are a bit arbitrary.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: bcd81230037f60a2fc9c2e903f8f07db68f86ce8
https://github.com/qemu/qemu/commit/bcd81230037f60a2fc9c2e903f8f07db68f86ce8
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/kvm.c
M target-ppc/mmu-hash64.c
M target-ppc/mmu-hash64.h
M target-ppc/mmu_helper.c
Log Message:
-----------
target-ppc: Rework ppc_store_slb
ppc_store_slb updates the SLB for PPC cpus with 64-bit hash MMUs.
Currently it takes two parameters, which contain values encoded as the
register arguments to the slbmte instruction, one register contains the
ESID portion of the SLBE and also the slot number, the other contains the
VSID portion of the SLBE.
We're shortly going to want to do some SLB updates from other code where
it is more convenient to supply the slot number and ESID separately, so
rework this function and its callers to work this way.
As a bonus, this slightly simplifies the emulation of segment registers for
when running a 32-bit OS on a 64-bit CPU.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: cd6a9bb6e977864b1b7ec21b983fa0678b4b82e9
https://github.com/qemu/qemu/commit/cd6a9bb6e977864b1b7ec21b983fa0678b4b82e9
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/machine.c
M target-ppc/mmu-hash64.c
Log Message:
-----------
target-ppc: Rework SLB page size lookup
Currently, the ppc_hash64_page_shift() function looks up a page size based
on information in an SLB entry. It open codes the bit translation for
existing CPUs, however different CPU models can have different SLB
encodings. We already store those in the 'sps' table in CPUPPCState, but
we don't currently enforce that that actually matches the logic in
ppc_hash64_page_shift.
This patch reworks lookup of page size from SLB in several ways:
* ppc_store_slb() will now fail (triggering an illegal instruction
exception) if given a bad SLB page size encoding
* On success ppc_store_slb() stores a pointer to the relevant entry in
the page size table in the SLB entry. This is looked up directly from
the published table of page size encodings, so can't get out ot sync.
* ppc_hash64_htab_lookup() and others now use this precached page size
information rather than decoding the SLB values
* Now that callers have easy access to the page_shift,
ppc_hash64_pte_raddr() amounts to just a deposit64(), so remove it and
have the callers use deposit64() directly.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: be18b2b53ebbf2eb3f00e7890d0b9ff8b58d22bf
https://github.com/qemu/qemu/commit/be18b2b53ebbf2eb3f00e7890d0b9ff8b58d22bf
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/mmu-hash64.c
Log Message:
-----------
target-ppc: Use actual page size encodings from HPTE
At present the 64-bit hash MMU code uses information from the SLB to
determine the page size of a translation. We do need that information to
correctly look up the hash table. However the MMU also allows a
possibly larger page size to be encoded into the HPTE itself, which is used
to populate the TLB. At present qemu doesn't check that, and so doesn't
support the MPSS "Multiple Page Size per Segment" feature.
This makes a start on allowing this, by adding an hpte_page_shift()
function which looks up the page size of an HPTE. We use this to validate
page sizes encodings on faults, and populate the qemu TLB with larger
page sizes when appropriate.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: 041d95f42e39ed1d3a029332cab9966889f0aeb3
https://github.com/qemu/qemu/commit/041d95f42e39ed1d3a029332cab9966889f0aeb3
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/mmu_helper.c
Log Message:
-----------
target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
ppc_tlb_invalidate_one() has a big switch handling many different MMU
types. However, most of those branches can never be reached:
It is called from 3 places: from remove_hpte() and h_protect() in
spapr_hcall.c (which always has a 64-bit hash MMU type), and from
helper_tlbie() in mmu_helper.c.
Calls to helper_tlbie() are generated from gen_tlbiel, gen_tlbiel and
gen_tlbiva. The first two are only used with the PPC_MEM_TLBIE flag,
set only with 32-bit or 64-bit hash MMU models, and gen_tlbiva() is
used only on 440 and 460 models with the BookE mmu model.
These means the exhaustive list of MMU types which may call
ppc_tlb_invalidate_one() is: POWERPC_MMU_SOFT_6xx, POWERPC_MMU_601,
POWERPC_MMU_32B, POWERPC_MMU_SOFT_74xx, POWERPC_MMU_64B, POWERPC_MMU_2_03,
POWERPC_MMU_2_06, POWERPC_MMU_2_07 and POWERPC_MMU_BOOKE.
Clean up by removing logic for all other MMU types from
ppc_tlb_invalidate_one().
This means that ppc4xx_tlb_invalidate_virt() now has no callers, or rather,
makes it obvious that it has no callers. So, we remove that function as
well.
Signed-off-by: David Gibson <address@hidden>
Commit: 4693364f31016cc08d79d1673c3f735a4f95fd89
https://github.com/qemu/qemu/commit/4693364f31016cc08d79d1673c3f735a4f95fd89
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/helper.h
M target-ppc/mmu_helper.c
M target-ppc/translate.c
Log Message:
-----------
target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
Currently both the tlbiva instruction (used on 44x chips) and the tlbie
instruction (used on hash MMU chips) are both handled via
ppc_tlb_invalidate_one(). This is silly, because they're invoked from
different places, and do different things.
Clean this up by separating out the tlbiva instruction into its own
handling. In fact the implementation is only a stub anyway.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: 61a36c9b5a12889994e6c45f4a175efcd63936db
https://github.com/qemu/qemu/commit/61a36c9b5a12889994e6c45f4a175efcd63936db
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
M target-ppc/mmu-hash64.c
M target-ppc/mmu-hash64.h
Log Message:
-----------
target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
When HPTEs are removed or modified by hypercalls on spapr, we need to
invalidate the relevant pages in the qemu TLB.
Currently we do that by doing some complicated calculations to work out the
right encoding for the tlbie instruction, then passing that to
ppc_tlb_invalidate_one()... which totally ignores the argument and flushes
the whole tlb.
Avoid that by adding a new flush-by-hpte helper in mmu-hash64.c.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: 1114e712c998d6c6d888e8a22aab94e143ae3fd8
https://github.com/qemu/qemu/commit/1114e712c998d6c6d888e8a22aab94e143ae3fd8
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M hw/ppc/spapr_hcall.c
M target-ppc/mmu-hash64.c
M target-ppc/mmu-hash64.h
Log Message:
-----------
target-ppc: Helper to determine page size information from hpte alone
h_enter() in the spapr code needs to know the page size of the HPTE it's
about to insert. Unlike other paths that do this, it doesn't have access
to the SLB, so at the moment it determines this with some open-coded
tests which assume POWER7 or POWER8 page size encodings.
To make this more flexible add ppc_hash64_hpte_page_shift_noslb() to
determine both the "base" page size per segment, and the individual
effective page size from an HPTE alone.
This means that the spapr code should now be able to handle any page size
listed in the env->sps table.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: a8891fbf216b643586937f01bb7478e4e5a319f8
https://github.com/qemu/qemu/commit/a8891fbf216b643586937f01bb7478e4e5a319f8
Author: David Gibson <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/mmu-hash64.h
M target-ppc/translate_init.c
Log Message:
-----------
target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
Now that the TCG and spapr code has been extended to allow (semi-)
arbitrary page encodings in the CPU's 'sps' table, we can add the many
page sizes supported by real POWER7 and POWER8 hardware that we previously
didn't support in TCG.
Signed-off-by: David Gibson <address@hidden>
Acked-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: fc03cfef8b1f2d855c96fd6942914f5104b57e71
https://github.com/qemu/qemu/commit/fc03cfef8b1f2d855c96fd6942914f5104b57e71
Author: James Clarke <address@hidden>
Date: 2016-01-30 (Sat, 30 Jan 2016)
Changed paths:
M target-ppc/cpu.h
Log Message:
-----------
target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro
Signed-off-by: James Clarke <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d1277156b5d3df6d75d138a7eec6ff80934cdcec
https://github.com/qemu/qemu/commit/d1277156b5d3df6d75d138a7eec6ff80934cdcec
Author: James Clarke <address@hidden>
Date: 2016-02-01 (Mon, 01 Feb 2016)
Changed paths:
M target-ppc/cpu.h
M target-ppc/translate.c
Log Message:
-----------
target-ppc: mcrfs should always update FEX/VX and only clear exception bits
Here is the description of the mcrfs instruction from the PowerPC Architecture
Book, Version 2.02, Book I: PowerPC User Instruction Set Architecture
(http://www.ibm.com/developerworks/systems/library/es-archguide-v2.html), found
on page 120:
The contents of FPSCR field BFA are copied to Condition Register field BF.
All exception bits copied are set to 0 in the FPSCR. If the FX bit is
copied, it is set to 0 in the FPSCR.
Special Registers Altered:
CR field BF
FX OX (if BFA=0)
UX ZX XX VXSNAN (if BFA=1)
VXISI VXIDI VXZDZ VXIMZ (if BFA=2)
VXVC (if BFA=3)
VXSOFT VXSQRT VXCVI (if BFA=5)
However, currently every bit in FPSCR field BFA is set to 0, including ones not
on that list.
This can be seen in the following simple C program:
#include <fenv.h>
#include <stdio.h>
int main(int argc, char **argv) {
int ret;
ret = fegetround();
printf("Current rounding: %d\n", ret);
ret = fesetround(FE_UPWARD);
printf("Setting to FE_UPWARD (%d): %d\n", FE_UPWARD, ret);
ret = fegetround();
printf("Current rounding: %d\n", ret);
ret = fegetround();
printf("Current rounding: %d\n", ret);
return 0;
}
which gave the output (before this commit):
Current rounding: 0
Setting to FE_UPWARD (2): 0
Current rounding: 2
Current rounding: 0
instead of (after this commit):
Current rounding: 0
Setting to FE_UPWARD (2): 0
Current rounding: 2
Current rounding: 2
The relevant disassembly is in fegetround(), which, on my system, is:
__GI___fegetround:
<+0>: mcrfs cr7, cr7
<+4>: mfcr r3
<+8>: clrldi r3, r3, 62
<+12>: blr
What happens is that, the first time fegetround() is called, FPSCR field 7 is
retrieved. However, because of the bug in mcrfs, the entirety of field 7 is set
to 0, which includes the rounding mode.
There are other issues this will fix, such as condition flags not persisting
when they should if read, and if you were to read a specific field with some
exception bits set, but no others were set in the entire register, then the
bits would be cleared correctly, but FEX/VX would not be updated to 0 as they
should be.
Signed-off-by: James Clarke <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 10ae9d76388e3f4a31f6a1475b5e2d1f28404a10
https://github.com/qemu/qemu/commit/10ae9d76388e3f4a31f6a1475b5e2d1f28404a10
Author: Peter Maydell <address@hidden>
Date: 2016-02-02 (Tue, 02 Feb 2016)
Changed paths:
M configure
A gdb-xml/power-vsx.xml
M hw/ide/macio.c
M hw/misc/macio/cuda.c
M hw/misc/macio/mac_dbdma.c
M hw/pci-host/uninorth.c
M hw/ppc/mac.h
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
M target-ppc/cpu-models.c
M target-ppc/cpu-models.h
M target-ppc/cpu.h
M target-ppc/gdbstub.c
M target-ppc/helper.h
M target-ppc/kvm.c
M target-ppc/kvm_ppc.h
M target-ppc/machine.c
M target-ppc/mmu-hash32.c
M target-ppc/mmu-hash32.h
M target-ppc/mmu-hash64.c
M target-ppc/mmu-hash64.h
M target-ppc/mmu_helper.c
M target-ppc/translate.c
M target-ppc/translate_init.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160201' into
staging
ppc patch queue for 2016-02-01
Currently accumulated patches for target-ppc, pseries machine type and
related devices.
* Cleanup of error handling code in spapr
* A number of fixes for Macintosh devices for the benefit of MacOS 9 and X
* Remove some abuses of the RTAS memory access functions in spapr
* Fixes for the gdbstub (and monitor debug) for VMX and VSX extensions.
* Fix pseries machine hotplug memory under TCG
* Clean up and extend handling of multiple page sizes with 64-bit hash MMUs
* Fix to the TCG implementation of mcrfs
# gpg: Signature made Mon 01 Feb 2016 02:28:34 GMT using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.6-20160201: (40 commits)
target-ppc: mcrfs should always update FEX/VX and only clear exception bits
target-ppc: Make every FPSCR_ macro have a corresponding FP_ macro
target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG
target-ppc: Helper to determine page size information from hpte alone
target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs
target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()
target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one
target-ppc: Use actual page size encodings from HPTE
target-ppc: Rework SLB page size lookup
target-ppc: Rework ppc_store_slb
target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to PowerPCCPU
target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub
uninorth.c: add support for UniNorth kMacRISCPCIAddressSelect (0x48) register
cuda.c: return error for unknown commands
pseries: Allow TCG h_enter to work with hotplugged memory
target-ppc: gdbstub: Add VSX support
target-ppc: gdbstub: fix spe registers for little-endian guests
target-ppc: gdbstub: fix altivec registers for little-endian guests
target-ppc: gdbstub: introduce avr_need_swap()
target-ppc: gdbstub: fix float registers for little-endian guests
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/0430891ce162...10ae9d76388e
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