[Qemu-commits] [qemu/qemu] a43e68: virt-acpi-build: add always-on property for timer

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a43e68a08bd0d723cc7e480e422a1008a5bb78a9
      
https://github.com/qemu/qemu/commit/a43e68a08bd0d723cc7e480e422a1008a5bb78a9
  Author: Andrew Jones <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  virt-acpi-build: add always-on property for timer

This patch is the ACPI equivalent of "hw/arm/virt: Add always-on
property to the virt board timer". The timer is always on, and
thus setting this informs Linux that it may switch off the periodic
timer. Switching off the periodic timer substantially reduces the
number of interrupts the host needs to inject.

Testing note: AArch64 guests (the only ones currently booting with
ACPI) do not actually need this patch to determine it can turn the
periodic timer off. I therefore used a hacked guest kernel to ensure
this patch works as the equivalent DT patch does.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6a43e0b6e1f6bcd6b11656967422f4217258200a
      
https://github.com/qemu/qemu/commit/6a43e0b6e1f6bcd6b11656967422f4217258200a
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make various system registers visible to EL3

The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ,
SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from
EL3 even if the CPU has no EL2 (unlike some others which are RES0
from EL3 in that configuration).  Move them from el2_cp_reginfo[] to
v8_cp_reginfo[] so they are always present.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 48d21a576a9cd5fd223bda416abb68b5c2818b52
      
https://github.com/qemu/qemu/commit/48d21a576a9cd5fd223bda416abb68b5c2818b52
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots

When booting Linux on AArch64 enabled cores, setup EL1 and
EL2 to use AArch64.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 98d68ec289750139258d9cd9ab3f6d7dd10bb762
      
https://github.com/qemu/qemu/commit/98d68ec289750139258d9cd9ab3f6d7dd10bb762
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Apply S2 MMU startlevel table size check to AArch64

The S2 starting level table size check applies to both AArch32
and AArch64. Move it to common code.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a0e966c93a0968d29ef51447d08a6b7be6f4d757
      
https://github.com/qemu/qemu/commit/a0e966c93a0968d29ef51447d08a6b7be6f4d757
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Rename check_s2_startlevel to check_s2_mmu_setup

Rename check_s2_startlevel to check_s2_mmu_setup in preparation
for additional checks.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3526423e867765568ad95b8094ae8b4042cac215
      
https://github.com/qemu/qemu/commit/3526423e867765568ad95b8094ae8b4042cac215
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement the S2 MMU inputsize > pamax check

Implement the inputsize > pamax check for Stage 2 translations.
This is CONSTRAINED UNPREDICTABLE and we choose to fault.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6d152ebaf4db6567cefbbd3b2b102c4a50172109
      
https://github.com/qemu/qemu/commit/6d152ebaf4db6567cefbbd3b2b102c4a50172109
  Author: Igor Mammedov <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M include/hw/arm/virt-acpi-build.h

  Log Message:
  -----------
  arm: virt-acpi: each MADT.GICC entry as enabled unconditionally

in current impl. condition

build_madt() {
  ...
  if (test_bit(i, cpuinfo->found_cpus))

is always true since loop handles only present CPUs
in range [0..smp_cpus).
But to fill usless cpuinfo->found_cpus we do unnecessary
scan over QOM tree to find the same CPUs.
So mark GICC as present always and drop not needed
code that fills cpuinfo->found_cpus.

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0602f420e40769b1d2829dd326bb632cc71aa407
      
https://github.com/qemu/qemu/commit/0602f420e40769b1d2829dd326bb632cc71aa407
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M disas/libvixl/vixl/a64/disasm-a64.cc

  Log Message:
  -----------
  libvixl: Avoid std::abs() of 64-bit type

The std::abs() function did not get a version that works on
'long long' until C++11. Avoid it, so that we can compile on
32-bit platforms (where int64_t is 'long long') with older
compilers (which don't support C++11).

Reported-by: Franz-Josef Haider <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 3c2f7bb32b4c597925c5c7411307d51f1a56045d
      
https://github.com/qemu/qemu/commit/3c2f7bb32b4c597925c5c7411307d51f1a56045d
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Don't report presence of EL2 if it doesn't exist

We already modify the processor feature bits to not report EL3
support to the guest if EL3 isn't enabled for the CPU we're emulating.
Add similar support for not reporting EL2 unless it is enabled.
This is necessary because real world guest code running at EL3
(trusted firmware or bootloaders) will query the ID registers to
determine whether it should start a guest Linux kernel in EL2 or EL3.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden


  Commit: 99494e696e03adf957bbbcf7345ce31ad7e45497
      
https://github.com/qemu/qemu/commit/99494e696e03adf957bbbcf7345ce31ad7e45497
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/misc/Makefile.objs
    A hw/misc/bcm2835_mbox.c
    A include/hw/misc/bcm2835_mbox.h
    A include/hw/misc/bcm2835_mbox_defs.h

  Log Message:
  -----------
  bcm2835_mbox: add BCM2835 mailboxes

This adds the system mailboxes which are used to communicate with a
number of GPU peripherals on Pi/Pi2.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 04f1ab15b9f60bbd0f71adbe7659aef12ca1a448
      
https://github.com/qemu/qemu/commit/04f1ab15b9f60bbd0f71adbe7659aef12ca1a448
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/bcm2835_property.c
    A include/hw/misc/bcm2835_property.h

  Log Message:
  -----------
  bcm2835_property: add bcm2835 property channel

This sits behind the mailbox interface, and implements
request/response queries for system properties. The
framebuffer-related properties will be added in a later patch.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e3ece3e34d912bcca13e552def3dd9bec2ad5d32
      
https://github.com/qemu/qemu/commit/e3ece3e34d912bcca13e552def3dd9bec2ad5d32
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/bcm2835_ic.c
    A include/hw/intc/bcm2835_ic.h

  Log Message:
  -----------
  bcm2835_ic: add bcm2835 interrupt controller

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c62aeb82a143f4fcb1e6e419175cd120407deac
      
https://github.com/qemu/qemu/commit/7c62aeb82a143f4fcb1e6e419175cd120407deac
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/bcm2835_peripherals.c
    A include/hw/arm/bcm2835_peripherals.h
    A include/hw/arm/raspi_platform.h

  Log Message:
  -----------
  bcm2835_peripherals: add rollup device for bcm2835 peripherals

This device maintains all the non-CPU peripherals on bcm2835 (Pi1)
which are also present on bcm2836 (Pi2). It also implements the
private address spaces used for DMA and mailboxes.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cc28296d82ce179e81ee6d0b9cfb7f6a79ffc1c6
      
https://github.com/qemu/qemu/commit/cc28296d82ce179e81ee6d0b9cfb7f6a79ffc1c6
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/intc/Makefile.objs
    A hw/intc/bcm2836_control.c
    A include/hw/intc/bcm2836_control.h

  Log Message:
  -----------
  bcm2836_control: add bcm2836 ARM control logic

This module is specific to the bcm2836 (Pi2). It implements the top
level interrupt controller, and mailboxes used for inter-processor
synchronisation.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bad5623690b17461dd87bbf3b49fe3396379bd69
      
https://github.com/qemu/qemu/commit/bad5623690b17461dd87bbf3b49fe3396379bd69
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/bcm2836.c
    A include/hw/arm/bcm2836.h

  Log Message:
  -----------
  bcm2836: add bcm2836 SoC device

This is the SoC for Raspberry Pi 2.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 716536a9b6688710909aef69ac842bcc66039b92
      
https://github.com/qemu/qemu/commit/716536a9b6688710909aef69ac842bcc66039b92
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/highbank.c
    M include/hw/arm/arm.h

  Log Message:
  -----------
  arm/boot: move highbank secure board setup code to common routine

The new version is slightly different, to support Rasbperry Pi (in
particular, Pi1's arm11 core which doesn't support v7 instructions
such as MOVW).

Tested-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1df7d1f9303aef9a2b1f703e887553416b7c0586
      
https://github.com/qemu/qemu/commit/1df7d1f9303aef9a2b1f703e887553416b7c0586
  Author: Andrew Baumann <address@hidden>
  Date:   2016-02-03 (Wed, 03 Feb 2016)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/raspi.c

  Log Message:
  -----------
  raspi: add raspberry pi 2 machine

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Andrew Baumann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 071aacc9c9e15859500bbacf153e03b45008ee50
      
https://github.com/qemu/qemu/commit/071aacc9c9e15859500bbacf153e03b45008ee50
  Author: Peter Maydell <address@hidden>
  Date:   2016-02-04 (Thu, 04 Feb 2016)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M disas/libvixl/vixl/a64/disasm-a64.cc
    M hw/arm/Makefile.objs
    A hw/arm/bcm2835_peripherals.c
    A hw/arm/bcm2836.c
    M hw/arm/boot.c
    M hw/arm/highbank.c
    A hw/arm/raspi.c
    M hw/arm/virt-acpi-build.c
    M hw/intc/Makefile.objs
    A hw/intc/bcm2835_ic.c
    A hw/intc/bcm2836_control.c
    M hw/misc/Makefile.objs
    A hw/misc/bcm2835_mbox.c
    A hw/misc/bcm2835_property.c
    M include/hw/arm/arm.h
    A include/hw/arm/bcm2835_peripherals.h
    A include/hw/arm/bcm2836.h
    A include/hw/arm/raspi_platform.h
    M include/hw/arm/virt-acpi-build.h
    A include/hw/intc/bcm2835_ic.h
    A include/hw/intc/bcm2836_control.h
    A include/hw/misc/bcm2835_mbox.h
    A include/hw/misc/bcm2835_mbox_defs.h
    A include/hw/misc/bcm2835_property.h
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160203' 
into staging

target-arm queue:
 * virt-acpi-build: add always-on property for timer
 * various fixes for EL2 and EL3 behaviour
 * arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
 * target-arm: Don't report presence of EL2 if it doesn't exist
 * raspi: add raspberry pi 2 machine

# gpg: Signature made Wed 03 Feb 2016 18:58:02 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20160203:
  raspi: add raspberry pi 2 machine
  arm/boot: move highbank secure board setup code to common routine
  bcm2836: add bcm2836 SoC device
  bcm2836_control: add bcm2836 ARM control logic
  bcm2835_peripherals: add rollup device for bcm2835 peripherals
  bcm2835_ic: add bcm2835 interrupt controller
  bcm2835_property: add bcm2835 property channel
  bcm2835_mbox: add BCM2835 mailboxes
  target-arm: Don't report presence of EL2 if it doesn't exist
  libvixl: Avoid std::abs() of 64-bit type
  arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
  target-arm: Implement the S2 MMU inputsize > pamax check
  target-arm: Rename check_s2_startlevel to check_s2_mmu_setup
  target-arm: Apply S2 MMU startlevel table size check to AArch64
  hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots
  target-arm: Make various system registers visible to EL3
  virt-acpi-build: add always-on property for timer

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/382d34ff9fcc...071aacc9c9e1