[Qemu-commits] [qemu/qemu] 8e7e8a: hw/mips: implement generic MIPS Coher

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[Qemu-commits] [qemu/qemu] 8e7e8a: hw/mips: implement generic MIPS Coher

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 8e7e8a: hw/mips: implement generic MIPS Coherent Processin...
Date:	Wed, 30 Mar 2016 09:30:04 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3
      
https://github.com/qemu/qemu/commit/8e7e8a5b7b95c143f396f6aadd310e9ff2f7efd3
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M default-configs/mips-softmmu-common.mak
    M hw/mips/Makefile.objs
    A hw/mips/cps.c
    A include/hw/mips/cps.h

  Log Message:
  -----------
  hw/mips: implement generic MIPS Coherent Processing System container

Implement generic MIPS Coherent Processing System (CPS) which in this
commit just creates VPs, but it will serve as a container also for
other components like Global Configuration Registers and Cluster Power
Controller.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: c870e3f52cac0c8a4a1377398327c4ff20d49d41
      
https://github.com/qemu/qemu/commit/c870e3f52cac0c8a4a1377398327c4ff20d49d41
  Author: Yongbok Kim <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add CMGCRBase register

Physical base address for the memory-mapped Coherency Manager Global
Configuration Register space.
The MIPS default location for the GCR_BASE address is 0x1FBF_8.
This register only exists if Config3 CMGCR is set to one.

Signed-off-by: Yongbok Kim <address@hidden>
address@hidden: move CMGCR enabling to a separate patch]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3994215db442e11880cfd0c337137d6dcf56e11d
      
https://github.com/qemu/qemu/commit/3994215db442e11880cfd0c337137d6dcf56e11d
  Author: Yongbok Kim <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/mips_cmgcr.c
    A include/hw/misc/mips_cmgcr.h

  Log Message:
  -----------
  hw/mips: add initial Global Config Register support

Add initial GCR support to indicate number of VPs present in the system,
L2 bypass mode and revision number.

Signed-off-by: Yongbok Kim <address@hidden>
address@hidden:
 * removed GIC part,
 * changed commit message,
 * replaced %lx format spec. with PRIx64,
 * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h},
 * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS]
Signed-off-by: Leon Alrae <address@hidden>


  Commit: a9bd9b5a8682c8129b46ae0e673efdad35f493c2
      
https://github.com/qemu/qemu/commit/a9bd9b5a8682c8129b46ae0e673efdad35f493c2
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/cps.c
    M include/hw/mips/cps.h

  Log Message:
  -----------
  hw/mips/cps: create GCR block inside CPS

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1f93a6e4f3f4da3c2ce4be1d300dcfe3e6dd0e77
      
https://github.com/qemu/qemu/commit/1f93a6e4f3f4da3c2ce4be1d300dcfe3e6dd0e77
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/mips_cpc.c
    A include/hw/misc/mips_cpc.h

  Log Message:
  -----------
  hw/mips: add initial Cluster Power Controller support

Cluster Power Controller (CPC) is responsible for power management in
multiprocessing system. It provides registers to control the power and the
clock frequency of the individual elements in the system.

This patch implements only three registers that are used to control the
power state of each VP on a single core:
* VP Run is a write-only register used to set each VP to the run state
* VP Stop is a write-only register used to set each VP to the suspend state
* VP Running is a read-only register indicating the run state of each VP

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 2edd5261fffcc8494936d353ffffe996d191da3b
      
https://github.com/qemu/qemu/commit/2edd5261fffcc8494936d353ffffe996d191da3b
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/cps.c
    M hw/misc/mips_cmgcr.c
    M include/hw/mips/cps.h
    M include/hw/misc/mips_cmgcr.h

  Log Message:
  -----------
  hw/mips/cps: create CPC block inside CPS

Create Cluster Power Controller and add a link to the CPC MemoryRegion
in GCR. Guest can enable / map CPC to any physical address by writing to
the memory-mapped GCR_CPC_BASE register.

Set vp-start-reset property to 1 to allow only first VP to run from reset.
Others are brought up by the guest via CPC memory-mapped registers.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: cc518af0b2df156b68551cb1585a9db17c2b0084
      
https://github.com/qemu/qemu/commit/cc518af0b2df156b68551cb1585a9db17c2b0084
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  hw/mips_malta: remove CPUMIPSState from the write_bootloader()

Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: dc520a7dee0a9307e844eb6c5d4b21482bf52fcd
      
https://github.com/qemu/qemu/commit/dc520a7dee0a9307e844eb6c5d4b21482bf52fcd
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  hw/mips_malta: remove redundant irq and clock init

Global smp_cpus is never zero (even if user provides -smp 0), thus clocks
and irqs are always initialized for each created CPU in the loop at the
beginning of mips_malta_init.

These two lines cause a leak of already allocated timer and irqs for the
first CPU - remove them.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 67a54961848cd78a82ef23b26a0daf011c1f5d4d
      
https://github.com/qemu/qemu/commit/67a54961848cd78a82ef23b26a0daf011c1f5d4d
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/mips_malta.c

  Log Message:
  -----------
  hw/mips_malta: move CPU creation to a separate function

Signed-off-by: Leon Alrae <address@hidden>


  Commit: bff384a4fbd5d0e86939092e74e766ef0f5f592c
      
https://github.com/qemu/qemu/commit/bff384a4fbd5d0e86939092e74e766ef0f5f592c
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/mips_malta.c
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  hw/mips_malta: add CPS to Malta board

If the user specifies smp > 1 and the CPU with CM GCR support, then
create Coherent Processing System (which takes care of instantiating CPUs)
rather than CPUs directly and connect i8259 and cbus to the pins exposed by
CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use
the same pin numbers as before.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: a9a95061715ca09abff56a3f239f704c410912c2
      
https://github.com/qemu/qemu/commit/a9a95061715ca09abff56a3f239f704c410912c2
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: enable CM GCR in MIPS64R6-generic CPU

Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 34fa7e83e117cb061a9ff5e53a9863b9bfb5f2f6
      
https://github.com/qemu/qemu/commit/34fa7e83e117cb061a9ff5e53a9863b9bfb5f2f6
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M default-configs/mips-softmmu-common.mak
    M hw/misc/Makefile.objs
    A hw/misc/mips_itu.c
    A include/hw/misc/mips_itu.h
    M target-mips/cpu.h

  Log Message:
  -----------
  hw/mips: implement ITC Configuration Tags and Storage Cells

Implement ITC as a single object consisting of two memory regions:

1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which
are accessible by the CPU via CACHE instruction. Also adding
MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will
dispatch reads/writes directly.

2) storage_io: memory-mapped ITC Storage whose address space is configurable
(i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers.

ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the
ITC cell tag indicates the type of the cell. If the ITC Storage contains
both types of cells then FIFOs are located before Semaphores.

Since issuing thread can get blocked on the access to a cell (in E/F
Synchronized and P/V Synchronized Views) each cell has a bitmap to track
which threads are currently blocked.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 5924c869c05c89c8699c5b2f6347880ba88e1989
      
https://github.com/qemu/qemu/commit/5924c869c05c89c8699c5b2f6347880ba88e1989
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/mips_itu.c

  Log Message:
  -----------
  hw/mips: implement ITC Storage - Control View

Control view is used to access the ITC Storage Cell Tags. It never causes
the issuing thread to block.

Guest can empty the FIFO cell by setting Empty bit to 1.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4051089d61166e7b548ac4b62288a52312331f31
      
https://github.com/qemu/qemu/commit/4051089d61166e7b548ac4b62288a52312331f31
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/mips_itu.c

  Log Message:
  -----------
  hw/mips: implement ITC Storage - Empty/Full Sync and Try Views

Empty/Full Synchronized and Try views can be used to access FIFO cells.
Store to the FIFO cell pushes the value into the queue, load pops the oldest
element from the queue. Cell's Full and Empty bits are automatically updated
to reflect new state of the cell.

Empty/Full Synchronized View causes the issuing thread to block when FIFO is
empty while thread is performing a read, or FIFO is full while thread is
performing a write.

Empty/Full Try View never blocks the thread. If cell is full then write is
ignored, if cell is empty then load returns 0.

Trap bit (i.e. Gating Storage exceptions) not implemented.
Store Conditional support for E/F Try View (i.e. indicate failure if FIFO
is full) not implemented.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 40dc9dc3394d2796341aeda6cd14bac46ce24735
      
https://github.com/qemu/qemu/commit/40dc9dc3394d2796341aeda6cd14bac46ce24735
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/mips_itu.c

  Log Message:
  -----------
  hw/mips: implement ITC Storage - P/V Sync and Try Views

P/V Synchronized and Try Views can be used to access Semaphore cells.
Load returns current value and post-decrements the value in the cell
(until it reaches zero). Stores increment the value (until it saturates
at 0xFFFF).

P/V Synchronized View causes the issuing thread to block on read if value
is 0. P/V Try View does not block the thread, it returns 0 in this case.

Cell's Empty and Full bits are not modified.

Trap bit (i.e. Gating Storage exceptions) not implemented.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 25a611e3e4a560c034c942527c643dfc990c7491
      
https://github.com/qemu/qemu/commit/25a611e3e4a560c034c942527c643dfc990c7491
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/misc/mips_itu.c

  Log Message:
  -----------
  hw/mips: implement ITC Storage - Bypass View

Bypass View does not cause issuing thread to block and does not affect
any of the cells state bit.

Read from a FIFO cell returns the value of the oldest entry.
Store to a FIFO cell changes the value of the newest entry.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 40d48212f934d4deab40ffe84a0f9c4c553d4742
      
https://github.com/qemu/qemu/commit/40d48212f934d4deab40ffe84a0f9c4c553d4742
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: check CP0 enabled for CACHE instruction also in R6

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 0d74a222c27e26fc40f4f6120c61c3f9ceaa3776
      
https://github.com/qemu/qemu/commit/0d74a222c27e26fc40f4f6120c61c3f9ceaa3776
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: make ITC Configuration Tags accessible to the CPU

Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv
processors these bits are used to enable CACHE instruction access to
different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will
access ITC tag values.

Generally we do not model caches and we have been treating the CACHE
instruction as NOP. But since CACHE can operate on ITC Tags new
MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when
CACHE is in the ITC Access mode.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: 408294352adb6b38952ada680951f6ed2fd628d6
      
https://github.com/qemu/qemu/commit/408294352adb6b38952ada680951f6ed2fd628d6
  Author: Leon Alrae <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M hw/mips/cps.c
    M include/hw/mips/cps.h

  Log Message:
  -----------
  hw/mips/cps: enable ITU for multithreading processors

Make ITU available in the system if CPU supports multithreading
and is part of CPS.

Signed-off-by: Leon Alrae <address@hidden>


  Commit: c98d3d79ee387ea6e8fb091299f8562b20022f10
      
https://github.com/qemu/qemu/commit/c98d3d79ee387ea6e8fb091299f8562b20022f10
  Author: Yongbok Kim <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: use CP0_CHECK for gen_m{f|t}hc0

Reuse CP0_CHECK macro for gen_m{f|t}hc0.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: f6d4dd810983fdf3d1c9fb81838167efef63d1c8
      
https://github.com/qemu/qemu/commit/f6d4dd810983fdf3d1c9fb81838167efef63d1c8
  Author: Yongbok Kim <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/machine.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add MAAR, MAARI register

The MAAR register is a read/write register included in Release 5
of the architecture that defines the accessibility attributes of
physical address regions. In particular, MAAR defines whether an
instruction fetch or data load can speculatively access a memory
region within the physical address bounds specified by MAAR.

As QEMU doesn't do speculative access, hence this patch only
provides ability to access the registers.

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 489ef4c810033e63af570c8a430af8b9858bfa5f
      
https://github.com/qemu/qemu/commit/489ef4c810033e63af570c8a430af8b9858bfa5f
  Author: Peter Maydell <address@hidden>
  Date:   2016-03-30 (Wed, 30 Mar 2016)

  Changed paths:
    M default-configs/mips-softmmu-common.mak
    M hw/mips/Makefile.objs
    A hw/mips/cps.c
    M hw/mips/mips_malta.c
    M hw/misc/Makefile.objs
    A hw/misc/mips_cmgcr.c
    A hw/misc/mips_cpc.c
    A hw/misc/mips_itu.c
    A include/hw/mips/cps.h
    A include/hw/misc/mips_cmgcr.h
    A include/hw/misc/mips_cpc.h
    A include/hw/misc/mips_itu.h
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/machine.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160329-2' into 
staging

MIPS patches 2016-03-29

Changes:
* add initial MIPS CPS support
* implement ITU block
* implement MAAR

# gpg: Signature made Wed 30 Mar 2016 09:27:01 BST using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <address@hidden>"

* remotes/lalrae/tags/mips-20160329-2: (21 commits)
  target-mips: add MAAR, MAARI register
  target-mips: use CP0_CHECK for gen_m{f|t}hc0
  hw/mips/cps: enable ITU for multithreading processors
  target-mips: make ITC Configuration Tags accessible to the CPU
  target-mips: check CP0 enabled for CACHE instruction also in R6
  hw/mips: implement ITC Storage - Bypass View
  hw/mips: implement ITC Storage - P/V Sync and Try Views
  hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
  hw/mips: implement ITC Storage - Control View
  hw/mips: implement ITC Configuration Tags and Storage Cells
  target-mips: enable CM GCR in MIPS64R6-generic CPU
  hw/mips_malta: add CPS to Malta board
  hw/mips_malta: move CPU creation to a separate function
  hw/mips_malta: remove redundant irq and clock init
  hw/mips_malta: remove CPUMIPSState from the write_bootloader()
  hw/mips/cps: create CPC block inside CPS
  hw/mips: add initial Cluster Power Controller support
  hw/mips/cps: create GCR block inside CPS
  hw/mips: add initial Global Config Register support
  target-mips: add CMGCRBase register
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/69bc7f5029db...489ef4c81003
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