[Qemu-commits] [qemu/qemu] 5fd111: ppc: Remove MMU_MODEn_SUFFIX definitions

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 5fd1111b20a8f1955e3156a80e0576007548e871
      
https://github.com/qemu/qemu/commit/5fd1111b20a8f1955e3156a80e0576007548e871
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  ppc: Remove MMU_MODEn_SUFFIX definitions

We don't use the resulting accessors and this gets in the way of
the split I/D TLB work.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9fb044911444fdd09f5f072ad0ca269d7f8b841d
      
https://github.com/qemu/qemu/commit/9fb044911444fdd09f5f072ad0ca269d7f8b841d
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper_regs.h
    M target-ppc/machine.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Use split I/D mmu modes to avoid flushes on interrupts

We rework the way the MMU indices are calculated, providing separate
indices for I and D side based on MSR:IR and MSR:DR respectively,
and thus no longer need to flush the TLB on context changes. This also
adds correct support for HV as a separate address space.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: cd0c6f473532bfaf20a095bc90a18e45162981b5
      
https://github.com/qemu/qemu/commit/cd0c6f473532bfaf20a095bc90a18e45162981b5
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Do some batching of TCG tlb flushes

On ppc64 especially, we flush the tlb on any slbie or tlbie instruction.

However, those instructions often come in bursts of 3 or more (context
switch will favor a series of slbie's for example to an slbia if the
SLB has less than a certain number of entries in it, and tlbie's can
happen in a series, with PAPR, H_BULK_REMOVE can remove up to 4 entries
at a time.

Doing a tlb_flush() each time is a waste of time. We end up doing a memset
of the whole TLB, reloading it for the next instruction, memset'ing again,
etc...

Those instructions don't have to take effect immediately. For slbie, they
can wait for the next context synchronizing event. For tlbie, the next
tlbsync.

This implements batching by keeping a flag that indicates that we have a
TLB in need of flushing. We check it on interrupts, rfi's, isync's and
tlbsync and flush the TLB if needed.

This reduces the number of tlb_flush() on a boot to a ubuntu installer
first dialog screen from roughly 360K down to 36K.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: added a 'CPUPPCState *' variable in h_remove() and
      h_bulk_remove() ]
Signed-off-by: Cédric Le Goater <address@hidden>
[dwg: removed spurious whitespace change, use 0/1 not true/false
      consistently, since tlb_need_flush has int type]
Signed-off-by: David Gibson <address@hidden>


  Commit: 74693da98894e685c53a660ab238e5253b211216
      
https://github.com/qemu/qemu/commit/74693da98894e685c53a660ab238e5253b211216
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: tlbie, tlbia and tlbisync are HV only

Not that anything remotely recent supports tlbia but ...

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f9ef0527ff8fe257756fb3db46b557f9980cb0eb
      
https://github.com/qemu/qemu/commit/f9ef0527ff8fe257756fb3db46b557f9980cb0eb
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Change 'invalid' bit mask of tlbiel and tlbie

Otherwise it will trip on the forms used in recent architecture.

Ideally, we should have different handlers for different architecture
levels but our current implementation of TLB flushing is dumb enough
that this will do for now.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c409bc5daf88a2753968fdf473b7e4b528eb841c
      
https://github.com/qemu/qemu/commit/c409bc5daf88a2753968fdf473b7e4b528eb841c
  Author: Michael Neuling <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Fix sign extension issue in mtmsr(d) emulation

Signed-off-by: Michael Neuling <address@hidden>
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b68e60e6f0d2865e961a800fb8db96a7fc6494c4
      
https://github.com/qemu/qemu/commit/b68e60e6f0d2865e961a800fb8db96a7fc6494c4
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  ppc: Get out of emulation on SMT "OR" ops

Otherwise tight loops at smt_low for example, which OPAL does,
eat so much CPU that we can't boot a kernel anymore. With that,
I can boot 8 CPUs just fine with powernv.

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4e0806110c8b896ceff3490f15a616e8b3165efe
      
https://github.com/qemu/qemu/commit/4e0806110c8b896ceff3490f15a616e8b3165efe
  Author: Benjamin Herrenschmidt <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  ppc: Add PPC_64H instruction flag to POWER7 and POWER8

This will enable decoding of hrfid

Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1c59eb39cf75e660b1ac4ea95ef789c84021a1c4
      
https://github.com/qemu/qemu/commit/1c59eb39cf75e660b1ac4ea95ef789c84021a1c4
  Author: Bharata B Rao <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec: Remove cpu from cpus list during cpu_exec_exit()

CPUState *cpu gets added to the cpus list during cpu_exec_init(). It
should be removed from cpu_exec_exit().

cpu_exec_exit() is called from generic CPU::instance_finalize and some
archs like PowerPC call it from CPU unrealizefn. So ensure that we
dequeue the cpu only once.

Now -1 value for cpu->cpu_index indicates that we have already dequeued
the cpu for CONFIG_USER_ONLY case also.

Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9dfeca7c6b1d3a8f36531bbbac0322a9907bcd86
      
https://github.com/qemu/qemu/commit/9dfeca7c6b1d3a8f36531bbbac0322a9907bcd86
  Author: Bharata B Rao <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec: Do vmstate unregistration from cpu_exec_exit()

cpu_exec_init() does vmstate_register for the CPU device. This needs to be
undone from cpu_exec_exit(). This change is needed to support CPU hot
removal.

Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
[dwg: added missing include to fix compile on some archs]
Signed-off-by: David Gibson <address@hidden>


  Commit: 4c055ab54fae39b6329c57bcb5334d59b920463e
      
https://github.com/qemu/qemu/commit/4c055ab54fae39b6329c57bcb5334d59b920463e
  Author: Gu Zheng <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M cpus.c
    M include/qom/cpu.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M kvm-stub.c

  Log Message:
  -----------
  cpu: Reclaim vCPU objects

In order to deal well with the kvm vcpus (which can not be removed without any
protection), we do not close KVM vcpu fd, just record and mark it as stopped
into a list, so that we can reuse it for the appending cpu hot-add request if
possible. It is also the approach that kvm guys suggested:
https://www.mail-archive.com/address@hidden/msg102839.html

Signed-off-by: Chen Fan <address@hidden>
Signed-off-by: Gu Zheng <address@hidden>
Signed-off-by: Zhu Guihua <address@hidden>
Signed-off-by: Bharata B Rao <address@hidden>
         [- Explicit CPU_REMOVE() from qemu_kvm/tcg_destroy_vcpu()
            isn't needed as it is done from cpu_exec_exit()
          - Use iothread mutex instead of global mutex during
            destroy
          - Don't cleanup vCPU object from vCPU thread context
            but leave it to the callers (device_add/device_del)]
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2c579042e3be50bb40a233a6986348b4f40ed026
      
https://github.com/qemu/qemu/commit/2c579042e3be50bb40a233a6986348b4f40ed026
  Author: Bharata B Rao <address@hidden>
  Date:   2016-05-30 (Mon, 30 May 2016)

  Changed paths:
    M cpus.c
    M include/qom/cpu.h

  Log Message:
  -----------
  cpu: Add a sync version of cpu_remove()

This sync API will be used by the CPU hotplug code to wait for the CPU to
completely get removed before flagging the failure to the device_add
command.

Sync version of this call is needed to correctly recover from CPU
realization failures when ->plug() handler fails.

Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 500acc9c410bcea17148a1072e323c08d12e6a6b
      
https://github.com/qemu/qemu/commit/500acc9c410bcea17148a1072e323c08d12e6a6b
  Author: Peter Maydell <address@hidden>
  Date:   2016-05-31 (Tue, 31 May 2016)

  Changed paths:
    M cpus.c
    M exec.c
    M hw/ppc/spapr_hcall.c
    M include/qom/cpu.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M kvm-stub.c
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper.h
    M target-ppc/helper_regs.h
    M target-ppc/machine.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.7-20160531' into 
staging

ppc patch queue for 2016-05-31

Here's another ppc patch queue.  This batch is all preliminaries
towards two significant features:

1) Full hypervisor-mode support for POWER8
    Patches 1-8 start fixing various bugs with TCG's handling of
    hypervisor mode

2) CPU hotplug support
    Patches 9-12 make some preliminary fixes towards implementing CPU
    hotplug on ppc64 (and other non-x86 platforms).  These patches are
    actually to generic code, not ppc, but are included here with
    Paolo's ACK.

# gpg: Signature made Tue 31 May 2016 01:39:44 BST using RSA key ID 20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.7-20160531:
  cpu: Add a sync version of cpu_remove()
  cpu: Reclaim vCPU objects
  exec: Do vmstate unregistration from cpu_exec_exit()
  exec: Remove cpu from cpus list during cpu_exec_exit()
  ppc: Add PPC_64H instruction flag to POWER7 and POWER8
  ppc: Get out of emulation on SMT "OR" ops
  ppc: Fix sign extension issue in mtmsr(d) emulation
  ppc: Change 'invalid' bit mask of tlbiel and tlbie
  ppc: tlbie, tlbia and tlbisync are HV only
  ppc: Do some batching of TCG tlb flushes
  ppc: Use split I/D mmu modes to avoid flushes on interrupts
  ppc: Remove MMU_MODEn_SUFFIX definitions

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/07e070aac4ee...500acc9c410b