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[Qemu-commits] [qemu/qemu] 92b30c: hw/intc/arm_gicv3: Add missing break
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[Qemu-commits] [qemu/qemu] 92b30c: hw/intc/arm_gicv3: Add missing break |
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Date: |
Mon, 27 Jun 2016 09:00:04 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 92b30c2f7d783e423f3d0093a14c88f4532c0de1
https://github.com/qemu/qemu/commit/92b30c2f7d783e423f3d0093a14c88f4532c0de1
Author: Shannon Zhao <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3: Add missing break
These are spotted by coverity 1356936 and 1356937.
Signed-off-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f6cf41932edf260c2574346a08358ad2d20c357e
https://github.com/qemu/qemu/commit/f6cf41932edf260c2574346a08358ad2d20c357e
Author: Alistair Francis <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
cadence_uart: Protect against transmit errors
If qemu_chr_fe_write() returns an error (represented by a negative
number) we should skip incrementing the count and initiating a
memmove().
Signed-off-by: Alistair Francis <address@hidden>
Reported-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f265ae8c79ce8c194de481e9def1daa3a80dbb96
https://github.com/qemu/qemu/commit/f265ae8c79ce8c194de481e9def1daa3a80dbb96
Author: Alistair Francis <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
cadence_gem: Avoid infinite loops with a misconfigured buffer
A guest can write zero to the DMACFG resulting in an infinite loop when
it reaches the while(bytes_to_copy) loop.
To avoid this issue enforce a minimum size for the RX buffer. Hardware
does not have this enforcement and relies on the guest to set a non-zero
value.
Signed-off-by: Alistair Francis <address@hidden>
Reported-by: Li Qiang <address@hidden>
Reported-by: P J P <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cbdab58d469cc52de30f3d0998a15d32d2fac3a0
https://github.com/qemu/qemu/commit/cbdab58d469cc52de30f3d0998a15d32d2fac3a0
Author: Alistair Francis <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
cadence_gem: Set the last bit when wrap is set
The Cadence GEM data sheet says:
"Wrap - marks last descriptor in transmit buffer descriptor list. This
can be set for any buffer within the frame."
which seems to imply that when the wrap bit is set so is the last bit.
Previously if the wrap bit is set, but the last is not then QEMU will
enter an infinite loop.
Signed-off-by: Alistair Francis <address@hidden>
Reported-by: Li Qiang <address@hidden>
Reported-by: P J P <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1f5c1cfbaec0792cd2e5daae082e017b3543c2c9
https://github.com/qemu/qemu/commit/1f5c1cfbaec0792cd2e5daae082e017b3543c2c9
Author: Thomas Huth <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M tests/Makefile.include
Log Message:
-----------
arm: Re-enable tmp105 test
The tmp105 test is currently not executed since the following
line in the Makefile overwrites the check-qtest-arm-y variable
instead of extending it.
Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1c8a2388aa20029dc75f95c072fb98880e447ffe
https://github.com/qemu/qemu/commit/1c8a2388aa20029dc75f95c072fb98880e447ffe
Author: Andrew Jeffery <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/misc/Makefile.objs
A hw/misc/aspeed_scu.c
M hw/misc/trace-events
A include/hw/misc/aspeed_scu.h
Log Message:
-----------
hw/misc: Add a model for the ASPEED System Control Unit
The SCU is a collection of chip-level control registers that manage the
various functions supported by ASPEED SoCs. Typically the bits control
interactions with clocks, external hardware or reset behaviour, and we
can largly take a hands-off approach to reads and writes.
Firmware makes heavy use of the state to determine how to boot, but the
reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev
property is exposed so that the integrating SoC model can configure the
silicon revision, which in-turn selects the appropriate reset values.
Further qdev properties are exposed so the board model can configure the
board-dependent hardware strapping.
Almost all provided AST2400 reset values are specified by the datasheet.
The notable exception is SOC_SCRATCH1, where we mark the DRAM as
successfully initialised to avoid unnecessary dark corners in the SoC's
u-boot support.
Signed-off-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: drop unnecessary inttypes.h include]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 334973bbae19788559f940966c8e3a208edbb1ee
https://github.com/qemu/qemu/commit/334973bbae19788559f940966c8e3a208edbb1ee
Author: Andrew Jeffery <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/arm/ast2400.c
M include/hw/arm/ast2400.h
Log Message:
-----------
ast2400: Integrate the SCU model and set silicon revision
By specifying the silicon revision we select the appropriate reset
values for the SoC.
Additionally, expose hardware strapping properties aliasing those
provided by the SCU for board-specific configuration.
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 87e79af074ba96a3307447939ae196324b34eb3d
https://github.com/qemu/qemu/commit/87e79af074ba96a3307447939ae196324b34eb3d
Author: Andrew Jeffery <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/arm/palmetto-bmc.c
Log Message:
-----------
palmetto-bmc: Configure the SCU's hardware strapping register
The magic constant configures the following options:
* 28:27: Configure DRAM size as 256MB
* 26:24: DDR3 SDRAM with CL = 6, CWL = 5
* 23: Configure 24/48MHz CLKIN
* 22: Disable GPIOE pass-through mode
* 21: Disable GPIOD pass-through mode
* 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses
* 19: Disable ACPI
* 18: Configure 48MHz CLKIN
* 17: Disable BMC 2nd boot watchdog timer
* 16: Decode SuperIO address 0x2E
* 15: VGA Class Code
* 14: Enable LPC dedicated reset pin
* 13:12: Enable SPI Master and SPI Slave to AHB Bridge
* 11:10: Select CPU:AHB ratio = 2:1
* 9:8: Select 384MHz H-PLL
* 7: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c7cd0a6c2475edaf4659839772cf6af24338eb6f
https://github.com/qemu/qemu/commit/c7cd0a6c2475edaf4659839772cf6af24338eb6f
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Replace JEDEC ID masking with function.
Instead of always reading and comparing jededc ID,
replace it by function.
Signed-off-by: Marcin Krzeminski <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: e3ba6cd67fbb9147f9f375f4925a3e882f8060e2
https://github.com/qemu/qemu/commit/e3ba6cd67fbb9147f9f375f4925a3e882f8060e2
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Make a table for JEDEC ID.
Since it is now longer than 4. This work based on Pawel Lenkow
changes and the kernel SPI framework.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e02b3bf263f81abb99164230e98043c60333d6e1
https://github.com/qemu/qemu/commit/e02b3bf263f81abb99164230e98043c60333d6e1
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Allow more than four banks.
Allow to have more than four 16MiB regions for bigger flash devices.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9964674e5016741f453f322e2b0c422c32cb2220
https://github.com/qemu/qemu/commit/9964674e5016741f453f322e2b0c422c32cb2220
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Introduce COLLECTING_VAR_LEN_DATA state.
Some flash allows to stop read at any time.
Allow framework to support this.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 30467afe7bb1540bd165f461ec43024ac854ae39
https://github.com/qemu/qemu/commit/30467afe7bb1540bd165f461ec43024ac854ae39
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Add additional flash commands:
Page program 4byte/quad and erase 32K sectors 4 bytes.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7a69c1000251799bf4f1d328d72e5cec5217f682
https://github.com/qemu/qemu/commit/7a69c1000251799bf4f1d328d72e5cec5217f682
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Introduce quad and equad modes.
Quad and Equad modes for Spansion and Macronix flash devices.
This commit also includes modification and new command to manipulate
quad mode (status registers and dedicated commands).
This work is based on Pawel Lenkow work.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d9cc8701f16ed1c2224d0820d69cd5c5362c43df
https://github.com/qemu/qemu/commit/d9cc8701f16ed1c2224d0820d69cd5c5362c43df
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Introduce configuration registers.
Configuration registers for Spansion and Macronix devices.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: cf6f1efe0b573a89597a046631153c5bef20e80d
https://github.com/qemu/qemu/commit/cf6f1efe0b573a89597a046631153c5bef20e80d
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Fast read commands family changes.
Support for Spansion and Macronix flashes.
Additionally Numonyx(Micron) moved from default
in fast read commands family. Also moved fast read
command decoding to functions.
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: dadb2f9078f6ec23140acebd8dbcbc7f0e9289b9
https://github.com/qemu/qemu/commit/dadb2f9078f6ec23140acebd8dbcbc7f0e9289b9
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: New flash devices.
Macronix: mx66u51235f and mx66u1g45g
Micron: mt25ql01g and mt25qu01g
Spansion: s25fs512s and s70fs01gs
Signed-off-by: Marcin Krzeminski <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3830c7a460b8252dc975f8115fdaed8c562d2d75
https://github.com/qemu/qemu/commit/3830c7a460b8252dc975f8115fdaed8c562d2d75
Author: Marcin Krzeminski <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Fix WINBOND fast read command handling
This commit fix obvious bug in WINBOND command handling.
Datasheet states that default dummy cycles is 8 so fix it.
Signed-off-by: Marcin Krzeminski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f12103afaa28b473515ccfcb66c2b42d6d057af0
https://github.com/qemu/qemu/commit/f12103afaa28b473515ccfcb66c2b42d6d057af0
Author: Peter Maydell <address@hidden>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hw/arm/ast2400.c
M hw/arm/palmetto-bmc.c
M hw/block/m25p80.c
M hw/char/cadence_uart.c
M hw/intc/arm_gicv3_cpuif.c
M hw/misc/Makefile.objs
A hw/misc/aspeed_scu.c
M hw/misc/trace-events
M hw/net/cadence_gem.c
M include/hw/arm/ast2400.h
A include/hw/misc/aspeed_scu.h
M tests/Makefile.include
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160627'
into staging
target-arm queue:
* arm_gicv3: add missing 'break' statements
* cadence_uart: protect against transmit errors
* cadence_gem: avoid infinite loops with misconfigured buffer
* cadence_gem: set the 'last' bit when 'wrap' is set
* reenable tmp105 test case
* palmetto-bmc: add ASPEED system control unit model
* m25p80: add new 512Mbit and 1Gbit devices
# gpg: Signature made Mon 27 Jun 2016 15:43:42 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20160627:
m25p80: Fix WINBOND fast read command handling
m25p80: New flash devices.
m25p80: Fast read commands family changes.
m25p80: Introduce configuration registers.
m25p80: Introduce quad and equad modes.
m25p80: Add additional flash commands:
m25p80: Introduce COLLECTING_VAR_LEN_DATA state.
m25p80: Allow more than four banks.
m25p80: Make a table for JEDEC ID.
m25p80: Replace JEDEC ID masking with function.
palmetto-bmc: Configure the SCU's hardware strapping register
ast2400: Integrate the SCU model and set silicon revision
hw/misc: Add a model for the ASPEED System Control Unit
arm: Re-enable tmp105 test
cadence_gem: Set the last bit when wrap is set
cadence_gem: Avoid infinite loops with a misconfigured buffer
cadence_uart: Protect against transmit errors
hw/intc/arm_gicv3: Add missing break
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/aa8151b7df6b...f12103afaa28
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