[Qemu-commits] [qemu/qemu] 17ab14: target/xtensa: add static vectors sel

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[Qemu-commits] [qemu/qemu] 17ab14: target/xtensa: add static vectors sel

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 17ab14: target/xtensa: add static vectors selection
Date:	Wed, 25 Jan 2017 10:00:04 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 17ab14acd488289d2f85ad6212b212c21f050b3d
      
https://github.com/qemu/qemu/commit/17ab14acd488289d2f85ad6212b212c21f050b3d
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/overlay_tool.h

  Log Message:
  -----------
  target/xtensa: add static vectors selection

Xtensa cores may have two distinct addresses for the static vectors
group. Provide a function to select one of them.

Signed-off-by: Max Filippov <address@hidden>


  Commit: bd527a83232ce8b48dac4b8c86607ad8a7e28d98
      
https://github.com/qemu/qemu/commit/bd527a83232ce8b48dac4b8c86607ad8a7e28d98
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.c

  Log Message:
  -----------
  target/xtensa: implement RUNSTALL

RUNSTALL signal stalls core execution while it's applied. It is widely
used in multicore configurations to control activity of additional
cores.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 59a71f75789fb15bac0a67a18325c4ac1acc981c
      
https://github.com/qemu/qemu/commit/59a71f75789fb15bac0a67a18325c4ac1acc981c
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: refactor CCOUNT/CCOMPARE

Xtensa cores may have a register (CCOUNT) that counts core clock cycles.
It may also have a number of registers (CCOMPAREx); when CCOUNT value
passes the value of CCOMPAREx, timer interrupt x is raised.

Currently xtensa target counts a number of completed instructions and
assumes that for CCOUNT one instruction takes one cycle to complete.
It calls helper function to update CCOUNT register at every TB end and
raise timer interrupts. This scheme works very predictably and doesn't
have noticeable performance impact, but it is hard to use with multiple
synchronized processors, especially with coming MTTCG.

Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL.
Use native QEMU timers for CCOMPARE timers, one timer for each register.

Signed-off-by: Max Filippov <address@hidden>


  Commit: d2132510ca88340bed89db5655e65b7cd87d3d8b
      
https://github.com/qemu/qemu/commit/d2132510ca88340bed89db5655e65b7cd87d3d8b
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: support icount

Delimit each instruction that may access timers or IRQ state with
qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with
-icount option.

Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec
recalculate how long this CPU is allowed to run.

RSR now may need to terminate TB, but it can't be done in RSR handler
because the same handler is used for XSR together with WSR handler, which
may also need to terminate TB. Change RSR and WSR handlers return type
to bool indicating whether TB termination is needed (RSR) or has been
done (WSR), and add TB termination after RSR/WSR dispatcher call.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 787eaa4904c53070fd5ad772b93e3683354a4b04
      
https://github.com/qemu/qemu/commit/787eaa4904c53070fd5ad772b93e3683354a4b04
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: don't continue translation after exception

There's no point in continuing translating guest instructions once an
unconditional exception is thrown.
There's also no point in updating pc before any instruction is
translated, don't do it.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 122d302053062af886c2272f1049017cbfdba7b3
      
https://github.com/qemu/qemu/commit/122d302053062af886c2272f1049017cbfdba7b3
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/Makefile

  Log Message:
  -----------
  target/xtensa: tests: run tests with icount

Timer tests expect certain determinism in CCOUNT updates and timer
interrupts firing. Run QEMU with -icount to get deterministic results.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 72b3b8f24a4ada7f6e97fe5cd83e04f94b1f25e0
      
https://github.com/qemu/qemu/commit/72b3b8f24a4ada7f6e97fe5cd83e04f94b1f25e0
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/test_timer.S

  Log Message:
  -----------
  target/xtensa: tests: fix timer tests

Don't expect that CCOUNT increments are equal to the number of executed
instructions. Verify that timer interrupt does not fire before the
programmed CCOMPARE value and does fire after.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 4f89b41c28a17739c4fd40886542e3cb8c7a15a3
      
https://github.com/qemu/qemu/commit/4f89b41c28a17739c4fd40886542e3cb8c7a15a3
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/test_timer.S

  Log Message:
  -----------
  target/xtensa: tests: replace hardcoded interrupt masks

Signed-off-by: Max Filippov <address@hidden>


  Commit: 0a362d0768c443cf9e5c36c8398c92bfebe9b8a4
      
https://github.com/qemu/qemu/commit/0a362d0768c443cf9e5c36c8398c92bfebe9b8a4
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/test_timer.S

  Log Message:
  -----------
  target/xtensa: tests: add ccount write tests

Check that CCOUNT SR is writable and that CCOMPARE timers are updated
when CCOUNT is written to.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 4b37aaa879d508494df14bdc49830cdf8aa77a57
      
https://github.com/qemu/qemu/commit/4b37aaa879d508494df14bdc49830cdf8aa77a57
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/overlay_tool.h

  Log Message:
  -----------
  target/xtensa: fix ICACHE/DCACHE options detection

Configuration overlay does not explicitly say whether there are ICACHE
and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect
if corresponding cache option is enabled, but that's not correct: on
cores without cache these macros are defined as 1, not as 0.
Check XCHAL_[ID]CACHE_SIZE instead.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 9e03ade4411c81a7f7d974dcedf0390835ce4096
      
https://github.com/qemu/qemu/commit/9e03ade4411c81a7f7d974dcedf0390835ce4096
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: implement MEMCTL SR

MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 255d254382aab90a52654ddef4296c806d6d6aad
      
https://github.com/qemu/qemu/commit/255d254382aab90a52654ddef4296c806d6d6aad
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/test_sr.S

  Log Message:
  -----------
  target/xtensa: tests: add memctl test

Signed-off-by: Max Filippov <address@hidden>


  Commit: 8b912ff033cbc2e58476dfdc00fa2b8529c9eb96
      
https://github.com/qemu/qemu/commit/8b912ff033cbc2e58476dfdc00fa2b8529c9eb96
  Author: Max Filippov <address@hidden>
  Date:   2017-01-15 (Sun, 15 Jan 2017)

  Changed paths:
    M tests/tcg/xtensa/test_interrupt.S

  Log Message:
  -----------
  target/xtensa: tests: clean up interrupt tests

Don't use hardcoded software interrupt masks, use XCHAL macros.
Mask off timer interrupt bits that are not checked for.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02
      
https://github.com/qemu/qemu/commit/3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02
  Author: Max Filippov <address@hidden>
  Date:   2017-01-16 (Mon, 16 Jan 2017)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target-xtensa: implement RER/WER instructions

RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: Max Filippov <address@hidden>


  Commit: e32c41e4f65f4d16508fe759a800538a73608839
      
https://github.com/qemu/qemu/commit/e32c41e4f65f4d16508fe759a800538a73608839
  Author: Peter Maydell <address@hidden>
  Date:   2017-01-25 (Wed, 25 Jan 2017)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/overlay_tool.h
    M target/xtensa/translate.c
    M tests/tcg/xtensa/Makefile
    M tests/tcg/xtensa/test_interrupt.S
    M tests/tcg/xtensa/test_sr.S
    M tests/tcg/xtensa/test_timer.S

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into 
staging

target/xtensa updates:

- refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting);
- support icount; run target/xtensa TCG tests with icount;
- implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER.

# gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT
# gpg:                using RSA key 0x51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <address@hidden>"
# gpg:                 aka "Max Filippov <address@hidden>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20170124-xtensa:
  target-xtensa: implement RER/WER instructions
  target/xtensa: tests: clean up interrupt tests
  target/xtensa: tests: add memctl test
  target/xtensa: implement MEMCTL SR
  target/xtensa: fix ICACHE/DCACHE options detection
  target/xtensa: tests: add ccount write tests
  target/xtensa: tests: replace hardcoded interrupt masks
  target/xtensa: tests: fix timer tests
  target/xtensa: tests: run tests with icount
  target/xtensa: don't continue translation after exception
  target/xtensa: support icount
  target/xtensa: refactor CCOUNT/CCOMPARE
  target/xtensa: implement RUNSTALL
  target/xtensa: add static vectors selection

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ae5045ae5b2b...e32c41e4f65f
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