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[Qemu-commits] [qemu/qemu] 68115e: hw/arm/boot: take Linux/arm64 TEXT_OF
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[Qemu-commits] [qemu/qemu] 68115e: hw/arm/boot: take Linux/arm64 TEXT_OFFSET header f... |
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Date: |
Thu, 20 Apr 2017 10:29:11 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 68115ed5fc1915dc4d3244c99937c6667f5ec0e7
https://github.com/qemu/qemu/commit/68115ed5fc1915dc4d3244c99937c6667f5ec0e7
Author: Ard Biesheuvel <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
The arm64 boot protocol stipulates that the kernel must be loaded
TEXT_OFFSET bytes beyond a 2 MB aligned base address, where TEXT_OFFSET
could be any 4 KB multiple between 0 and 2 MB, and whose value can be
found in the header of the Image file.
So after attempts to load the arm64 kernel image as an ELF file or as a
U-Boot image have failed (both of which have their own way of specifying
the load offset), try to determine the TEXT_OFFSET from the image after
loading it but before mapping it as a ROM mapping into the guest address
space.
Signed-off-by: Ard Biesheuvel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f2ad5140fa521bda30b9c3c3db5b6913f6dda1ae
https://github.com/qemu/qemu/commit/f2ad5140fa521bda30b9c3c3db5b6913f6dda1ae
Author: Krzysztof Kozlowski <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/exynos4_boards.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/exynos4210_rtc.c
Log Message:
-----------
hw/arm/exynos: Convert fprintf to qemu_log_mask/error_report
qemu_log_mask() and error_report() are preferred over fprintf() for
logging errors. Also remove square brackets [] and additional new line
characters in printed messages.
Signed-off-by: Krzysztof Kozlowski <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: wrapped long line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 75c6d92e4c0a5128d61d21175d2eed1354e87717
https://github.com/qemu/qemu/commit/75c6d92e4c0a5128d61d21175d2eed1354e87717
Author: Krzysztof Kozlowski <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/char/exynos4210_uart.c
Log Message:
-----------
hw/char/exynos4210_uart: Constify static array and few arguments
The static array exynos4210_uart_regs with register values is not
modified so it can be made const.
Few other functions accept driver or uart state as an argument but they
do not change it and do not cast it so this can be made const for code
safeness.
Signed-off-by: Krzysztof Kozlowski <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 885f27105669b75095912f9fbae57f9260f143fb
https://github.com/qemu/qemu/commit/885f27105669b75095912f9fbae57f9260f143fb
Author: Krzysztof Kozlowski <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/misc/exynos4210_pmu.c
Log Message:
-----------
hw/misc/exynos4210_pmu: Reorder local variables for readability
Short declaration of 'i' was in the middle of declarations with
assignments. Make it a little bit more readable. Additionally switch
from "unsigned" to "unsigned int" as this pattern is more widely used.
No functional change.
Signed-off-by: Krzysztof Kozlowski <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 32b81e620ea562d56ab2733421b5da1082b237a2
https://github.com/qemu/qemu/commit/32b81e620ea562d56ab2733421b5da1082b237a2
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/internals.h
Log Message:
-----------
target/arm: Add missing entries to excnames[] for log strings
Recent changes have added new EXCP_ values to ARM but forgot
to update the excnames[] array which is used to provide
human-readable strings when printing information about the
exception for debug logging. Add the missing entries, and
add a comment to the list of #defines to help avoid the mistake
being repeated in future.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: 2c4a7cc5afb1bfc1728a39abd951ddd7714c476e
https://github.com/qemu/qemu/commit/2c4a7cc5afb1bfc1728a39abd951ddd7714c476e
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
arm: Move excnames[] array into arm_log_exceptions()
The excnames[] array is defined in internals.h because we used
to use it from two different source files for handling logging
of AArch32 and AArch64 exception entry. Refactoring means that
it's now used only in arm_log_exception() in helper.c, so move
the array into that function.
Suggested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 65ed2ed90d9d81fd4b639029be850ea5651f919f
https://github.com/qemu/qemu/commit/65ed2ed90d9d81fd4b639029be850ea5651f919f
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Add assertion about FSC format for syndrome registers
In tlb_fill() we construct a syndrome register value from a
fault status register value which is filled in by arm_tlb_fill().
arm_tlb_fill() returns FSR values which might be in the format
used with short-format page descriptors, or the format used
with long-format (LPAE) descriptors. The syndrome register
always uses LPAE-format FSR status codes.
It isn't actually possible to end up delivering a syndrome
register value to the guest for a fault which is reported
with a short-format FSR (that kind of stage 1 fault will only
happen for an AArch32 translation regime which doesn't have
a syndrome register, and can never be redirected to an AArch64
or Hyp exception level). Add an assertion which checks this,
and adjust the code so that we construct a syndrome with
an invalid status code, rather than allowing set bits in
the FSR input to randomly corrupt other fields in the syndrome.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Commit: df3692e04b2562327024eefeb855c9373a822bab
https://github.com/qemu/qemu/commit/df3692e04b2562327024eefeb855c9373a822bab
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
stellaris: Don't hw_error() on bad register accesses
Current recommended style is to log a guest error on bad register
accesses, not kill the whole system with hw_error(). Change the
hw_error() calls to log as LOG_GUEST_ERROR or LOG_UNIMP or use
g_assert_not_reached() as appropriate.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: dffc58519e6a9aac3e40c10c1d375cfd4d568aed
https://github.com/qemu/qemu/commit/dffc58519e6a9aac3e40c10c1d375cfd4d568aed
Author: Ishani Chugh <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/kvm64.c
Log Message:
-----------
arm/kvm: Remove trailing newlines from error_report()
Signed-off-by: Ishani Chugh <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0493a139c976e6e3436c7ea905f046db00a41ae3
https://github.com/qemu/qemu/commit/0493a139c976e6e3436c7ea905f046db00a41ae3
Author: Suramya Shah <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/pxa2xx.c
Log Message:
-----------
hw/arm: Qomify pxa2xx.c
Signed-off-by: Suramya Shah <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 75b7760212b2cfa86977704a2c19a0d8daced5be
https://github.com/qemu/qemu/commit/75b7760212b2cfa86977704a2c19a0d8daced5be
Author: Alistair Francis <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
cadence_gem: Read the correct queue descriptor
Read the correct descriptor instead of hardcoding the first (q=0).
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: dacc0566acda512ebaf18ad051b387a56a3f7253
https://github.com/qemu/qemu/commit/dacc0566acda512ebaf18ad051b387a56a3f7253
Author: Alistair Francis <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
cadence_gem: Correct the multi-queue can rx logic
Correct the buffer descriptor busy logic to work correctly when using
multiple queues.
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Commit: 596b6f51b71eb1dd6f603b3f5aeb0a2f9300b21f
https://github.com/qemu/qemu/commit/596b6f51b71eb1dd6f603b3f5aeb0a2f9300b21f
Author: Alistair Francis <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/net/cadence_gem.c
Log Message:
-----------
cadence_gem: Correct the interupt logic
This patch fixes two mistakes in the interrupt logic.
First we only trigger single-queue or multi-queue interrupts if the status
register is set. This logic was already used for non multi-queue interrupts
but it also applies to multi-queue interrupts.
Secondly we need to lower the interrupts if the ISR isn't set. As part
of this we can remove the other interrupt lowering logic and consolidate
it inside gem_update_int_status().
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Commit: a5517666b21b85f1a02c7accf297938acb720699
https://github.com/qemu/qemu/commit/a5517666b21b85f1a02c7accf297938acb720699
Author: Alistair Francis <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/net/cadence_gem.c
M include/hw/net/cadence_gem.h
Log Message:
-----------
cadence_gem: Make the revision a property
Expose the Cadence GEM revision as a property.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 20bff2130753b5b38d90afee83f2b43a803bc320
https://github.com/qemu/qemu/commit/20bff2130753b5b38d90afee83f2b43a803bc320
Author: Alistair Francis <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/xlnx-zynqmp.c
Log Message:
-----------
xlnx-zynqmp: Set the Cadence GEM revision
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9d7c59c84d4530d05e8702b1c3a31e6da00a397e
https://github.com/qemu/qemu/commit/9d7c59c84d4530d05e8702b1c3a31e6da00a397e
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Don't implement BXJ on M-profile CPUs
For M-profile CPUs, the BXJ instruction does not exist at all, and
the encoding should always UNDEF. We were accidentally implementing
it to behave like A-profile BXJ; correct the error.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: bedb8a6b09c1754c3b9f155750c62dc087706698
https://github.com/qemu/qemu/commit/bedb8a6b09c1754c3b9f155750c62dc087706698
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Thumb shift operations should not permit interworking branches
In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.
When we added support for doing interworking branches on writes to
PC from data processing instructions in commit 21aeb3430ce7ba, we
accidentally changed a Thumb instruction to have interworking
branch behaviour for writes to PC. (MOV, MOVS register-shifted
register, encoding T2; this is the standard encoding for
LSL/LSR/ASR/ROR (register).)
For this encoding, behaviour with Rd == R15 is specified as
UNPREDICTABLE, so allowing an interworking branch is within
spec, but it's confusing and differs from our handling of this
class of UNPREDICTABLE for other Thumb ALU operations. Make
it perform a simple (non-interworking) branch like the others.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 5425415ebba5fa20558e1ef25e1997a6f5ea4c7c
https://github.com/qemu/qemu/commit/5425415ebba5fa20558e1ef25e1997a6f5ea4c7c
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Factor out "generate right kind of step exception"
We currently have two places that do:
if (dc->ss_active) {
gen_step_complete_exception(dc);
} else {
gen_exception_internal(EXCP_DEBUG);
}
Factor this out into its own function, as we're about to add
a third place that needs the same logic.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 4d5e8c969a74c86124fc2284ea603cc6dd3c5dfa
https://github.com/qemu/qemu/commit/4d5e8c969a74c86124fc2284ea603cc6dd3c5dfa
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
Move the utility routines gen_set_condexec() and gen_set_pc_im()
up in the file, as we will want to use them from a function
placed earlier in the file than their current location.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f021b2c4627890d82fbcc300db3bd782b37b7f8a
https://github.com/qemu/qemu/commit/f021b2c4627890d82fbcc300db3bd782b37b7f8a
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Move condition-failed codepath generation out of if()
Move the code to generate the "condition failed" instruction
codepath out of the if (singlestepping) {} else {}. This
will allow adding support for handling a new is_jmp type
which can't be neatly split into "singlestepping case"
versus "not singlestepping case".
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: b636649f5a2e108413dd171edaf320f781f57942
https://github.com/qemu/qemu/commit/b636649f5a2e108413dd171edaf320f781f57942
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
arm: Abstract out "are we singlestepping" test to utility function
We now test for "are we singlestepping" in several places and
it's not a trivial check because we need to care about both
architectural singlestep and QEMU gdbstub singlestep. We're
also about to add another place that needs to make this check,
so pull the condition out into a function.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 064c379c99b835bdcc478d21a3849507ea07d53a
https://github.com/qemu/qemu/commit/064c379c99b835bdcc478d21a3849507ea07d53a
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
arm: Track M profile handler mode state in TB flags
For M profile exception-return handling we'd like to generate different
code for some instructions depending on whether we are in Handler
mode or Thread mode. This isn't the same as "are we privileged
or user", so we need an extra bit in the TB flags to distinguish.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 3bb8a96f5348913ee130169504f3642f501b113e
https://github.com/qemu/qemu/commit/3bb8a96f5348913ee130169504f3642f501b113e
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
arm: Implement M profile exception return properly
On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
* POP or LDM which loads the PC
* LDR to PC
* BX register
and the new PC value is 0xFFxxxxxx.
QEMU tries to implement this by not treating the instruction
specially but then catching the attempt to execute from the magic
address value. This is not ideal, because:
* there are guest visible differences from the architecturally
specified behaviour (for instance jumping to 0xFFxxxxxx via a
different instruction should not cause an exception return but it
will in the QEMU implementation)
* we have to account for it in various places (like refusing to take
an interrupt if the PC is at a magic value, and making sure that
the MPU doesn't deny execution at the magic value addresses)
Drop these hacks, and instead implement exception return the way the
architecture specifies -- by having the relevant instructions check
for the magic value and raise the 'do an exception return' QEMU
internal exception immediately.
The effect on the generated code is minor:
bx lr, old code (and new code for Thread mode):
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
exit_tb $0x0
set_label $L0
exit_tb $0x7f2aabd61993
x86_64 generated code:
0x7f2aabe87019: mov %ebx,%ebp
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
0x7f2aabe87022: and $0x1,%ebx
0x7f2aabe87025: mov %ebx,0x218(%r14)
0x7f2aabe8702c: xor %eax,%eax
0x7f2aabe8702e: jmpq 0x7f2aabe7c016
bx lr, new code when in Handler mode:
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
movi_i32 tmp5,$0xffffffffff000000
brcond_i32 pc,tmp5,geu,$L1
exit_tb $0x0
set_label $L1
movi_i32 tmp5,$0x8
call exception_internal,$0x0,$0,env,tmp5
x86_64 generated code:
0x7fe8fa1264e3: mov %ebp,%ebx
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
0x7fe8fa1264ec: and $0x1,%ebp
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
0x7fe8fa1264f6: cmp $0xff000000,%ebx
0x7fe8fa1264fc: jae 0x7fe8fa126509
0x7fe8fa126502: xor %eax,%eax
0x7fe8fa126504: jmpq 0x7fe8fa122016
0x7fe8fa126509: mov %r14,%rdi
0x7fe8fa12650c: mov $0x8,%esi
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
0x7fe8fa12651b: callq *%r10
which is a difference of one cmp/branch-not-taken. This will
be lost in the noise of having to exit generated code and
look up the next TB anyway.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa
https://github.com/qemu/qemu/commit/f4e8e4edda875cab9df91dc4ae9767f7cb1f50aa
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M target/arm/cpu.c
M target/arm/translate.c
Log Message:
-----------
arm: Remove workarounds for old M-profile exception return implementation
Now that we've rewritten M-profile exception return so that the magic
PC values are not visible to other parts of QEMU, we can delete the
special casing of them elsewhere.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: da92ada855036c55bd08b0b0c64c7551d56f3586
https://github.com/qemu/qemu/commit/da92ada855036c55bd08b0b0c64c7551d56f3586
Author: Peter Maydell <address@hidden>
Date: 2017-04-20 (Thu, 20 Apr 2017)
Changed paths:
M hw/arm/boot.c
M hw/arm/exynos4_boards.c
M hw/arm/pxa2xx.c
M hw/arm/stellaris.c
M hw/arm/xlnx-zynqmp.c
M hw/char/exynos4210_uart.c
M hw/misc/exynos4210_pmu.c
M hw/net/cadence_gem.c
M hw/timer/exynos4210_mct.c
M hw/timer/exynos4210_pwm.c
M hw/timer/exynos4210_rtc.c
M include/hw/net/cadence_gem.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/arm/op_helper.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170420'
into staging
target-arm queue:
* implement M profile exception return properly
* cadence GEM: fix multiqueue handling bugs
* pxa2xx.c: QOMify a device
* arm/kvm: Remove trailing newlines from error_report()
* stellaris: Don't hw_error() on bad register accesses
* Add assertion about FSC format for syndrome registers
* Move excnames[] array into arm_log_exceptions()
* exynos: minor code cleanups
* hw/arm/boot: take Linux/arm64 TEXT_OFFSET header field into account
* Fix APSR writes via M profile MSR
# gpg: Signature made Thu 20 Apr 2017 17:39:35 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170420: (24 commits)
arm: Remove workarounds for old M-profile exception return implementation
arm: Implement M profile exception return properly
arm: Track M profile handler mode state in TB flags
arm: Abstract out "are we singlestepping" test to utility function
arm: Move condition-failed codepath generation out of if()
arm: Move gen_set_condexec() and gen_set_pc_im() up in the file
arm: Factor out "generate right kind of step exception"
arm: Thumb shift operations should not permit interworking branches
arm: Don't implement BXJ on M-profile CPUs
xlnx-zynqmp: Set the Cadence GEM revision
cadence_gem: Make the revision a property
cadence_gem: Correct the interupt logic
cadence_gem: Correct the multi-queue can rx logic
cadence_gem: Read the correct queue descriptor
hw/arm: Qomify pxa2xx.c
arm/kvm: Remove trailing newlines from error_report()
stellaris: Don't hw_error() on bad register accesses
target/arm: Add assertion about FSC format for syndrome registers
arm: Move excnames[] array into arm_log_exceptions()
target/arm: Add missing entries to excnames[] for log strings
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/64c8ed97ccea...da92ada85503
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