[Qemu-commits] [qemu/qemu] 853406: target-microblaze: dec

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[Qemu-commits] [qemu/qemu] 853406: target-microblaze: dec_load: Use bool

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 853406: target-microblaze: dec_load: Use bool instead of u...
Date:	Tue, 29 May 2018 05:52:36 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8534063a38583f1e0458daf076154131a83fa0e0
      
https://github.com/qemu/qemu/commit/8534063a38583f1e0458daf076154131a83fa0e0
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_load: Use bool instead of unsigned int

Use bool instead of unsigned int to represent flags.
No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: b51b3d43deeb9880b383603806daedf125ae9cce
      
https://github.com/qemu/qemu/commit/b51b3d43deeb9880b383603806daedf125ae9cce
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_store: Use bool instead of unsigned int

Use bool instead of unsigned int to represent flags.
Also, use extract32 instead of open coding the bit extract.

No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 0e9033c8c53c3839871c59ef431bcfdc9359d0c1
      
https://github.com/qemu/qemu/commit/0e9033c8c53c3839871c59ef431bcfdc9359d0c1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: compute_ldst_addr: Use bool instead of int

Use bool instead of int to represent flags.
No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 4c8ac10737ae38256d59406801591d9dca2bd69b
      
https://github.com/qemu/qemu/commit/4c8ac10737ae38256d59406801591d9dca2bd69b
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.c

  Log Message:
  -----------
  target-microblaze: Fallback to our latest CPU version

Today, when running QEMU in linux-user or with boards that don't
select a specific CPU version, we treat it as an invalid version
and log a message.

Instead, if no specific version was selected, fallback to our
latest CPU version.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 5c594ef3c77c7226e7b2080430b9b74d26d5bd7e
      
https://github.com/qemu/qemu/commit/5c594ef3c77c7226e7b2080430b9b74d26d5bd7e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Correct special register array sizes

Correct special register array sizes.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: c56911a424c5279a5113c4e1d508733a60c12dbc
      
https://github.com/qemu/qemu/commit/c56911a424c5279a5113c4e1d508733a60c12dbc
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h

  Log Message:
  -----------
  target-microblaze: Correct the PVR array size

Correct the PVR array size, there are 13 PVR registers.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: cfeea807e5af996979b2c13ab3b6eb447e1796bb
      
https://github.com/qemu/qemu/commit/cfeea807e5af996979b2c13ab3b6eb447e1796bb
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Tighten up TCGv_i32 vs TCGv type usage

Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when
TCGv_i32 should be used.

This is in preparation for adding 64bit addressing support.
No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: a17f7c05f07aa3a825f7dc1ba22d70df16098d3c
      
https://github.com/qemu/qemu/commit/a17f7c05f07aa3a825f7dc1ba22d70df16098d3c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/helper.c

  Log Message:
  -----------
  target-microblaze: Remove USE_MMU PVR checks

We already have a CPU property to control if a core has
an MMU or not. Remove USE_MMU PVR checks in favor of
looking at the property.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 9e50a927b4e2e724849f6ec19fa55fe40e13d174
      
https://github.com/qemu/qemu/commit/9e50a927b4e2e724849f6ec19fa55fe40e13d174
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.c

  Log Message:
  -----------
  target-microblaze: Conditionalize setting of PVR11_USE_MMU

Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: a2de5ca451354155a0d6a9b098cbdd44eabb2da5
      
https://github.com/qemu/qemu/commit/a2de5ca451354155a0d6a9b098cbdd44eabb2da5
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/helper.c

  Log Message:
  -----------
  target-microblaze: Bypass MMU with MMU_NOMMU_IDX

Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 0dc4af5c1a0e8d3f73b176f8fd3159e77a4c2492
      
https://github.com/qemu/qemu/commit/0dc4af5c1a0e8d3f73b176f8fd3159e77a4c2492
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Make compute_ldst_addr always use a temp

Make compute_ldst_addr always use a temp. This simplifies
the code a bit in preparation for adding support for
64bit addresses.

No functional change.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 0a87e691b3924d5e3964dd1b77eb88b000dd4126
      
https://github.com/qemu/qemu/commit/0a87e691b3924d5e3964dd1b77eb88b000dd4126
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Remove pointer indirection for ld/st addresses

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 403322ea6c383b3337fe3c52d9ed84958f94bcd1
      
https://github.com/qemu/qemu/commit/403322ea6c383b3337fe3c52d9ed84958f94bcd1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h
    M target/microblaze/helper.h
    M target/microblaze/op_helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Use TCGv for load/store addresses

Use TCGv for load/store addresses, allowing for future
computation of 64-bit load/store address.

No functional change.

Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 0031eef23ac0850cb04f6932ba8c42d2d6e712f2
      
https://github.com/qemu/qemu/commit/0031eef23ac0850cb04f6932ba8c42d2d6e712f2
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Name special registers we support

Name special registers we support.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: bdfc1e886939f06b94f4fee3105a41dbd20a97db
      
https://github.com/qemu/qemu/commit/bdfc1e886939f06b94f4fee3105a41dbd20a97db
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Break out trap_userspace()

Break out trap_userspace() to avoid open coding it everywhere.
For privileged insns, we now always stop translation of the
current insn for cores without exceptions.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 9ba8cd452bb48ad63e2878f8ebef4cfb18f46812
      
https://github.com/qemu/qemu/commit/9ba8cd452bb48ad63e2878f8ebef4cfb18f46812
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Break out trap_illegal()

Break out trap_illegal() to handle illegal operation traps.
We now generally stop translation of the current insn if
it's not valid.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 2023e9a3bcb514a5fd41644c63825109c286e4ef
      
https://github.com/qemu/qemu/commit/2023e9a3bcb514a5fd41644c63825109c286e4ef
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_msr: Use bool and extract32

Use bool and extract32 to represent the to, clr and
clrset flags.

No functional change.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 351527b712f74749c23fdaf47be227903f0c2592
      
https://github.com/qemu/qemu/commit/351527b712f74749c23fdaf47be227903f0c2592
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_msr: Reuse more code when reg-decoding

Reuse more code when decoding register numbers.

No functional changes.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: ab6dd3808d52b96347a4595f9da77c46df1a5e1d
      
https://github.com/qemu/qemu/commit/ab6dd3808d52b96347a4595f9da77c46df1a5e1d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_msr: Fix MTS to FSR

Fix moves to FSR. Not only bit 31 is accessible.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 0a22f8cf3ec1716865d635688fbfb31402c0ba7a
      
https://github.com/qemu/qemu/commit/0a22f8cf3ec1716865d635688fbfb31402c0ba7a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M linux-user/microblaze/cpu_loop.c
    M target/microblaze/cpu.h
    M target/microblaze/helper.c
    M target/microblaze/mmu.c
    M target/microblaze/op_helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Make special registers 64-bit

Extend special registers to 64-bits. This is in preparation for
MFSE/MTSE, moves to and from extended special registers.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: be73ef6423fbe1f06c912a67d6d066d257c11e18
      
https://github.com/qemu/qemu/commit/be73ef6423fbe1f06c912a67d6d066d257c11e18
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M configure
    M target/microblaze/cpu.h

  Log Message:
  -----------
  target-microblaze: Setup for 64bit addressing

Setup MicroBlaze builds for 64bit addressing.
No functional change since the translator does not yet
emit 64bit addresses.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: d248e1beac9a640c033cc7d3c3d494576a74bbc0
      
https://github.com/qemu/qemu/commit/d248e1beac9a640c033cc7d3c3d494576a74bbc0
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Add Extended Addressing

Add support for Extended Addressing. Load/stores with EA
enabled concatenate two 32bit registers to form an extended
address.

We don't allow users to enable address sizes larger than
32 bits quite yet though. Once the MMU support is in, we'll
turn it on.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: a1b48e3a3aa19d6e03b6c39cae4e915f5cceb028
      
https://github.com/qemu/qemu/commit/a1b48e3a3aa19d6e03b6c39cae4e915f5cceb028
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Implement MFSE EAR

Implement MFSE EAR to enable access to the upper part of EAR.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: a2207b593b6d7e164e6d4a587aec4cd885a8e855
      
https://github.com/qemu/qemu/commit/a2207b593b6d7e164e6d4a587aec4cd885a8e855
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h

  Log Message:
  -----------
  target-microblaze: mmu: Add R_TBLX_MISS macros

Add a R_TBLX_MISS MASK and SHIFT macros.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 96716533afa039b4698360af221a8c399367f91d
      
https://github.com/qemu/qemu/commit/96716533afa039b4698360af221a8c399367f91d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h

  Log Message:
  -----------
  target-microblaze: mmu: Remove unused register state

Add explicit handling for MMU_R_TLBX and log accesses to
invalid MMU registers. We can now remove the state for
all regs but PID, ZPR and TLBX (0 - 2).

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: d2f004c3cdcb786303057683252112c3ff7b337e
      
https://github.com/qemu/qemu/commit/d2f004c3cdcb786303057683252112c3ff7b337e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h

  Log Message:
  -----------
  target-microblaze: mmu: Prepare for 64-bit addresses

Prepare for 64-bit addresses.
This makes no functional difference as the upper parts of
the 64-bit addresses are not yet reachable.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 3924a9aa02fa00a256ddcfe2d6a08bc410ddcaaf
      
https://github.com/qemu/qemu/commit/3924a9aa02fa00a256ddcfe2d6a08bc410ddcaaf
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.c
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h

  Log Message:
  -----------
  target-microblaze: mmu: Add a configurable output address mask

Add a configurable output address mask, used to mimic the
configurable physical address bit width.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 05a9a6519c9127b5fb0b13481ecc0e72331c8a38
      
https://github.com/qemu/qemu/commit/05a9a6519c9127b5fb0b13481ecc0e72331c8a38
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: dec_msr: Plug a temp leak

Plug a temp leak.

Reported-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: f0f7e7f7b284f536389a3c5b67de681055325317
      
https://github.com/qemu/qemu/commit/f0f7e7f7b284f536389a3c5b67de681055325317
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/helper.h
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h
    M target/microblaze/op_helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Add support for extended access to TLBLO

Add support for extended access to TLBLO's upper 32 bits.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 25ec2fdd7bb4957f15fa6153bf446d43dd7acb3e
      
https://github.com/qemu/qemu/commit/25ec2fdd7bb4957f15fa6153bf446d43dd7acb3e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.c

  Log Message:
  -----------
  target-microblaze: Allow address sizes between 32 and 64 bits

Allow address sizes between 32 and 64 bits.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: f7a66e3a8602b0498d340e5de959fbcf738a19b6
      
https://github.com/qemu/qemu/commit/f7a66e3a8602b0498d340e5de959fbcf738a19b6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Simplify address computation using tcg_gen_addi_i32()

Simplify address computation using tcg_gen_addi_i32().
tcg_gen_addi_i32() already optimizes the case when the
immediate is zero.

No functional change.

Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 75c9ddce5d069c27b91e75127f969f32842cb664
      
https://github.com/qemu/qemu/commit/75c9ddce5d069c27b91e75127f969f32842cb664
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/mmu.c

  Log Message:
  -----------
  target-microblaze: mmu: Cleanup debug log messages

Cleanup debug log messages:
* Avoid long 80+ character lines.
* Remove D() macro and use qemu_log_mask.
* Remove logs that are not very useful

Suggested-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: d89b86e9129a7c21a453fc495fc52b062708e8dc
      
https://github.com/qemu/qemu/commit/d89b86e9129a7c21a453fc495fc52b062708e8dc
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Use table based condition-codes conversion

Use a table based conversion to map condition-codes between
MicroBlaze ISA encoding and TCG.
No functional change.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 9e6e1828b62094a9f44f01de3da5e9c5109d54b0
      
https://github.com/qemu/qemu/commit/9e6e1828b62094a9f44f01de3da5e9c5109d54b0
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Remove argument b in eval_cc()

Remove argument b in eval_cc() as it is always set to zero.
No functional change.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 43d318b220f52f3080293375a4d8c741b26e3563
      
https://github.com/qemu/qemu/commit/43d318b220f52f3080293375a4d8c741b26e3563
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h
    M target/microblaze/op_helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Convert env_btarget to i64

Convert env_btarget to i64.
No functional change.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: e956caf2a6f1ba6e769b6e414b0a33aabae106c0
      
https://github.com/qemu/qemu/commit/e956caf2a6f1ba6e769b6e414b0a33aabae106c0
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/translate.c

  Log Message:
  -----------
  target-microblaze: Use tcg_gen_movcond in eval_cond_jmp

Cleanup eval_cond_jmp to use tcg_gen_movcond_i64().
No functional change.

Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: 923ce2e6af7f8228d2ccb3ff272ea0fad855618c
      
https://github.com/qemu/qemu/commit/923ce2e6af7f8228d2ccb3ff272ea0fad855618c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h

  Log Message:
  -----------
  target-microblaze: cpu_mmu_index: Fixup indentation

Fixup the indentation of cpu_mmu_index in preparation for
future edits.
No functional changes.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: d10367e035eab12c77b83b5985915ff7f003de1f
      
https://github.com/qemu/qemu/commit/d10367e035eab12c77b83b5985915ff7f003de1f
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M target/microblaze/cpu.h
    M target/microblaze/helper.c

  Log Message:
  -----------
  target-microblaze: Consolidate MMU enabled checks

Consolidate MMU enabled checks to cpu_mmu_index().
No functional changes.

Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>


  Commit: e609fa71e89c81fbe2670411be62da95dfb093e0
      
https://github.com/qemu/qemu/commit/e609fa71e89c81fbe2670411be62da95dfb093e0
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-29 (Tue, 29 May 2018)

  Changed paths:
    M configure
    M linux-user/microblaze/cpu_loop.c
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/microblaze/helper.c
    M target/microblaze/helper.h
    M target/microblaze/mmu.c
    M target/microblaze/mmu.h
    M target/microblaze/op_helper.c
    M target/microblaze/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging

Tag edgar/xilinx-next-2018-05-29-v1.for-upstream

# gpg: Signature made Tue 29 May 2018 09:58:30 BST
# gpg:                using RSA key 29C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <address@hidden>"
# gpg:                 aka "Edgar E. Iglesias <address@hidden>"
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits)
  target-microblaze: Consolidate MMU enabled checks
  target-microblaze: cpu_mmu_index: Fixup indentation
  target-microblaze: Use tcg_gen_movcond in eval_cond_jmp
  target-microblaze: Convert env_btarget to i64
  target-microblaze: Remove argument b in eval_cc()
  target-microblaze: Use table based condition-codes conversion
  target-microblaze: mmu: Cleanup debug log messages
  target-microblaze: Simplify address computation using tcg_gen_addi_i32()
  target-microblaze: Allow address sizes between 32 and 64 bits
  target-microblaze: Add support for extended access to TLBLO
  target-microblaze: dec_msr: Plug a temp leak
  target-microblaze: mmu: Add a configurable output address mask
  target-microblaze: mmu: Prepare for 64-bit addresses
  target-microblaze: mmu: Remove unused register state
  target-microblaze: mmu: Add R_TBLX_MISS macros
  target-microblaze: Implement MFSE EAR
  target-microblaze: Add Extended Addressing
  target-microblaze: Setup for 64bit addressing
  target-microblaze: Make special registers 64-bit
  target-microblaze: dec_msr: Fix MTS to FSR
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/dcd425608240...e609fa71e89c
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