[Qemu-commits] [qemu/qemu] b7d678: mac_dbdma: only dump commands for deb

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[Qemu-commits] [qemu/qemu] b7d678: mac_dbdma: only dump commands for deb

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] b7d678: mac_dbdma: only dump commands for debug enabled ch...
Date:	Tue, 03 Jul 2018 08:04:24 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b7d678135f0294489e0458ef97088e848d08dfb5
      
https://github.com/qemu/qemu/commit/b7d678135f0294489e0458ef97088e848d08dfb5
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/misc/macio/mac_dbdma.c

  Log Message:
  -----------
  mac_dbdma: only dump commands for debug enabled channels

This enables us to apply the same filter in DEBUG_DBDMA_CHANMASK to the
DBDMA command execution debug output.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5107a9cb431b816af6d7e450c22b044198bc6d18
      
https://github.com/qemu/qemu/commit/5107a9cb431b816af6d7e450c22b044198bc6d18
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  mac_newworld: always enable disable_direct_reg3_writes for ADB machines

Commit 84051eb400 "adb: add property to disable direct reg 3 writes" added a
workaround for MacOS 9 incorrectly setting the mouse address during boot of
PMU machines.

Further testing has shown that since fb6649f172 "adb: fix read reg 3 byte
ordering" this can still sometimes happen with the CUDA mac99 machine,
so let's enable this workaround for all New World machines using ADB for now.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 43f7868da3c84c1c7eef89631ab0bf6dc194eedb
      
https://github.com/qemu/qemu/commit/43f7868da3c84c1c7eef89631ab0bf6dc194eedb
  Author: Guenter Roeck <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/sam460ex.c

  Log Message:
  -----------
  sam460ex: Fix sam460ex device tree when booting the Linux kernel

sam460ex (or at least this emulation) does not support the "ibm,cpm" power
management. As a result, Linux crashes when trying to access it. Remove
its device tree node. Also, if/when we boot the Linux kernel directly,
serial port clock frequencies in the device tree file will be unset, and
serial port initialization will fail. Add valid frequency values to
the serial ports to be able to use it. Also set valid values for the other
clock nodes otherwise set by u-boot.

Signed-off-by: Guenter Roeck <address@hidden>
Reviewed-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a028dd423ee6dfd091a8c63028240832bf10f671
      
https://github.com/qemu/qemu/commit/a028dd423ee6dfd091a8c63028240832bf10f671
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/intc/xics_pnv.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: introduce ICP DeviceRealize and DeviceReset handlers

This changes the ICP realize and reset handlers in DeviceRealize and
DeviceReset handlers. parent handlers are now called from the
inheriting classes which is a cleaner object pattern.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0a647b76dbf29e6a20c328cd8676a1ca49526f09
      
https://github.com/qemu/qemu/commit/0a647b76dbf29e6a20c328cd8676a1ca49526f09
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppc/xics: introduce a parent_realize in ICSStateClass

This makes possible to move the common ICSState code of the realize
handlers in the ics-base class.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 815049a01ba187d48166f0144356bc640d4e5803
      
https://github.com/qemu/qemu/commit/815049a01ba187d48166f0144356bc640d4e5803
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics.c

  Log Message:
  -----------
  ppc/xics: move the instance_init handler under the ics-base class

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eeefd43b3cf342d1696128462a16e092995ff1b5
      
https://github.com/qemu/qemu/commit/eeefd43b3cf342d1696128462a16e092995ff1b5
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  ppx/xics: introduce a parent_reset in ICSStateClass

Just like for the realize handlers, this makes possible to move the
common ICSState code of the reset handlers in the ics-base class.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c8b1846f238ea5702ccbc0c3e2760c8fee875808
      
https://github.com/qemu/qemu/commit/c8b1846f238ea5702ccbc0c3e2760c8fee875808
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics.c

  Log Message:
  -----------
  ppc/xics: move the vmstate structures under the ics-base class

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: abe82ebb2005eef846fd62652b0107d268c8e06f
      
https://github.com/qemu/qemu/commit/abe82ebb2005eef846fd62652b0107d268c8e06f
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/intc/xics_kvm.c
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc/xics: rework the ICS classes inheritance tree

With the previous changes, we can now let the ICS_KVM class inherit
directly from ICS_BASE class and not from the intermediate ICS_SIMPLE.
It makes the class hierarchy much cleaner.

What is left in the top classes is the low level interface to access
the KVM XICS device in ICS_KVM and the XICS emulating handlers in
ICS_SIMPLE.

This should not break migration compatibility.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 56f68439213f4fc002c602cee6f4e6863609cb88
      
https://github.com/qemu/qemu/commit/56f68439213f4fc002c602cee6f4e6863609cb88
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/pnv_core.c

  Log Message:
  -----------
  ppc/pnv: fix pnv_core_realize() error handling

commit d35aefa9ae15 ("ppc/pnv: introduce a new intc_create() operation
to the chip model") changed the object link in the pnv_core_realize()
routine but a return was forgotten in case of error, which can lead to
more problems afterwards (segv)

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0f3110fa67d3c3405202104f4833f1780e1a32bb
      
https://github.com/qemu/qemu/commit/0f3110fa67d3c3405202104f4833f1780e1a32bb
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/excp_helper.c
    M target/ppc/internal.h
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  target/ppc: Add do_unaligned_access hook

This allows faults from MO_ALIGN to have the same effect
as from gen_check_align.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 94bf2658676be00b6f2b4db5d1788122217665b0
      
https://github.com/qemu/qemu/commit/94bf2658676be00b6f2b4db5d1788122217665b0
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/helper.h
    M target/ppc/mem_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use atomic load for LQ and LQARX

Section 1.4 of the Power ISA v3.0B states that both of these
instructions are single-copy atomic.  As we cannot (yet) issue
128-bit loads within TCG, use the generic helpers provided.

Since TCG cannot (yet) return a 128-bit value, add a slot within
CPUPPCState for returning the high half of a 128-bit return value.
This solution is preferred to the helper assigning to architectural
registers directly, as it avoids clobbering all TCG live values.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f89ced5f556a06986d362dd41a99dfc4dc960fc1
      
https://github.com/qemu/qemu/commit/f89ced5f556a06986d362dd41a99dfc4dc960fc1
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/mem_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use atomic store for STQ

Section 1.4 of the Power ISA v3.0B states that this insn is
single-copy atomic.  As we cannot (yet) issue 128-bit stores
within TCG, use the generic helpers provided.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4a9b3c5dd30cfd548d447521d4ef1fdba6f0fcf2
      
https://github.com/qemu/qemu/commit/4a9b3c5dd30cfd548d447521d4ef1fdba6f0fcf2
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/mem_helper.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use atomic cmpxchg for STQCX

When running in a parallel context, we must use a helper in order
to perform the 128-bit atomic operation.  When running in a serial
context, do the compare before the store.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 14db18997eb29b79f6c538c1a3cd27df259f77a6
      
https://github.com/qemu/qemu/commit/14db18997eb29b79f6c538c1a3cd27df259f77a6
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M linux-user/ppc/cpu_loop.c
    M target/ppc/cpu.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Remove POWERPC_EXCP_STCX

Always use the gen_conditional_store implementation that uses
atomic_cmpxchg.  Make sure and clear reserve_addr across most
interrupts crossing the cpu_loop.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d8b86898275827089c3ea10d1c83fcbab50abb3b
      
https://github.com/qemu/qemu/commit/d8b86898275827089c3ea10d1c83fcbab50abb3b
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Tidy gen_conditional_store

Leave only the minimal amount of code within the STCX macro,
moving the rest of the code into gen_conditional_store.
Remove the explicit call to gen_check_align; the matching LDAX will
have already checked alignment, and we verify the same address.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2a4e6c1bffe11a982f6774fe01049debf07703fc
      
https://github.com/qemu/qemu/commit/2a4e6c1bffe11a982f6774fe01049debf07703fc
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Split out gen_load_locked

Leave only the minimal amount of code within the LDAR macro,
moving the rest of the code into gen_load_locked.  Use MO_ALIGN
and remove the explicit call to gen_check_align.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 20ba8504a64cb4f008bc32ed9806c56ade036663
      
https://github.com/qemu/qemu/commit/20ba8504a64cb4f008bc32ed9806c56ade036663
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Split out gen_ld_atomic

Move the guts of LD_ATOMIC to a function.  Use foo_tl for the operations
instead of foo_i32 or foo_i64 specifically.  Use MO_ALIGN instead of an
explicit call to gen_check_align.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9deb041cbda9eae6365c88ca42353b4a644aeb09
      
https://github.com/qemu/qemu/commit/9deb041cbda9eae6365c88ca42353b4a644aeb09
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Split out gen_st_atomic

Move the guts of ST_ATOMIC to a function.  Use foo_tl for the operations
instead of foo_i32 or foo_i64 specifically.  Use MO_ALIGN instead of an
explicit call to gen_check_align.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c674a9831e8bf58928508e2db604e092c66638a4
      
https://github.com/qemu/qemu/commit/c674a9831e8bf58928508e2db604e092c66638a4
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use MO_ALIGN for EXIWX and ECOWX

This avoids the need for gen_check_align entirely.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b8ce0f86782b1317f363cc90f4e1aaeb116a7cc2
      
https://github.com/qemu/qemu/commit/b8ce0f86782b1317f363cc90f4e1aaeb116a7cc2
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use atomic min/max helpers

These operations were previously unimplemented for ppc.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 20923c1d02b68dfd848f014a77747c0e4817682a
      
https://github.com/qemu/qemu/commit/20923c1d02b68dfd848f014a77747c0e4817682a
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Implement the rest of gen_ld_atomic

These cases were stubbed out.  For now, implement them only within
a serial context, forcing parallel execution to synchronize.  It
would be possible to implement these with cmpxchg loops, if we care.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7fbc2b20d2e0ca1898bfc2bd871fb674ec1039fb
      
https://github.com/qemu/qemu/commit/7fbc2b20d2e0ca1898bfc2bd871fb674ec1039fb
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Implement the rest of gen_st_atomic

The store twin case was stubbed out.  For now, implement it only within
a serial context, forcing parallel execution to synchronize.  It would
be possible to implement with a cmpxchg loop, if we care, but the loose
alignment requirements (simply no crossing 32-byte boundary) might send
us back to the serial context anyway.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9e430ca3da7b9bef4c89f8c72ebc703900f7c6b5
      
https://github.com/qemu/qemu/commit/9e430ca3da7b9bef4c89f8c72ebc703900f7c6b5
  Author: John Arbuckle <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/fpu_helper.c

  Log Message:
  -----------
  fpu_helper.c: fix setting FPSCR[FI] bit

The FPSCR[FI] bit indicates if the last floating point instruction had a result 
that was rounded. Each consecutive floating point instruction is suppose to set 
this bit to the correct value. What currently happens is this bit is not set as 
often as it should be. I have verified that this is the behavior of a real 
PowerPC 950. This patch fixes that problem by deciding to set this bit after 
each floating point instruction.

https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-environments-for-32-e3087633.html
Page 63 in table 2-4 is where the description of this bit can be found.

Signed-off-by: John Arbuckle <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3c47beb8defb8cab04ea2e19bc3fd8c65bf9af7d
      
https://github.com/qemu/qemu/commit/3c47beb8defb8cab04ea2e19bc3fd8c65bf9af7d
  Author: David Gibson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M hw/ppc/Makefile.objs

  Log Message:
  -----------
  hw/ppc: Give sam46ex its own config option

At present the Sam460ex board is activated by the general CONFIG_PPC4XX
option.  However that includes the board for both ppc-softmmu and
(deprecated) ppcemb-softmmu builds.  As Sam460ex is developed, that would
require adding more things into ppcemb-softmmu, which we don't want to do.

Signed-off-by: David Gibson <address@hidden>


  Commit: afb6e20429d5853e79e9a8af4a68b51d14b0c0c1
      
https://github.com/qemu/qemu/commit/afb6e20429d5853e79e9a8af4a68b51d14b0c0c1
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/i2c/ppc4xx_i2c.c
    M include/hw/i2c/ppc4xx_i2c.h

  Log Message:
  -----------
  ppc4xx_i2c: Rewrite to model hardware more closely

Rewrite to make it closer to how real device works so that guest OS
drivers can access I2C devices. Previously this was only a hack to
allow U-Boot to get past accessing SPD EEPROMs but to support other
I2C devices and allow guests to access them we need to model real
device more properly.

Signed-off-by: BALATON Zoltan <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c6f2594c4b19db903cd76e89578cf501056b744d
      
https://github.com/qemu/qemu/commit/c6f2594c4b19db903cd76e89578cf501056b744d
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/ppc-softmmu.mak
    M hw/timer/Makefile.objs
    A hw/timer/m41t80.c

  Log Message:
  -----------
  hw/timer: Add basic M41T80 emulation

Basic emulation of the M41T80 serial (I2C) RTC chip. Only getting time
of day is implemented. Setting time and RTC alarm are not supported.

Signed-off-by: BALATON Zoltan <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d2179f70d396cf796151ebf56cc177d7c3e53749
      
https://github.com/qemu/qemu/commit/d2179f70d396cf796151ebf56cc177d7c3e53749
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/sam460ex.c

  Log Message:
  -----------
  sam460ex: Add RTC device

The Sam460ex has an M41T80 serial RTC chip on I2C bus 0 at address 0x68.

Signed-off-by: BALATON Zoltan <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3c409c1927efde2fc7ac5f6cd5d79d0784be3b5d
      
https://github.com/qemu/qemu/commit/3c409c1927efde2fc7ac5f6cd5d79d0784be3b5d
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/ppc440.h
    M hw/ppc/ppc440_uc.c
    M hw/ppc/sam460ex.c

  Log Message:
  -----------
  ppc440_uc: Basic emulation of PPC440 DMA controller

PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
can get further booting on the sam460ex machine.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 71d0f1eac43044ccfaf7c398a93dcdb09bf29e0f
      
https://github.com/qemu/qemu/commit/71d0f1eac43044ccfaf7c398a93dcdb09bf29e0f
  Author: Greg Kurz <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc/kvm: get rid of kvm_get_fallback_smmu_info()

Now that we're checking our MMU configuration is supported by KVM,
rather than adjusting it to KVM, it doesn't really make sense to
have a fallback for kvm_get_smmu_info(). If KVM is too old or buggy
to provide the details, we should rather treat this as an error.

This patch thus adds error reporting to kvm_get_smmu_info() and get
rid of the fallback code. QEMU will now terminate if KVM fails to
provide MMU details. This may break some very old setups, but the
simplification is worth the sacrifice.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ab2569600916864a9db431a7e42f08d5fc72730e
      
https://github.com/qemu/qemu/commit/ab2569600916864a9db431a7e42f08d5fc72730e
  Author: Greg Kurz <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc/kvm: don't pass cpu to kvm_get_smmu_info()

In a future patch the machine code will need to retrieve the MMU
information from KVM during machine initialization before the CPUs
are created.

Actually, KVM_PPC_GET_SMMU_INFO is a VM class ioctl, and thus, we
don't need to have a CPU object around. We just need for KVM to
be initialized and use the kvm_state global. This patch just does
that.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e89372951d328143ecdb3a524bf53454ad9309b0
      
https://github.com/qemu/qemu/commit/e89372951d328143ecdb3a524bf53454ad9309b0
  Author: Greg Kurz <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c

  Log Message:
  -----------
  spapr: compute default value of "hpt-max-page-size" later

It is currently not possible to run a pseries-2.12 or older machine
with HV KVM. QEMU prints the following and exits right away.

qemu-system-ppc64: KVM doesn't support for base page shift 34

The "hpt-max-page-size" capability was recently added to spapr to hide
host configuration details from HPT mode guests. Its default value for
newer machine types is 64k.

For backwards compatibility, pseries-2.12 and older machine types need
a different value. This is handled as usual in a class init function.
The default value is 16G, ie, all page sizes supported by POWER7 and
newer CPUs, but HV KVM requires guest pages to be hpa contiguous as
well as gpa contiguous. The default value is the page size used to
back the guest RAM in this case.

Unfortunately kvmppc_hpt_needs_host_contiguous_pages()->kvm_enabled() is
called way before KVM init and returns false, even if the user requested
KVM. We thus end up selecting 16G, which isn't supported by HV KVM. The
default value must be set during machine init, because we can safely
assume that KVM is initialized at this point.

We fix this by moving the logic to default_caps_with_cpu(). Since the
user cannot pass cap-hpt-max-page-size=0, we set the default to 0 in
the pseries-2.12 class init function and use that as a flag to do the
real work.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2a8ceefca23bc2aaafe711f8afd7585be3c27064
      
https://github.com/qemu/qemu/commit/2a8ceefca23bc2aaafe711f8afd7585be3c27064
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: set is_jmp on ppc_tr_breakpoint_check

The use of GDB breakpoints was broken by b0c2d52 ("target/ppc: convert
to TranslatorOps", 2018-02-16).

Fix it by setting is_jmp, so that we break from the translation loop
as originally intended.

Tested-by: Mark Cave-Ayland <address@hidden>
Reported-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0123d3cbb06600e0624fdbf2255055d9cffe9c28
      
https://github.com/qemu/qemu/commit/0123d3cbb06600e0624fdbf2255055d9cffe9c28
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Relax reserved bitmask of indexed store instructions

The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
instruction exception. In particular, MorphOS has an stwx instruction
with bit 31 set and fails to boot currently because of this. With this
patch it gets further.

Signed-off-by: David Gibson <address@hidden>


  Commit: 29f9cef39eb1ae55e82c6763eb22d7a1bdff7276
      
https://github.com/qemu/qemu/commit/29f9cef39eb1ae55e82c6763eb22d7a1bdff7276
  Author: Sebastian Bauer <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M hw/ppc/spapr.c

  Log Message:
  -----------
  ppc: Include vga cirrus card into the compiling process

Drivers for this card exists on PPC-based AmigaOS guests so it is useful to
allow users to emulate the graphics card for PPC machines.

As cirrus vga is currently preferred over std(vga) in absence of any user
choice, this change also sets the default display of spapr machines to
std as otherwise qemu refuses to start these machines. Not specifying an
explicit graphics mode is for instance done by 'make check'.

Signed-off-by: Sebastian Bauer <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b07cd3e748b3f27a17c27afeee578dc4eedb8dd5
      
https://github.com/qemu/qemu/commit/b07cd3e748b3f27a17c27afeee578dc4eedb8dd5
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M MAINTAINERS
    M default-configs/ppc-softmmu.mak
    M hw/i2c/ppc4xx_i2c.c
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/intc/xics_pnv.c
    M hw/misc/macio/mac_dbdma.c
    M hw/ppc/Makefile.objs
    M hw/ppc/mac_newworld.c
    M hw/ppc/pnv_core.c
    M hw/ppc/ppc440.h
    M hw/ppc/ppc440_uc.c
    M hw/ppc/sam460ex.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/timer/Makefile.objs
    A hw/timer/m41t80.c
    M include/hw/i2c/ppc4xx_i2c.h
    M include/hw/ppc/xics.h
    M linux-user/ppc/cpu_loop.c
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/fpu_helper.c
    M target/ppc/helper.h
    M target/ppc/internal.h
    M target/ppc/kvm.c
    M target/ppc/mem_helper.c
    M target/ppc/translate.c
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180703' into 
staging

ppc patch queue 2018-07-03

Here's a last minue pull request before today's soft freeze.  Ideally
I would have sent this earlier, but I was waiting for a couple of
extra fixes I knew were close.  And the freeze crept up on me, like
always.

Most of the changes here are bugfixes in any case.  There are some
cleanups as well, which have been in my staging tree for a little
while.  There are a couple of truly new features (some extensions to
the sam460ex platform), but these are low risk, since they only affect
a new and not really stabilized machine type anyway.

Higlights are:
  * Mac platform improvements from Mark Cave-Ayland
  * Sam460ex improvements from BALATON Zoltan et al.
  * XICS interrupt handler cleanups from Cédric Le Goater
  * TCG improvements for atomic loads and stores from Richard
    Henderson
  * Assorted other bugfixes

# gpg: Signature made Tue 03 Jul 2018 06:55:22 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-3.0-20180703: (35 commits)
  ppc: Include vga cirrus card into the compiling process
  target/ppc: Relax reserved bitmask of indexed store instructions
  target/ppc: set is_jmp on ppc_tr_breakpoint_check
  spapr: compute default value of "hpt-max-page-size" later
  target/ppc/kvm: don't pass cpu to kvm_get_smmu_info()
  target/ppc/kvm: get rid of kvm_get_fallback_smmu_info()
  ppc440_uc: Basic emulation of PPC440 DMA controller
  sam460ex: Add RTC device
  hw/timer: Add basic M41T80 emulation
  ppc4xx_i2c: Rewrite to model hardware more closely
  hw/ppc: Give sam46ex its own config option
  fpu_helper.c: fix setting FPSCR[FI] bit
  target/ppc: Implement the rest of gen_st_atomic
  target/ppc: Implement the rest of gen_ld_atomic
  target/ppc: Use atomic min/max helpers
  target/ppc: Use MO_ALIGN for EXIWX and ECOWX
  target/ppc: Split out gen_st_atomic
  target/ppc: Split out gen_ld_atomic
  target/ppc: Split out gen_load_locked
  target/ppc: Tidy gen_conditional_store
  ...

Signed-off-by: Peter Maydell <address@hidden>

# Conflicts:
#       hw/ppc/spapr.c


Compare: https://github.com/qemu/qemu/compare/a395717cbd26...b07cd3e748b3
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