[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] be53b6: target/arm: Introduce isar_feature_aa
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] be53b6: target/arm: Introduce isar_feature_aa64_bti |
Date: |
Tue, 05 Feb 2019 11:36:44 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: be53b6f4d7ace2e6a018e45af825069ccb7bab66
https://github.com/qemu/qemu/commit/be53b6f4d7ace2e6a018e45af825069ccb7bab66
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Introduce isar_feature_aa64_bti
Also create field definitions for id_aa64pfr1 from ARMv8.5.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f6e52eaac13b6947f4406c127e3090c898e439c9
https://github.com/qemu/qemu/commit/f6e52eaac13b6947f4406c127e3090c898e439c9
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Add PSTATE.BTYPE
Place this in its own field within ENV, as that will
make it easier to reset from within TCG generated code.
With the change to pstate_read/write, exception entry
and return are automatically handled.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 08f1434a71ddf2bdfdb034dcd24b24464d1efd72
https://github.com/qemu/qemu/commit/08f1434a71ddf2bdfdb034dcd24b24464d1efd72
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Add BT and BTYPE to tb->flags
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d3765835ed02f91f0c6cbb452874209a6af4a730
https://github.com/qemu/qemu/commit/d3765835ed02f91f0c6cbb452874209a6af4a730
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M include/exec/memattrs.h
Log Message:
-----------
exec: Add target-specific tlb bits to MemTxAttrs
These bits can be used to cache target-specific data in cputlb
read from the page tables.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1bafc2ba7e6bfe89fff3503fdac8db39c973de48
https://github.com/qemu/qemu/commit/1bafc2ba7e6bfe89fff3503fdac8db39c973de48
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Cache the GP bit for a page in MemTxAttrs
Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: no need to OR in guarded bit status]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 51bf0d7aa91a9d4e2563240a42e6cb705cef84aa
https://github.com/qemu/qemu/commit/51bf0d7aa91a9d4e2563240a42e6cb705cef84aa
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Default handling of BTYPE during translation
The branch target exception for guarded pages has high priority,
and only 8 instructions are valid for that case. Perform this
check before doing any other decode.
Clear BTYPE after all insns that neither set BTYPE nor exit via
exception (DISAS_NORETURN).
Not yet handled are insns that exit via DISAS_NORETURN for some
other reason, like direct branches.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 358622703583d2e2967e0a93da990e747dcc3ac6
https://github.com/qemu/qemu/commit/358622703583d2e2967e0a93da990e747dcc3ac6
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Reset btype for direct branches
This is all of the non-exception cases of DISAS_NORETURN.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 001d47b6efbe4795ed77366986b8ef384ab8b127
https://github.com/qemu/qemu/commit/001d47b6efbe4795ed77366986b8ef384ab8b127
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Set btype for indirect branches
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a15daafa1cba96ff28abdfb6c860e0939655dbd1
https://github.com/qemu/qemu/commit/a15daafa1cba96ff28abdfb6c860e0939655dbd1
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable BTI for -cpu max
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: bff63fbf97482979267e6bd8aaad32e5f5018e41
https://github.com/qemu/qemu/commit/bff63fbf97482979267e6bd8aaad32e5f5018e41
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M linux-user/aarch64/target_syscall.h
M linux-user/syscall.c
Log Message:
-----------
linux-user: Implement PR_PAC_RESET_KEYS
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 06bf3b153acb93a341a90fb76258d8337cbede9b
https://github.com/qemu/qemu/commit/06bf3b153acb93a341a90fb76258d8337cbede9b
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/pauth-1.c
Log Message:
-----------
tests/tcg/aarch64: Add pauth smoke test
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4a9ee99db38ba513bf1e8f43665b79c60accd017
https://github.com/qemu/qemu/commit/4a9ee99db38ba513bf1e8f43665b79c60accd017
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore
Split out gen_top_byte_ignore in preparation of handling these
data accesses; the new tbflags field is not yet honored.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3a471103ac1823bafc907962dcaf6bd4fc0942a2
https://github.com/qemu/qemu/commit/3a471103ac1823bafc907962dcaf6bd4fc0942a2
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Clean TBI for data operations in the translator
This will allow TBI to be used in user-only mode, as well as
avoid ping-ponging the softmmu TLB when TBI is in use. It
will also enable other armv8 extensions.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c47eaf9fc2af68cfbdbd9ae31f8e2e5ebb7022b4
https://github.com/qemu/qemu/commit/c47eaf9fc2af68cfbdbd9ae31f8e2e5ebb7022b4
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Compute TB_FLAGS for TBI for user-only
Enables, but does not turn on, TBI for CONFIG_USER_ONLY.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: adjusted #ifdeffery to placate clang, which otherwise complains
about static functions that are unused in the CONFIG_USER_ONLY build]
Signed-off-by: Peter Maydell <address@hidden>
Commit: f6a148fef63698826e69ca91cc11877ab1ed786f
https://github.com/qemu/qemu/commit/f6a148fef63698826e69ca91cc11877ab1ed786f
Author: Richard Henderson <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Enable TBI for user-only
This has been enabled in the linux kernel since v3.11
(commit d50240a5f6cea, 2013-09-03,
"arm64: mm: permit use of tagged pointers at EL0").
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 45a4de25835b8c29283d40e47cc2291e7cea2337
https://github.com/qemu/qemu/commit/45a4de25835b8c29283d40e47cc2291e7cea2337
Author: Max Filippov <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M gdbstub.c
Log Message:
-----------
gdbstub: allow killing QEMU via vKill command
With multiprocess extensions gdb uses 'vKill' packet instead of 'k' to
kill the inferior. Handle 'vKill' the same way 'k' was handled in the
presence of single process.
Fixes: 7cf48f6752e5 ("gdbstub: add multiprocess support to
(f|s)ThreadInfo and ThreadExtraInfo")
Cc: Luc Michel <address@hidden>
Signed-off-by: Max Filippov <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Tested-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c3a42358e31a7bd45e6ac12013895d2897169ca5
https://github.com/qemu/qemu/commit/c3a42358e31a7bd45e6ac12013895d2897169ca5
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Fix block comment style in arm_load_kernel()
Fix the block comment style in arm_load_kernel() to QEMU's
current style preferences. This will allow us to do some
refactoring of this function without checkpatch complaining
about the code-motion patches.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Commit: d33774ee446569162a8ab8b4d43606b049207b80
https://github.com/qemu/qemu/commit/d33774ee446569162a8ab8b4d43606b049207b80
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Factor out "direct kernel boot" code into its own function
Factor out the "direct kernel boot" code path from arm_load_kernel()
into its own function; this function is getting long enough that
the code flow is a bit confusing.
This commit only moves code around; no semantic changes.
We leave the "load the dtb" code in arm_load_kernel() -- this
is currently only used by the "direct kernel boot" path, but
this is a bug which we will fix shortly.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Commit: 4c0f268731c17e77403825b4ad550a16d2145d79
https://github.com/qemu/qemu/commit/4c0f268731c17e77403825b4ad550a16d2145d79
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Factor out "set up firmware boot" code
Factor out the "boot via firmware" code path from arm_load_kernel()
into its own function.
This commit only moves code around; no semantic changes.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Commit: 2a5bdfc8d524535e78d81f5932fc62a6b34addc6
https://github.com/qemu/qemu/commit/2a5bdfc8d524535e78d81f5932fc62a6b34addc6
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info
The code path for booting firmware doesn't set env->boot_info. At
first sight this looks odd, so add a comment saying why we don't.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Commit: 5614ca800e05dc07e4045b7738351058538c6079
https://github.com/qemu/qemu/commit/5614ca800e05dc07e4045b7738351058538c6079
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: Support DTB autoload for firmware-only boots
The arm_boot_info struct has a skip_dtb_autoload flag: if this is
set to true by the board code then arm_load_kernel() will not
load the DTB itself, but will leave this for the board code to
do itself later. However, the check for this is done in a
code path which is only executed for the case where we load
a kernel image file. If we're taking the "boot via firmware"
code path then the flag isn't honoured and the DTB is never
loaded.
We didn't notice this because the only real user of "boot
via firmware" that cares about the DTB is the virt board
(for UEFI boot), and that always wants skip_dtb_autoload
anyway. But the SBSA reference board model we're planning to
add will want the flag to behave correctly.
Now we've refactored the arm_load_kernel() function, the
fix is simple: drop the early 'return' so we fall into
the same "load the DTB" code the boot-direct-kernel path uses.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Message-id: address@hidden
Commit: a15945d98d3a3390c3da344d1b47218e91e49d8b
https://github.com/qemu/qemu/commit/a15945d98d3a3390c3da344d1b47218e91e49d8b
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI
The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for
enabling trapped IEEE floating point exceptions (where IEEE exception
conditions cause a CPU exception rather than updating the FPSR status
bits). QEMU doesn't implement this (and nor does the hardware we're
modelling), but for implementations which don't implement trapped
exception handling these control bits are supposed to be RAZ/WI.
This allows guest code to test for whether the feature is present
by trying to write to the bit and checking whether it sticks.
QEMU is incorrectly making these bits read as written. Make them
RAZ/WI as the architecture requires.
In particular this was causing problems for the NetBSD automatic
test suite.
Reported-by: Martin Husemann <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 47994e16b1d66411953623e7c0bf0cdcd50bd507
https://github.com/qemu/qemu/commit/47994e16b1d66411953623e7c0bf0cdcd50bd507
Author: Peter Maydell <address@hidden>
Date: 2019-02-05 (Tue, 05 Feb 2019)
Changed paths:
M gdbstub.c
M hw/arm/boot.c
M include/exec/memattrs.h
M linux-user/aarch64/target_syscall.h
M linux-user/syscall.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
M target/arm/translate.h
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/pauth-1.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190205'
into staging
target-arm queue:
* Implement Armv8.5-BTI extension for system emulation mode
* Implement the PR_PAC_RESET_KEYS prctl() for linux-user mode's Armv8.3-PAuth
support
* Support TBI (top-byte-ignore) properly for linux-user mode
* gdbstub: allow killing QEMU via vKill command
* hw/arm/boot: Support DTB autoload for firmware-only boots
* target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI
# gpg: Signature made Tue 05 Feb 2019 17:04:22 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# gpg: aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190205: (22 commits)
target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI
hw/arm/boot: Support DTB autoload for firmware-only boots
hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info
hw/arm/boot: Factor out "set up firmware boot" code
hw/arm/boot: Factor out "direct kernel boot" code into its own function
hw/arm/boot: Fix block comment style in arm_load_kernel()
gdbstub: allow killing QEMU via vKill command
target/arm: Enable TBI for user-only
target/arm: Compute TB_FLAGS for TBI for user-only
target/arm: Clean TBI for data operations in the translator
target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore
tests/tcg/aarch64: Add pauth smoke test
linux-user: Implement PR_PAC_RESET_KEYS
target/arm: Enable BTI for -cpu max
target/arm: Set btype for indirect branches
target/arm: Reset btype for direct branches
target/arm: Default handling of BTYPE during translation
target/arm: Cache the GP bit for a page in MemTxAttrs
exec: Add target-specific tlb bits to MemTxAttrs
target/arm: Add BT and BTYPE to tb->flags
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/9669c9756205...47994e16b1d6
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] be53b6: target/arm: Introduce isar_feature_aa64_bti,
Peter Maydell <=