[Qemu-commits] [qemu/qemu] 0feb4a: riscv: plic: Fix incorrect irq calculation

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0feb4a7129eb4f120c75849ddc9e50495c50cb63
      
https://github.com/qemu/qemu/commit/0feb4a7129eb4f120c75849ddc9e50495c50cb63
  Author: Alistair Francis <address@hidden>
  Date:   2019-04-04 (Thu, 04 Apr 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  riscv: plic: Fix incorrect irq calculation

This patch fixes four different things, to maintain bisectability they
have been merged into a single patch. The following fixes are below:

sifive_plic: Fix incorrect irq calculation
The irq is incorrectly calculated to be off by one. It has worked in the
past as the priority_base offset has also been set incorrectly. We are
about to fix the priority_base offset so first first the irq
calculation.

sifive_u: Fix PLIC priority base offset and numbering
According to the FU540 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00. The same manual also specifies that the
PLIC only has 53 source priorities. Fix these two incorrect header
files.

We also need to over extend the plic_gpios[] array as the PLIC sources
count from 1 and not 0.

riscv: sifive_e: Fix PLIC priority base offset
According to the FE31 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00.

riscv: virt: Fix PLIC priority base offset
Update the virt offsets based on the newly updated SiFive U and SiFive E
offsets.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 79bcac250f96ba1d4fdecfdc6e3363c9024703a4
      
https://github.com/qemu/qemu/commit/79bcac250f96ba1d4fdecfdc6e3363c9024703a4
  Author: Alistair Francis <address@hidden>
  Date:   2019-04-04 (Thu, 04 Apr 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c

  Log Message:
  -----------
  riscv: plic: Log guest errors

Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 10546e09e174e0bb185b66a4c397aa845efcd36e
      
https://github.com/qemu/qemu/commit/10546e09e174e0bb185b66a4c397aa845efcd36e
  Author: Peter Maydell <address@hidden>
  Date:   2019-04-05 (Fri, 05 Apr 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/palmer/tags/riscv-for-master-4.0-rc3-v2' into staging

RISC-V Patches for 4.0-rc3, v2

This patch set contains a pair of tightly coupled PLIC bug fixes:

* We were calculating the PLIC addresses incorrectly.
* We were installing the wrong number of PLIC interrupts.

The two bugs togther resulted in a mostly-working system, but they're
impossible to seperate because fixing one bug would result in
significant breakage.  As a result they're in the same patch.

There is also a cleanup to use qemu_log_mask(LOG_GUEST_ERROR,...) for
error reporting.

As far as I know these are the last outstanding RISC-V patches for 4.0.

v2 no longer fails "make check" for me... sorry!

# gpg: Signature made Fri 05 Apr 2019 01:33:57 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-rc3-v2:
  riscv: plic: Log guest errors
  riscv: plic: Fix incorrect irq calculation

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/bc939abe00cd...10546e09e174