[Qemu-commits] [qemu/qemu] 8d031c: i386: Add new Hygon 'Dhyana' CPU model

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8d031cec366f26669807eb43f61eb335973b7053
      
https://github.com/qemu/qemu/commit/8d031cec366f26669807eb43f61eb335973b7053
  Author: Pu Wen <address@hidden>
  Date:   2019-04-25 (Thu, 25 Apr 2019)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add new Hygon 'Dhyana' CPU model

Add a new base CPU model called 'Dhyana' to model processors from Hygon
Dhyana(family 18h), which derived from AMD EPYC(family 17h).

The following features bits have been removed compare to AMD EPYC:
aes, pclmulqdq, sha_ni

The Hygon Dhyana support to KVM in Linux is already accepted upstream[1].
So add Hygon Dhyana support to Qemu is necessary to create Hygon's own
CPU model.

Reference:
[1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87

Signed-off-by: Pu Wen <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Daniel P. Berrangé <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 965242dbf47192a96472290302a66a4bd620f368
      
https://github.com/qemu/qemu/commit/965242dbf47192a96472290302a66a4bd620f368
  Author: Ernest Esene <address@hidden>
  Date:   2019-04-25 (Thu, 25 Apr 2019)

  Changed paths:
    M hw/i386/pc_piix.c

  Log Message:
  -----------
  Categorize devices: IGD passthrough ISA bridge

Set category for the device.

Signed-off-by: Ernest Esene <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
[ehabkost: edited commit message]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 1ec202c9bed532ea629af9ce95485dd36a183250
      
https://github.com/qemu/qemu/commit/1ec202c9bed532ea629af9ce95485dd36a183250
  Author: Ernest Esene <address@hidden>
  Date:   2019-04-25 (Thu, 25 Apr 2019)

  Changed paths:
    M hw/i386/amd_iommu.c
    M hw/i386/intel_iommu.c

  Log Message:
  -----------
  Categorize devices: iommu

Set category and description for iommu devices.

Signed-off-by: Ernest Esene <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
[ehabkost: edited commit message]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: a4e0b436f44a4bb47ed4a75b0c05d2547cf12b1c
      
https://github.com/qemu/qemu/commit/a4e0b436f44a4bb47ed4a75b0c05d2547cf12b1c
  Author: Stanislav Lanci <address@hidden>
  Date:   2019-04-25 (Thu, 25 Apr 2019)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  Pass through cache information for TOPOEXT CPUs

Signed-off-by: Stanislav Lanci <address@hidden>
Message-Id: <address@hidden>
[ehabkost: removed redundant comment line]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: db7f1c3fafa8e1d23ecb212454f9d83ac59e411b
      
https://github.com/qemu/qemu/commit/db7f1c3fafa8e1d23ecb212454f9d83ac59e411b
  Author: Peter Maydell <address@hidden>
  Date:   2019-04-26 (Fri, 26 Apr 2019)

  Changed paths:
    M hw/i386/amd_iommu.c
    M hw/i386/intel_iommu.c
    M hw/i386/pc_piix.c
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2019-04-25

* Hygon Dhyana CPU model (Pu Wen)
* Categorize a few devices in hw/i386 (Ernest Esene)
* Support host-cache-info on TOPOEXT CPUID leaf (Stanislav Lanci)

# gpg: Signature made Thu 25 Apr 2019 19:12:25 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  Pass through cache information for TOPOEXT CPUs
  Categorize devices: iommu
  Categorize devices: IGD passthrough ISA bridge
  i386: Add new Hygon 'Dhyana' CPU model

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/06e643395550...db7f1c3fafa8