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[Qemu-commits] [qemu/qemu] c10aaa: tests: Fix up docker cross builds for
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c10aaa: tests: Fix up docker cross builds for ppc64 (BE) t... |
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Date: |
Thu, 30 May 2019 08:32:35 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c10aaaab0fcfaf7ad68ccbc07a9069d7f6310532
https://github.com/qemu/qemu/commit/c10aaaab0fcfaf7ad68ccbc07a9069d7f6310532
Author: David Gibson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M tests/docker/Makefile.include
A tests/docker/dockerfiles/debian-ppc64-cross.docker
M tests/tcg/ppc/Makefile.include
Log Message:
-----------
tests: Fix up docker cross builds for ppc64 (BE) targets
We currently have docker cross building targets for powerpc (32-bit, BE)
and ppc64el (64-bit, LE), but not for pcp64 (64-bit, BE). This is an
irritating gap in make check-tcg coverage so correct it.
Signed-off-by: David Gibson <address@hidden>
Commit: f8378accda78acdc601f228254e2a41b4531621b
https://github.com/qemu/qemu/commit/f8378accda78acdc601f228254e2a41b4531621b
Author: Richard Henderson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M configure
Log Message:
-----------
configure: Distinguish ppc64 and ppc64le hosts
We cannot use the ppc64le host compiler to build ppc64(be) guest code.
Clean up confusion between cross_cc_powerpc and cross_cc_ppc; make use
of the cflags variable as well.
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
[dwg: Dropped hunk relating to ppc64abi32, it doesn't test properly]
Signed-off-by: David Gibson <address@hidden>
Commit: 3ff1075ab614d488c3cc3730a6d0d3c08f1965c4
https://github.com/qemu/qemu/commit/3ff1075ab614d488c3cc3730a6d0d3c08f1965c4
Author: Richard Henderson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M configure
Log Message:
-----------
configure: Use quotes around uses of $CPU_CFLAGS
About half of the values to which CPU_CFLAGS is set
have multiple space separated arguments.
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 228152c27e7085fec1cc8c86259a5e21ee5c7f89
https://github.com/qemu/qemu/commit/228152c27e7085fec1cc8c86259a5e21ee5c7f89
Author: Boxuan Li <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/kvm.c
M target/ppc/trace-events
Log Message:
-----------
target/ppc/kvm: Fix trace typo
Signed-off-by: Boxuan Li <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c50be9e1ec705512c622366f80861436eafacffa
https://github.com/qemu/qemu/commit/c50be9e1ec705512c622366f80861436eafacffa
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
hw/ppc/prep: use TYPE_MC146818_RTC instead of a hardcoded string
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2e8f85189d477e1009e13235ef73c86834664571
https://github.com/qemu/qemu/commit/2e8f85189d477e1009e13235ef73c86834664571
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/isa/i82378.c
M hw/ppc/prep.c
Log Message:
-----------
hw/ppc/40p: Move the MC146818 RTC to the board where it belongs
The MC146818 RTC was incorrectly added to the i82378 chipset in
commit a04ff940974a. In the next commit (506b7ddf8893) the PReP
machine use the i82378.
Since the MC146818 is specific to the PReP machine, move its use
there.
Fixes: a04ff940974a
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1dbe3d196d81da45df9f17d6959871c08bdb9dac
https://github.com/qemu/qemu/commit/1dbe3d196d81da45df9f17d6959871c08bdb9dac
Author: Artyom Tarasenko <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
hw/ppc/40p: use 1900 as a base year
AIX 5.1 expects the base year to be 1900. Adjust accordingly.
Signed-off-by: Artyom Tarasenko <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 83f192d34d2525f9c0053c2179bdbc69327b9158
https://github.com/qemu/qemu/commit/83f192d34d2525f9c0053c2179bdbc69327b9158
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
target/ppc: Add ibm,purr and ibm,spurr device-tree properties
The ibm,purr and ibm,spurr device tree properties are used to indicate
that the processor implements the Processor Utilisation of Resources
Register (PURR) and Scaled Processor Utilisation of Resources Registers
(SPURR), respectively. Each property has a single value which represents
the level of architecture supported. A value of 1 for ibm,purr means
support for the version of the PURR defined in book 3 in version 2.02 of
the architecture. A value of 1 for ibm,spurr means support for the
version of the SPURR defined in version 2.05 of the architecture.
Add these properties for all processors for which the PURR and SPURR
registers are generated.
Fixes: 0da6f3fef9a "spapr: Reorganize CPU dt generation code"
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cf4e9363f7fd889d8d804c8f78e8927782c2aa48
https://github.com/qemu/qemu/commit/cf4e9363f7fd889d8d804c8f78e8927782c2aa48
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Fix xvxsigdp
Fix a typo in xvxsigdp where we put both results into the lower
doubleword.
Fixes: dd977e4f45cb ("target/ppc: Optimize x[sv]xsigdp using deposit_i64()")
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d47a751adab7833e9831408376077bc8dba41d5d
https://github.com/qemu/qemu/commit/d47a751adab7833e9831408376077bc8dba41d5d
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Fix xxbrq, xxbrw
Fix a typo in xxbrq and xxbrw where we put both results into the lower
doubleword.
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 63be02fc69d44442dc7eb316d44f1c1fbe49c075
https://github.com/qemu/qemu/commit/63be02fc69d44442dc7eb316d44f1c1fbe49c075
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: Fix vslv and vsrv
vslv and vsrv are broken on little endian, we append 00 to the
high byte not the low byte. Fix it by using the VsrB() accessor.
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7fa0ddc1d63806769d1b6246a62708d3bde39037
https://github.com/qemu/qemu/commit/7fa0ddc1d63806769d1b6246a62708d3bde39037
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: Fix vsum2sws
A recent cleanup changed the pre zeroing of the result from 64 bit
to 32 bit operations:
- result.u64[i] = 0;
+ result.VsrW(i) = 0;
This corrupts the result.
Fixes: 60594fea298d ("target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in
int_helper.c")
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4c406ca7345e874f16110734907af970c968d727
https://github.com/qemu/qemu/commit/4c406ca7345e874f16110734907af970c968d727
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Fix xxspltib
xxspltib raises a VMX or a VSX exception depending on the register
set it is operating on. We had a check, but it was backwards.
Fixes: f113283525a4 ("target-ppc: add xxspltib instruction")
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7f9136f90dd2675c4cee29eed447f9213f94f3e6
https://github.com/qemu/qemu/commit/7f9136f90dd2675c4cee29eed447f9213f94f3e6
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
spapr/xive: EQ page should be naturally aligned
When the OS configures the EQ page in which to receive event
notifications from the XIVE interrupt controller, the page should be
naturally aligned. Add this check.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
[dwg: Minor change for printf warning on some platforms]
Signed-off-by: David Gibson <address@hidden>
Commit: 13df93244efbd4bb8b4cf4e26104a26033178674
https://github.com/qemu/qemu/commit/13df93244efbd4bb8b4cf4e26104a26033178674
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
spapr/xive: fix EQ page addresses above 64GB
The high order bits of the address of the OS event queue is stored in
bits [4-31] of word2 of the XIVE END internal structures and the low
order bits in word3. This structure is using Big Endian ordering and
computing the value requires some simple arithmetic which happens to
be wrong. The mask removing bits [0-3] of word2 is applied to the
wrong value and the resulting address is bogus when above 64GB.
Guests with more than 64GB of RAM will allocate pages for the OS event
queues which will reside above the 64GB limit. In this case, the XIVE
device model will wake up the CPUs in case of a notification, such as
IPIs, but the update of the event queue will be written at the wrong
place in memory. The result is uncertain as the guest memory is
trashed and IPI are not delivered.
Introduce a helper xive_end_qaddr() to compute this value correctly in
all places where it is used.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fb2e8b5132fa592753e330b2675093e907265cdc
https://github.com/qemu/qemu/commit/fb2e8b5132fa592753e330b2675093e907265cdc
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
spapr/xive: print out the EQ page address in the monitor
This proved to be a useful information when debugging issues with OS
event queues allocated above 64GB.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f81d69fcea571af19de01377d2b474a675f573d6
https://github.com/qemu/qemu/commit/f81d69fcea571af19de01377d2b474a675f573d6
Author: Satheesh Rajendran <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
Fix typo on "info pic" monitor cmd output for xive
Instead of LISN i.e "Logical Interrupt Source Number" as per
Xive PAPR document "info pic" prints as LSIN, let's fix it.
Signed-off-by: Satheesh Rajendran <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Stefano Garzarella <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e04c5dd139a319a97d50e29c0a84b5c630e6e740
https://github.com/qemu/qemu/commit/e04c5dd139a319a97d50e29c0a84b5c630e6e740
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STORE
A few small optimisations:
In VSX_LOAD_SCALAR_DS() we can don't need to read the VSR via
get_cpu_vsrh().
Split VSX_VECTOR_LOAD_STORE() into two functions. Loads only need to
write the VSRs (set_cpu_vsr*()) and stores only need to read the VSRs
(get_cpu_vsr*())
Thanks to Mark Cave-Ayland for the suggestions.
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 77bd8937c03dd55e57cc257951ad07c185303c3e
https://github.com/qemu/qemu/commit/77bd8937c03dd55e57cc257951ad07c185303c3e
Author: Anton Blanchard <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]p
We were using set_cpu_vsr*() when we should have used get_cpu_vsr*().
Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
helpers for VSR register access")
Signed-off-by: Anton Blanchard <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e7f78db9fbb18900c724fd8ebfc46b6962203b98
https://github.com/qemu/qemu/commit/e7f78db9fbb18900c724fd8ebfc46b6962203b98
Author: Greg Kurz <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr/xive: Sanity checks of OV5 during CAS
If a machine is started with ic-mode=xive but the guest only knows
about XICS, eg. an RHEL 7.6 guest, the kernel panics. This is
expected but a bit unfortunate since the crash doesn't provide
much information for the end user to guess what's happening.
Detect that during CAS and exit QEMU with a proper error message
instead, like it is already done for the MMU.
Even if this is less likely to happen, the opposite case of a guest
that only knows about XIVE would certainly fail all the same if the
machine is started with ic-mode=xics.
Also, the only valid values a guest can pass in byte 23 of OV5 during
CAS are 0b00 (XIVE legacy mode) and 0b01 (XIVE exploitation mode). Any
other value is a bug, at least with the current spec. Again, it does
not seem right to let the guest go on without a precise idea of the
interrupt mode it asked for.
Handle these cases as well.
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 70de096748dc0243b9c6aec5458b3ff270fe13e6
https://github.com/qemu/qemu/commit/70de096748dc0243b9c6aec5458b3ff270fe13e6
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_rtas.c
Log Message:
-----------
target/ppc: Set PSSCR_EC on cpu halt to prevent spurious wakeup
The processor stop status and control register (PSSCR) is used to
control the power saving facilities of the thread. The exit criterion
bit (EC) is used to specify whether the thread should be woken by any
interrupt (EC == 0) or only an interrupt enabled in the LPCR to wake the
thread (EC == 1).
The rtas facilities start-cpu and self-stop are used to transition a
vcpu between the stopped and running states. When a vcpu is stopped it
may only be started again by the start-cpu rtas call.
Currently a vcpu in the stopped state will start again whenever an
interrupt comes along due to PSSCR_EC being cleared, and while this is
architecturally correct for a hardware thread, a vcpu is expected to
only be woken by calling start-cpu. This means when performing a reboot
on a tcg machine that the secondary threads will restart while the
primary is still in slof, this is unsupported and causes call traces
like:
SLOF **********************************************************************
QEMU Starting
Build Date = Jan 14 2019 18:00:39
FW Version = git-a5b428e1c1eae703
Press "s" to enter Open Firmware.
qemu: fatal: Trying to deliver HV exception (MSR) 70 with no HV support
NIP 6d61676963313230 LR 000000003dbe0308 CTR 6d61676963313233 XER
0000000000000000 CPU#1
MSR 0000000000000000 HID0 0000000000000000 HF 0000000000000000 iidx 3 didx 3
TB 00000026 115746031956 DECR 18446744073326238463
GPR00 000000003dbe0308 000000003e669fe0 000000003dc10700 0000000000000003
GPR04 000000003dc62198 000000003dc62178 000000003dc0ea48 0000000000000030
GPR08 000000003dc621a8 0000000000000018 000000003e466008 000000003dc50700
GPR12 c00000000093a4e0 c00000003ffff300 c00000003e533f90 0000000000000000
GPR16 0000000000000000 0000000000000000 000000003e466010 000000003dc0b040
GPR20 0000000000008000 000000000000f003 0000000000000006 000000003e66a050
GPR24 000000003dc06400 000000003dc0ae70 0000000000000003 000000000000f001
GPR28 000000003e66a060 ffffffffffffffff 6d61676963313233 0000000000000028
CR 28000222 [ E L - - - E E E ] RES ffffffffffffffff
FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 00000000311825e0
FPR12 00000000311825e0 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR 0000000000000000
SRR0 000000003dbe06b0 SRR1 0000000000080000 PVR 00000000004e1200 VRSAVE
0000000000000000
SPRG0 000000003dbe0308 SPRG1 000000003e669fe0 SPRG2 00000000000000d8 SPRG3
000000003dbe0308
SPRG4 0000000000000000 SPRG5 0000000000000000 SPRG6 0000000000000000 SPRG7
0000000000000000
HSRR0 6d61676963313230 HSRR1 0000000000000000
CFAR 000000003dbe3e64
LPCR 0000000004020008
PTCR 0000000000000000 DAR 0000000000000000 DSISR 0000000000000000
Aborted (core dumped)
To fix this, set the PSSCR_EC bit when a vcpu is stopped to disable it
from coming back online until the start-cpu rtas call is made.
Fixes: 21c0d66a9c99 ("target/ppc: Fix support for "STOP light" states on
POWER9")
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 64d4a53431733fe9d50e94a5a33b15d151f7f8e9
https://github.com/qemu/qemu/commit/64d4a53431733fe9d50e94a5a33b15d151f7f8e9
Author: David Gibson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Add forgotten capability to migration stream
spapr machine capabilities are supposed to be sent in the migration stream
so that we can sanity check the source and destination have compatible
configuration. Unfortunately, when we added the hpt-max-page-size
capability, we forgot to add it to the migration state. This means that we
can generate spurious warnings when both ends are configured for large
pages, or potentially fail to warn if the source is configured for huge
pages, but the destination is not.
Fixes: 2309832afda "spapr: Maximum (HPT) pagesize property"
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Commit: 571fbe6ccd7a159789e5d473e2837d45764197ec
https://github.com/qemu/qemu/commit/571fbe6ccd7a159789e5d473e2837d45764197ec
Author: Richard Henderson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Use vector variable shifts for VSL, VSR, VSRA
The gvec expanders take care of masking the shift amount
against the element width.
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: eb3cba827294e2c128cd484f423da648fada8f68
https://github.com/qemu/qemu/commit/eb3cba827294e2c128cd484f423da648fada8f68
Author: David Gibson <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Fix phb_placement backwards compatibility
When we added support for NVLink2 passthrough devices, we changed the
phb_placement hook to handle the placement of NVLink2 bridges' specific
resources. For compatibility we use a version that doesn't do this
allocation for old machine types.
However, because of the delay between when the patch was posted and when
it was merged, we ended up with that compatibility hook applying for
machine versions 3.1 and earlier whereas it should apply for 4.0 and
earlier (since the patch was applied early in the 4.1 tree).
Fixes: ec132efaa81 "spapr: Support NVIDIA V100 GPU with NVLink2"
Reported-by: Laurent Vivier <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Commit: 75de59416df857b429f1aac028855090c69f2ea9
https://github.com/qemu/qemu/commit/75de59416df857b429f1aac028855090c69f2ea9
Author: Greg Kurz <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Print out extra hints when CAS negotiation of interrupt mode fails
Let's suggest to the user how the machine should be configured to allow
the guest to boot successfully.
Suggested-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Satheesh Rajendran <address@hidden>
Tested-by: Satheesh Rajendran <address@hidden>
[dwg: Adjusted for style error]
Signed-off-by: David Gibson <address@hidden>
Commit: 38afd772f802ff787ea16af73b0c0d24a8c46b6c
https://github.com/qemu/qemu/commit/38afd772f802ff787ea16af73b0c0d24a8c46b6c
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/Makefile.objs
M hw/intc/spapr_xive.c
A hw/intc/spapr_xive_kvm.c
M hw/intc/xive.c
M hw/ppc/Kconfig
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xive.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
spapr/xive: add KVM support
This introduces a set of helpers when KVM is in use, which create the
KVM XIVE device, initialize the interrupt sources at a KVM level and
connect the interrupt presenters to the vCPU.
They also handle the initialization of the TIMA and the source ESB
memory regions of the controller. These have a different type under
KVM. They are 'ram device' memory mappings, similarly to VFIO, exposed
to the guest and the associated VMAs on the host are populated
dynamically with the appropriate pages using a fault handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0c575703e487b6e36d226b67e0c8d08c004ce998
https://github.com/qemu/qemu/commit/0c575703e487b6e36d226b67e0c8d08c004ce998
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr/xive: add hcall support when under KVM
XIVE hcalls are all redirected to QEMU as none are on a fast path.
When necessary, QEMU invokes KVM through specific ioctls to perform
host operations. QEMU should have done the necessary checks before
calling KVM and, in case of failure, H_HARDWARE is simply returned.
H_INT_ESB is a special case that could have been handled under KVM
but the impact on performance was low when under QEMU. Here are some
figures :
kernel irqchip OFF ON
H_INT_ESB KVM QEMU
rtl8139 (LSI ) 1.19 1.24 1.23 Gbits/sec
virtio 31.80 42.30 -- Gbits/sec
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7bfc759c02b8d19fd76d70d138deea0025f6f461
https://github.com/qemu/qemu/commit/7bfc759c02b8d19fd76d70d138deea0025f6f461
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xive.c
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xive.h
Log Message:
-----------
spapr/xive: add state synchronization with KVM
This extends the KVM XIVE device backend with 'synchronize_state'
methods used to retrieve the state from KVM. The HW state of the
sources, the KVM device and the thread interrupt contexts are
collected for the monitor usage and also migration.
These get operations rely on their KVM counterpart in the host kernel
which acts as a proxy for OPAL, the host firmware. The set operations
will be added for migration support later.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9b88cd7673dddf9336f50540e5735eb6f190200a
https://github.com/qemu/qemu/commit/9b88cd7673dddf9336f50540e5735eb6f190200a
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr/xive: introduce a VM state change handler
This handler is in charge of stabilizing the flow of event notifications
in the XIVE controller before migrating a guest. This is a requirement
before transferring the guest EQ pages to a destination.
When the VM is stopped, the handler sets the source PQs to PENDING to
stop the flow of events and to possibly catch a triggered interrupt
occuring while the VM is stopped. Their previous state is saved. The
XIVE controller is then synced through KVM to flush any in-flight
event notification and to stabilize the EQs. At this stage, the EQ
pages are marked dirty to make sure the EQ pages are transferred if a
migration sequence is in progress.
The previous configuration of the sources is restored when the VM
resumes, after a migration or a stop. If an interrupt was queued while
the VM was stopped, the handler simply generates the missing trigger.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 277dd3d7712ae056d2614ea164f6560afd5d71d4
https://github.com/qemu/qemu/commit/277dd3d7712ae056d2614ea164f6560afd5d71d4
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
M hw/intc/xive.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xive.h
Log Message:
-----------
spapr/xive: add migration support for KVM
When the VM is stopped, the VM state handler stabilizes the XIVE IC
and marks the EQ pages dirty. These are then transferred to destination
before the transfer of the device vmstates starts.
The SpaprXive interrupt controller model captures the XIVE internal
tables, EAT and ENDT and the XiveTCTX model does the same for the
thread interrupt context registers.
At restart, the SpaprXive 'post_load' method restores all the XIVE
states. It is called by the sPAPR machine 'post_load' method, when all
XIVE states have been transferred and loaded.
Finally, the source states are restored in the VM change state handler
when the machine reaches the running state.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0dc9f5f8496a23da375a3b19556e265ba22478e0
https://github.com/qemu/qemu/commit/0dc9f5f8496a23da375a3b19556e265ba22478e0
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr_irq.c
Log Message:
-----------
spapr/xive: activate KVM support
All is in place for KVM now. State synchronization and migration will
come next.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 90c20e1e2ce0fb52975ff4d6590620ef0129790e
https://github.com/qemu/qemu/commit/90c20e1e2ce0fb52975ff4d6590620ef0129790e
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/core/sysbus.c
M include/hw/sysbus.h
Log Message:
-----------
sysbus: add a sysbus_mmio_unmap() helper
This will be used to remove the MMIO regions of the POWER9 XIVE
interrupt controller when the sPAPR machine is reseted.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 56b11587dfc79dc6453d857159801dcc38f24d0c
https://github.com/qemu/qemu/commit/56b11587dfc79dc6453d857159801dcc38f24d0c
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics_kvm.c
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
Log Message:
-----------
spapr: introduce routines to delete the KVM IRQ device
If a new interrupt mode is chosen by CAS, the machine generates a
reset to reconfigure. At this point, the connection with the previous
KVM device needs to be closed and a new connection needs to opened
with the KVM device operating the chosen interrupt mode.
New routines are introduced to destroy the XICS and the XIVE KVM
devices. They make use of a new KVM device ioctl which destroys the
device and also disconnects the IRQ presenters from the vCPUs.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3bf84e99c823987704d1324cf0e34e7597e737a5
https://github.com/qemu/qemu/commit/3bf84e99c823987704d1324cf0e34e7597e737a5
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics_kvm.c
Log Message:
-----------
spapr: check for the activation of the KVM IRQ device
The activation of the KVM IRQ device depends on the interrupt mode
chosen at CAS time by the machine and some methods used at reset or by
the migration need to be protected.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ae805ea9073bb97363d867ef081be27e2c63d782
https://github.com/qemu/qemu/commit/ae805ea9073bb97363d867ef081be27e2c63d782
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
Log Message:
-----------
spapr/irq: introduce a spapr_irq_init_device() helper
The way the XICS and the XIVE devices are initialized follows the same
pattern. First, try to connect to the KVM device and if not possible
fallback on the emulated device, unless a kernel_irqchip is required.
The spapr_irq_init_device() routine implements this sequence in
generic way using new sPAPR IRQ handlers ->init_emu() and ->init_kvm().
The XIVE init sequence is moved under the associated sPAPR IRQ
->init() handler. This will change again when KVM support is added for
the dual interrupt mode.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cf435df697e50db5ed1ec60e5efe639123a03154
https://github.com/qemu/qemu/commit/cf435df697e50db5ed1ec60e5efe639123a03154
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/xics_spapr.c
M include/hw/ppc/xics.h
Log Message:
-----------
spapr/irq: initialize the IRQ device only once
Add a check to make sure that the routine initializing the emulated
IRQ device is called once. We don't have much to test on the XICS
side, so we introduce a 'init' boolean under ICSState.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 83629419a52f393d67317b14a861d3062e37c5c3
https://github.com/qemu/qemu/commit/83629419a52f393d67317b14a861d3062e37c5c3
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
ppc/xics: fix irq priority in ics_set_irq_type()
Recent commits changed the behavior of ics_set_irq_type() to
initialize correctly LSIs at the KVM level. ics_set_irq_type() is also
called by the realize routine of the different devices of the machine
when initial interrupts are claimed, before the ICSState device is
reseted.
In the case, the ICSIRQState priority is 0x0 and the call to
ics_set_irq_type() results in configuring the target of the
interrupt. On P9, when using the KVM XICS-on-XIVE device, the target
is configured to be server 0, priority 0 and the event queue 0 is
created automatically by KVM.
With the dual interrupt mode creating the KVM device at reset, it
leads to unexpected effects on the guest, mostly blocking IPIs. This
is wrong, fix it by reseting the ICSIRQState structure when
ics_set_irq_type() is called.
Fixes: commit 6cead90c5c9c ("xics: Write source state to KVM at claim time")
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3f777abc7107a27a2c19ee0eb823054fc9ecc902
https://github.com/qemu/qemu/commit/3f777abc7107a27a2c19ee0eb823054fc9ecc902
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive_kvm.c
M hw/intc/xics_kvm.c
M hw/intc/xive.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/xive.h
Log Message:
-----------
spapr/irq: add KVM support to the 'dual' machine
The interrupt mode is chosen by the CAS negotiation process and
activated after a reset to take into account the required changes in
the machine. This brings new constraints on how the associated KVM IRQ
device is initialized.
Currently, each model takes care of the initialization of the KVM
device in their realize method but this is not possible anymore as the
initialization needs to be done globaly when the interrupt mode is
known, i.e. when machine is reseted. It also means that we need a way
to delete a KVM device when another mode is chosen.
Also, to support migration, the QEMU objects holding the state to
transfer should always be available but not necessarily activated.
The overall approach of this proposal is to initialize both interrupt
mode at the QEMU level to keep the IRQ number space in sync and to
allow switching from one mode to another. For the KVM side of things,
the whole initialization of the KVM device, sources and presenters, is
grouped in a single routine. The XICS and XIVE sPAPR IRQ reset
handlers are modified accordingly to handle the init and the delete
sequences of the KVM device.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 24563a587f964ff16477feab54686ccf617d3570
https://github.com/qemu/qemu/commit/24563a587f964ff16477feab54686ccf617d3570
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M MAINTAINERS
M docs/index.rst
A docs/specs/index.rst
A docs/specs/ppc-spapr-xive.rst
A docs/specs/ppc-xive.rst
Log Message:
-----------
docs: provide documentation on the POWER9 XIVE interrupt controller
This documents the overall XIVE architecture and the XIVE support for
sPAPR guest machines (pseries).
It also provides documentation on the 'info pic' command.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Satheesh Rajendran <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cdd71c8e9dffc97c5e0569b6ea14dfb65fc74851
https://github.com/qemu/qemu/commit/cdd71c8e9dffc97c5e0569b6ea14dfb65fc74851
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/intc/spapr_xive.c
M hw/intc/spapr_xive_kvm.c
Log Message:
-----------
spapr/xive: fix multiple resets when using the 'dual' interrupt mode
Today, when a reset occurs on a pseries machine using the 'dual'
interrupt mode, the KVM devices are released and recreated depending
on the interrupt mode selected by CAS. If XIVE is selected, the SysBus
memory regions of the SpaprXive model are initialized by the KVM
backend initialization routine each time a reset occurs. This leads to
a crash after a couple of resets because the machine reaches the
QDEV_MAX_MMIO limit of SysBusDevice :
qemu-system-ppc64: hw/core/sysbus.c:193: sysbus_init_mmio: Assertion
`dev->num_mmio < QDEV_MAX_MMIO' failed.
To fix, initialize the SysBus memory regions in spapr_xive_realize()
called only once and remove the same inits from the QEMU and KVM
backend initialization routines which are called at each reset.
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bd94bc06479ad3be5e2d5db70fde9e8098b77d21
https://github.com/qemu/qemu/commit/bd94bc06479ad3be5e2d5db70fde9e8098b77d21
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: change default interrupt mode to 'dual'
Now that XIVE support is complete (QEMU emulated and KVM devices),
change the pseries machine to advertise both interrupt modes: XICS
(P7/P8) and XIVE (P9).
The machine default interrupt modes depends on the version. Current
settings are:
pseries default interrupt mode
4.1 dual
4.0 xics
3.1 xics
3.0 legacy xics (different IRQ number space layout)
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3725ef1a944bbe1173b55fdabe76fb17876f1d9e
https://github.com/qemu/qemu/commit/3725ef1a944bbe1173b55fdabe76fb17876f1d9e
Author: Greg Kurz <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Don't migrate the hpt_maxpagesize cap to older machine types
Commit 0b8c89be7f7b added the hpt_maxpagesize capability to the migration
stream. This is okay for new machine types but it breaks backward migration
to older QEMUs, which don't expect the extra subsection.
Add a compatibility boolean flag to the sPAPR machine class and use it to
skip migration of the capability for machine types 4.0 and older. This
fixes migration to an older QEMU. Note that the destination will emit a
warning:
qemu-system-ppc64: warning: cap-hpt-max-page-size lower level (16) in incoming
stream than on destination (24)
This is expected and harmless though. It is okay to migrate from a lower
HPT maximum page size (64k) to a greater one (16M).
Fixes: 0b8c89be7f7b "spapr: Add forgotten capability to migration stream"
Based-on: <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 83b90bf026767df5faefe3daca9f1649a5591418
https://github.com/qemu/qemu/commit/83b90bf026767df5faefe3daca9f1649a5591418
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: introduce new skiboot platform properties
Newer skiboots (after 6.3) support QEMU platforms that have
characteristics closer to real OpenPOWER systems. The CPU type is used
to define the BMC drivers: Aspeed AST2400 for POWER8 processors and
AST2500 for POWER9s.
Advertise the new platform property names, "qemu,powernv8" and
"qemu,powernv9", using the CPU type chosen for the QEMU PowerNV
machine. Also, advertise the original platform name "qemu,powernv" in
case of POWER8 processors for compatibility with older skiboots.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ce4b1b56852ea741170ae85d3b8c0771c1ca7c9e
https://github.com/qemu/qemu/commit/ce4b1b56852ea741170ae85d3b8c0771c1ca7c9e
Author: Cédric Le Goater <address@hidden>
Date: 2019-05-29 (Wed, 29 May 2019)
Changed paths:
M hw/ppc/pnv_xscom.c
Log Message:
-----------
ppc/pnv: add dummy XSCOM registers for PRD initialization
PRD (Processor recovery diagnostics) is a service available on
OpenPower systems. The opal-prd daemon initializes the PowerPC
Processor through the XSCOM bus and then waits for hardware diagnostic
events.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 60905286cb5150de854e08279bca7dfc4b549e91
https://github.com/qemu/qemu/commit/60905286cb5150de854e08279bca7dfc4b549e91
Author: Peter Maydell <address@hidden>
Date: 2019-05-30 (Thu, 30 May 2019)
Changed paths:
M MAINTAINERS
M configure
M docs/index.rst
A docs/specs/index.rst
A docs/specs/ppc-spapr-xive.rst
A docs/specs/ppc-xive.rst
M hw/core/sysbus.c
M hw/intc/Makefile.objs
M hw/intc/spapr_xive.c
A hw/intc/spapr_xive_kvm.c
M hw/intc/xics.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/isa/i82378.c
M hw/ppc/Kconfig
M hw/ppc/pnv.c
M hw/ppc/pnv_xscom.c
M hw/ppc/prep.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics.h
M include/hw/ppc/xics_spapr.h
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
M include/hw/sysbus.h
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/trace-events
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vsx-impl.inc.c
M tests/docker/Makefile.include
A tests/docker/dockerfiles/debian-ppc64-cross.docker
M tests/tcg/ppc/Makefile.include
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.1-20190529' into
staging
ppc patch queue 2019-05-29
Next pull request against qemu-4.1. Highlights:
* KVM accelerated support for the XIVE interrupt controller in PAPR
guests
* A number of TCG vector fixes
* Fixes for the PReP / 40p machine
* Improvements to make check-tcg test coverage
Other than that it's just a bunch of assorted fixes, cleanups and
minor improvements.
This supersedes both the pull request dated 2019-05-21 and the one
dated 2019-05-22. I've dropped one hunk which I think may have caused
the check-tcg failure that Peter saw (by enabling the ppc64abi32
build, which I think has been broken for ages). I'm not entirely
certain, since I haven't reproduced exactly the same failure.
# gpg: Signature made Wed 29 May 2019 07:49:04 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.1-20190529: (44 commits)
ppc/pnv: add dummy XSCOM registers for PRD initialization
ppc/pnv: introduce new skiboot platform properties
spapr: Don't migrate the hpt_maxpagesize cap to older machine types
spapr: change default interrupt mode to 'dual'
spapr/xive: fix multiple resets when using the 'dual' interrupt mode
docs: provide documentation on the POWER9 XIVE interrupt controller
spapr/irq: add KVM support to the 'dual' machine
ppc/xics: fix irq priority in ics_set_irq_type()
spapr/irq: initialize the IRQ device only once
spapr/irq: introduce a spapr_irq_init_device() helper
spapr: check for the activation of the KVM IRQ device
spapr: introduce routines to delete the KVM IRQ device
sysbus: add a sysbus_mmio_unmap() helper
spapr/xive: activate KVM support
spapr/xive: add migration support for KVM
spapr/xive: introduce a VM state change handler
spapr/xive: add state synchronization with KVM
spapr/xive: add hcall support when under KVM
spapr/xive: add KVM support
spapr: Print out extra hints when CAS negotiation of interrupt mode fails
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/48a8b399619c...60905286cb51
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