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[Qemu-commits] [qemu/qemu] f92be7: spapr: quantify error messages regard
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] f92be7: spapr: quantify error messages regarding capabilit... |
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Date: |
Wed, 21 Aug 2019 07:17:07 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f92be77fea88b6347f22ca96ba54bef0c382e3b7
https://github.com/qemu/qemu/commit/f92be77fea88b6347f22ca96ba54bef0c382e3b7
Author: Daniel Black <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_caps.c
Log Message:
-----------
spapr: quantify error messages regarding capability settings
Its not immediately obvious how cap-X=Y setting need to be applied
to the command line so, for spapr capability error messages, this
has been clarified to:
appending -machine cap-X=Y
The wrong value messages have been left as is, as the user has found
the right location.
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Daniel Black <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a14f04ebbab80fb7342c277705e6076c309a5e50
https://github.com/qemu/qemu/commit/a14f04ebbab80fb7342c277705e6076c309a5e50
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_iommu.c
Log Message:
-----------
spapr_iommu: Fix xlate trace to print translated address
Currently we basically print IO address twice, fix this.
Fixes: 7e472264e9e2 ("PPC: spapr: iommu: rework traces")
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9aec2e52ce9d9632a86be2d1d0dd493722d2e7be
https://github.com/qemu/qemu/commit/9aec2e52ce9d9632a86be2d1d0dd493722d2e7be
Author: Cornelia Huck <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/arm/virt.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/i386/pc.h
Log Message:
-----------
hw: add compat machines for 4.2
Add 4.2 machine types for arm/i440fx/q35/s390x/spapr.
For i440fx and q35, unversioned cpu models are still translated
to -v1, as 0788a56bd1ae ("i386: Make unversioned CPU models be
aliases") states this should only transition to the latest cpu
model version in 4.3 (or later).
Signed-off-by: Cornelia Huck <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d15d4ad64f12cf88df8eac0cc910fa0637ab15e0
https://github.com/qemu/qemu/commit/d15d4ad64f12cf88df8eac0cc910fa0637ab15e0
Author: David Gibson <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: Allow 2MiB and 16MiB IOMMU pagesizes by default
We've had the qemu and kernel KVM infrastructure to handle larger TCE
page sizes for a while, but forgot to update the defaults to actually
allow them. This turns that change on.
Signed-off-by: David Gibson <address@hidden>
Commit: d14f33976282a8744ca1bf1d64e73996c145aa3f
https://github.com/qemu/qemu/commit/d14f33976282a8744ca1bf1d64e73996c145aa3f
Author: Maxiwell S. Garcia <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/ppc.c
M target/ppc/cpu-qom.h
Log Message:
-----------
migration: Do not re-read the clock on pre_save in case of paused guest
Re-read the timebase before migrate was ported from x86 commit:
6053a86fe7bd: kvmclock: reduce kvmclock difference on migration
The clock move makes the guest knows about the paused time between
the stop and migrate commands. This is an issue in an already-paused
VM because some side effects, like process stalls, could happen
after migration.
So, this patch checks the runstate of guest in the pre_save handler and
do not re-reads the timebase in case of paused state (cold migration).
Signed-off-by: Maxiwell S. Garcia <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1cc792698e568626b5bf833e15e641ad0a81c6bb
https://github.com/qemu/qemu/commit/1cc792698e568626b5bf833e15e641ad0a81c6bb
Author: Stefan Brankovic <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize emulation of lvsl and lvsr instructions
Adding simple macro that is calling tcg implementation of appropriate
instruction if altivec support is active.
Optimization of altivec instruction lvsl (Load Vector for Shift Left).
Place bytes sh:sh+15 of value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F
in destination register. Sh is calculated by adding 2 source registers and
getting bits 60-63 of result.
First, the bits [28-31] are placed from EA to variable sh. After that,
the bytes are created in the following way:
sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
followed by addition of the result with 0x0001020304050607. Value obtained
is placed in higher doubleword element of vD.
(sh+8):(sh+15) by adding the result of previous multiplication with
0x08090a0b0c0d0e0f. Value obtained is placed in lower doubleword element
of vD.
Optimization of altivec instruction lvsr (Load Vector for Shift Right).
Place bytes 16-sh:31-sh of value 0x00 || 0x01 || 0x02 || ... || 0x1E ||
0x1F in destination register. Sh is calculated by adding 2 source
registers and getting bits 60-63 of result.
First, the bits [28-31] are placed from EA to variable sh. After that,
the bytes are created in the following way:
sh:(sh+7) of X(from description) by multiplying sh with 0x0101010101010101
followed by substraction of the result from 0x1011121314151617. Value
obtained is placed in higher doubleword element of vD.
(sh+8):(sh+15) by substracting the result of previous multiplication from
0x18191a1b1c1d1e1f. Value obtained is placed in lower doubleword element
of vD.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4e6d0920e7547e6af4bbac5ffe9adfe6ea621822
https://github.com/qemu/qemu/commit/4e6d0920e7547e6af4bbac5ffe9adfe6ea621822
Author: Stefan Brankovic <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize emulation of vsl and vsr instructions
Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt).
Perform shift operation (left and right respectively) on 128 bit value of
register vA by value specified in bits 125-127 of register vB. Lowest 3
bits in each byte element of register vB must be identical or result is
undefined.
For vsl instruction, the first step is bits 125-127 of register vB have
to be saved in variable sh. Then, the highest sh bits of the lower
doubleword element of register vA are saved in variable shifted,
in order not to lose those bits when shift operation is performed on
the lower doubleword element of register vA, which is the next
step. After shifting the lower doubleword element shift operation
is performed on higher doubleword element of vA, with replacement of
the lowest sh bits(that are now 0) with bits saved in shifted.
For vsr instruction, firstly, the bits 125-127 of register vB have
to be saved in variable sh. Then, the lowest sh bits of the higher
doubleword element of register vA are saved in variable shifted,
in odred not to lose those bits when the shift operation is
performed on the higher doubleword element of register vA, which is
the next step. After shifting higher doubleword element, shift operation
is performed on lower doubleword element of vA, with replacement of
highest sh bits(that are now 0) with bits saved in shifted.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 28876bf27d2792e6b16cfb5283b9fb959fc0ad12
https://github.com/qemu/qemu/commit/28876bf27d2792e6b16cfb5283b9fb959fc0ad12
Author: Alex Bennée <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: move opcode decode tables to PowerPCCPU
The opcode decode tables aren't really part of the CPUPPCState but an
internal implementation detail for the translator. This can cause
problems with memcpy in cpu_copy as any table created during
ppc_cpu_realize get written over causing a memory leak. To avoid this
move the tables into PowerPCCPU which is better suited to hold
internal implementation details.
Attempts to fix: https://bugs.launchpad.net/qemu/+bug/1836558
Cc: address@hidden
Signed-off-by: Alex Bennée <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 083b3f012fc27536afc74d005d706b20eae200f8
https://github.com/qemu/qemu/commit/083b3f012fc27536afc74d005d706b20eae200f8
Author: Stefan Brankovic <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize emulation of vgbbd instruction
Optimize altivec instruction vgbbd (Vector Gather Bits by Bytes by Doubleword)
All ith bits (i in range 1 to 8) of each byte of doubleword element in
source register are concatenated and placed into ith byte of appropriate
doubleword element in destination register.
Following solution is done for both doubleword elements of source register
in parallel, in order to reduce the number of instructions needed(that's why
arrays are used):
First, both doubleword elements of source register vB are placed in
appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
have to be shifted right for 7 and 8 places, respectively, in order to get
bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
After first 8 iteration(first loop), all the first bits are in their final
places, all second bits but second bit from eight byte are in their places...
only 1 eight bit from eight byte is in it's place). In second loop we do all
operations symmetrically, in order to get other half of bits in their final
spots. Results for first and second doubleword elements are saved in
result[0] and result[1] respectively. In the end those results are saved in
appropriate doubleword element of destination register vD.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b8313f0d91b192c9415b3c678b387acb77ad112b
https://github.com/qemu/qemu/commit/b8313f0d91b192c9415b3c678b387acb77ad112b
Author: Stefan Brankovic <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize emulation of vclzd instruction
Optimize Altivec instruction vclzd (Vector Count Leading Zeros Doubleword).
This instruction counts the number of leading zeros of each doubleword element
in source register and places result in the appropriate doubleword element of
destination register.
Using tcg-s count leading zeros instruction two times(once for each
doubleword element of source register vB) and placing result in
appropriate doubleword element of destination register vD.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1872588ede5770751ebc0e1df9909c8a785cb549
https://github.com/qemu/qemu/commit/1872588ede5770751ebc0e1df9909c8a785cb549
Author: Stefan Brankovic <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize emulation of vclzw instruction
Optimize Altivec instruction vclzw (Vector Count Leading Zeros Word).
This instruction counts the number of leading zeros of each word element
in source register and places result in the appropriate word element of
destination register.
Counting is to be performed in four iterations of for loop(one for each
word elemnt of source register vB). Every iteration consists of loading
appropriate word element from source register, counting leading zeros
with tcg_gen_clzi_i32, and saving the result in appropriate word element
of destination register.
Signed-off-by: Stefan Brankovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d758880586323da46e3e737eaefb950a7279dfba
https://github.com/qemu/qemu/commit/d758880586323da46e3e737eaefb950a7279dfba
Author: Shivaprasad G Bhat <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_caps.c
Log Message:
-----------
ppc: fix memory leak in spapr_caps_add_properties
Free the capability name string after setting
the capability.
Signed-off-by: Shivaprasad G Bhat <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dbd26f2f7f589994aa2a2ec9740527a5bf201994
https://github.com/qemu/qemu/commit/dbd26f2f7f589994aa2a2ec9740527a5bf201994
Author: Shivaprasad G Bhat <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_drc.c
Log Message:
-----------
ppc: fix memory leak in spapr_dt_drc()
Leaking the drc_name while preparing the DT properties.
Fixing that.
Also, remove the const qualifier from spapr_drc_name().
Signed-off-by: Shivaprasad G Bhat <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 00005f222973d318a8a4d7bc7a15e251fb8cf604
https://github.com/qemu/qemu/commit/00005f222973d318a8a4d7bc7a15e251fb8cf604
Author: Shivaprasad G Bhat <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
ppc: fix leak in h_client_architecture_support
Free all SpaprOptionVector local pointers after use.
Signed-off-by: Shivaprasad G Bhat <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 03ef074c04a219188bbd0094ee599bd50a0a374e
https://github.com/qemu/qemu/commit/03ef074c04a219188bbd0094ee599bd50a0a374e
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M target/ppc/cpu.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
spapr: Implement dispatch tracking for tcg
Implement cpu_exec_enter/exit on ppc which calls into new methods of
the same name in PPCVirtualHypervisorClass. These are used by spapr
to implement the splpar VPA dispatch counter initially.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
[dwg: Removed unnecessary CONFIG_USER_ONLY checks as suggested by gkurz]
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3a6e6224a9d8f9637890e9beab14fa63eaf67937
https://github.com/qemu/qemu/commit/3a6e6224a9d8f9637890e9beab14fa63eaf67937
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr_cpu_core.h
Log Message:
-----------
spapr: Implement H_PROD
H_PROD is added, and H_CEDE is modified to test the prod bit
according to PAPR.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e8ce0e40ee9494b789cb36260a6cf07bbef83cd0
https://github.com/qemu/qemu/commit/e8ce0e40ee9494b789cb36260a6cf07bbef83cd0
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Implement H_CONFER
This does not do directed yielding and is not quite as strict as PAPR
specifies in terms of precise dispatch behaviour. This generally will
mean suboptimal performance, rather than guest misbehaviour. Linux
does not rely on exact dispatch behaviour.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 107413142bf34aecdea2398a3e976739f1256c64
https://github.com/qemu/qemu/commit/107413142bf34aecdea2398a3e976739f1256c64
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: Implement H_JOIN
This has been useful to modify and test the Linux pseries suspend
code but it requires modification to the guest to call it (due to
being gated by other unimplemented features). It is not otherwise
used by Linux yet, but work is slowly progressing there.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1daba4d1b296d23907b73735615b12588da670fb
https://github.com/qemu/qemu/commit/1daba4d1b296d23907b73735615b12588da670fb
Author: Michael Roth <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
A docs/specs/ppc-spapr-uv-hcalls.txt
Log Message:
-----------
docs/specs: initial spec summary for Ultravisor-related hcalls
For now this only covers hcalls relating to TPM communication since
it's the only one particularly important from a QEMU perspective atm,
but others can be added here where it makes sense.
The full specification for all hcalls/ucalls will eventually be made
available in the public/OpenPower version of the PAPR specification.
Signed-off-by: Michael Roth <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0fb6bd07323019dc8d3f2c124323f71e2ddfc9f4
https://github.com/qemu/qemu/commit/0fb6bd07323019dc8d3f2c124323f71e2ddfc9f4
Author: Michael Roth <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_tpm_proxy.c
M hw/ppc/trace-events
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_tpm_proxy.h
Log Message:
-----------
spapr: initial implementation for H_TPM_COMM/spapr-tpm-proxy
This implements the H_TPM_COMM hypercall, which is used by an
Ultravisor to pass TPM commands directly to the host's TPM device, or
a TPM Resource Manager associated with the device.
This also introduces a new virtual device, spapr-tpm-proxy, which
is used to configure the host TPM path to be used to service
requests sent by H_TPM_COMM hcalls, for example:
-device spapr-tpm-proxy,id=tpmp0,host-path=/dev/tpmrm0
By default, no spapr-tpm-proxy will be created, and hcalls will return
H_FUNCTION.
The full specification for this hypercall can be found in
docs/specs/ppc-spapr-uv-hcalls.txt
Since SVM-related hcalls like H_TPM_COMM use a reserved range of
0xEF00-0xEF80, we introduce a separate hcall table here to handle
them.
Signed-off-by: Michael Roth <address@hidden
Message-Id: <address@hidden>
[dwg: Corrected #include for upstream change]
Signed-off-by: David Gibson <address@hidden>
Commit: 316f239c294101d63a2b336c86c7970d8ae15213
https://github.com/qemu/qemu/commit/316f239c294101d63a2b336c86c7970d8ae15213
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
The only change that SLOF does not rely on QEMU providing an RTAS blob
and provides one itself:
https://git.qemu.org/?p=SLOF.git;a=commitdiff;h=5e4ed1fd0f39e
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1994d3aa4774c86e8e932531186613f3a0860efd
https://github.com/qemu/qemu/commit/1994d3aa4774c86e8e932531186613f3a0860efd
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: use an abstract type for XiveNotifier
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d98ec603c6587075a17820f07cada988a9a675bb
https://github.com/qemu/qemu/commit/d98ec603c6587075a17820f07cada988a9a675bb
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Implement TM_PULL_OS_CTX special command
When a vCPU is not dispatched anymore on a HW thread, the Hypervisor
(KVM on Linux) invalidates the OS interrupt context of a vCPU with
this special command. It returns the OS CAM line value and resets the
VO bit.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 52c5acf04ee0f111657c03916db13ff325c58866
https://github.com/qemu/qemu/commit/52c5acf04ee0f111657c03916db13ff325c58866
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Provide backlog support
If backlog is activated ('b' bit) on the END, the pending priority of
a missed event is recorded in the IPB field of the NVT for a later
resend.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b4e3066684ea9379e09c8c6b0902eceb939fa97c
https://github.com/qemu/qemu/commit/b4e3066684ea9379e09c8c6b0902eceb939fa97c
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Provide escalation support
If the XIVE presenter can not find the NVT dispatched on any of the HW
threads, it can not deliver the interrupt. XIVE offers an escalation
mechanism to handle such scenarios and inform the hypervisor that an
action should be taken.
Escalation is configured by setting the 'e' bit and the EAS in word 4
& 5 to let the HW look for the escalation END on which to trigger a
new event.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 53e934921d660be951167fccad4b6302c4633486
https://github.com/qemu/qemu/commit/53e934921d660be951167fccad4b6302c4633486
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive: Provide unconditional escalation support
When the 'u' bit is set the escalation is said to be 'unconditional'
which means that the ESe PQ bits are not used. Introduce a
xive_router_end_es_notify() routine to share code with the ESn
notification.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ad31e2d242399bdaa300b940bbef253331c92ec3
https://github.com/qemu/qemu/commit/ad31e2d242399bdaa300b940bbef253331c92ec3
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive: Provide silent escalation support
When the 's' bit is set the escalation is said to be 'silent' or
'silent/gather'. In such configuration, the notification sequence is
skipped and only the escalation sequence is performed. This is used to
configure all the EQs of a vCPU to escalate on a single EQ which will
then target the hypervisor.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c5e760e0f2de9e6ba682c001c8cdd0b40c8b5731
https://github.com/qemu/qemu/commit/c5e760e0f2de9e6ba682c001c8cdd0b40c8b5731
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
Log Message:
-----------
ppc/xive: Improve 'info pic' support
Provide a better output of the XIVE END structures including the
escalation information and extend the PowerNV machine 'info pic'
command with a dump of the END EAS table used for escalations.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4b5e06c9465ece90b48cb0b978c0b898ea46e133
https://github.com/qemu/qemu/commit/4b5e06c9465ece90b48cb0b978c0b898ea46e133
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M include/hw/boards.h
M vl.c
Log Message:
-----------
machine: Add wakeup method to MachineClass
Waking from suspend is not logically a machine reset on all machines,
particularly in the paravirtualized case rather than hardware
emulated. The ppc spapr machine for example just invokes hypervisor
to suspend, and expects that call to return with the machine in the
same state (modulo some possible migration and reconfiguration
details).
Implement a machine ->wakeup method and use that if it exists.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c508bd12f65e14f82eb62e462bcb64898d8806a6
https://github.com/qemu/qemu/commit/c508bd12f65e14f82eb62e462bcb64898d8806a6
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/i386/pc.c
M vl.c
Log Message:
-----------
i386: use machine class ->wakeup method
Move the i386 suspend_wakeup logic out of the fallback path, and into
the new ->wakeup method.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 93eac7b8f44738f7d2f4ba4460d67b04af5b0b99
https://github.com/qemu/qemu/commit/93eac7b8f44738f7d2f4ba4460d67b04af5b0b99
Author: Nicholas Piggin <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_rtas.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Implement ibm,suspend-me
This has been useful to modify and test the Linux pseries suspend
code but it requires modification to the guest to call it (due to
being gated by other unimplemented features). It is not otherwise
used by Linux yet, but work is slowly progressing there.
This allows a (lightly modified) guest kernel to suspend with
`echo mem > /sys/power/state` and be resumed with system_wakeup
monitor command.
Signed-off-by: Nicholas Piggin <address@hidden>
Message-Id: <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1e8f51e856621d3615a21cfea6f0baf055cbcce8
https://github.com/qemu/qemu/commit/1e8f51e856621d3615a21cfea6f0baf055cbcce8
Author: Shivaprasad G Bhat <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
ppc: remove idle_timer logic
The logic is broken for multiple vcpu guests, also causing memory leak.
The logic is in place to handle kvm not having KVM_CAP_PPC_IRQ_LEVEL,
which is part of the kernel now since 2.6.37. Instead of fixing the
leak, drop the redundant logic which is not excercised on new kernels
anymore. Exit with error on older kernels.
Signed-off-by: Shivaprasad G Bhat <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 078eb6b05b7f962e43d8bc376e0b96cdd550c17a
https://github.com/qemu/qemu/commit/078eb6b05b7f962e43d8bc376e0b96cdd550c17a
Author: Greg Kurz <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr/pci: Consolidate de-allocation of MSIs
When freeing MSIs, we need to:
- remove them from the machine's MSI bitmap
- remove them from the IC backend
- remove them from the PHB's MSI cache
This is currently open coded in two places in rtas_ibm_change_msi(),
and we're about to need this in spapr_phb_reset() as well. Instead of
duplicating this code again, make it a destroy function for the PHB's
MSI cache. Removing an MSI device from the cache will call the destroy
function internally.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ea52074d3a1c5fbe70f3014dc1b1f2e7d5ced5de
https://github.com/qemu/qemu/commit/ea52074d3a1c5fbe70f3014dc1b1f2e7d5ced5de
Author: Greg Kurz <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr/pci: Free MSIs during reset
When the machine is reset, the MSI bitmap is cleared but the allocated
MSIs are not freed. Some operating systems, such as AIX, can detect the
previous configuration and assert.
Empty the MSI cache, this performs the needed cleanup.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e1588bcdd2ceca232021a626aa3b8e835ea49c52
https://github.com/qemu/qemu/commit/e1588bcdd2ceca232021a626aa3b8e835ea49c52
Author: Greg Kurz <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr/irq: Drop spapr_irq_msi_reset()
PHBs already take care of clearing the MSIs from the bitmap during reset
or unplug. No need to do this globally from the machine code. Rather add
an assert to ensure that PHBs have acted as expected.
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
[dwg: Fix crash in qtest case where spapr->irq_map can be NULL at the
new assert()]
Signed-off-by: David Gibson <address@hidden>
Commit: fd38b1629cdb73da17e6fa294168e0c1bb1ccb07
https://github.com/qemu/qemu/commit/fd38b1629cdb73da17e6fa294168e0c1bb1ccb07
Author: Paul Mackerras <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/char/spapr_vty.c
Log Message:
-----------
spapr: Implement better workaround in spapr-vty device
Linux guest kernels have code which scans the string of characters
returned from the H_GET_TERM_CHAR hypercall and removes any \0
character which comes immediately after a \r character. This is to
work around a bug which was present in some ancient versions of
PowerVM. In order to avoid the corruption of the console byte stream
that this introduced, commit 6c3bc244d3cb ("spapr: Implement bug in
spapr-vty device to be compatible with PowerVM") added a workaround
which adds a \0 character after every \r character. Unfortunately,
this corrupts the console byte stream for those operating systems,
such as AIX, which don't remove the null bytes.
We can avoid triggering the Linux kernel workaround if we avoid
returning a buffer which contains a \0 after a \r. We can do that by
breaking out of the loop in vty_getchars() if we are about to insert a
\0 and the previous character in the buffer is a \r. That means we
return the characters up to the \r for the current H_GET_TERM_CHAR,
and the characters starting with the \0 for the next one.
With this workaround, we don't insert any spurious characters and we
avoid triggering the Linux kernel workaround, so the guest will
receive an uncorrupted stream whether or not they have the workaround.
Fixes: 6c3bc244d3cb ("spapr: Implement bug in spapr-vty device to be compatible
with PowerVM")
Signed-off-by: Paul Mackerras <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f55750e4e4fb35b6a12c81c485f16494e2c61ad2
https://github.com/qemu/qemu/commit/f55750e4e4fb35b6a12c81c485f16494e2c61ad2
Author: Cédric Le Goater <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
spapr/xive: Mask the EAS when allocating an IRQ
If an IRQ is allocated and not configured, such as a MSI requested by
a PCI driver, it can be saved in its default state and possibly later
on restored using the same state. If not initially MASKED, KVM will
try to find a matching priority/target tuple for the interrupt and
fail to restore the VM because 0/0 is not a valid target.
When allocating a IRQ number, the EAS should be set to a sane default :
VALID and MASKED.
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cfc61ba62f30753849fe2b78da8b6d0a0a639db2
https://github.com/qemu/qemu/commit/cfc61ba62f30753849fe2b78da8b6d0a0a639db2
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Add Directed Privileged Door-bell Exception State (DPDES) SPR
DPDES stores a status of a doorbell message and if it is lost in
migration, the destination CPU won't receive it. This does not hit us
much as IPIs complete too quick to catch a pending one and even if
we missed one, broadcasts happen often enough to wake that CPU.
This defines DPDES and registers with KVM for migration.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 31eb7dddacc242af244798854444c3497b515e9f
https://github.com/qemu/qemu/commit/31eb7dddacc242af244798854444c3497b515e9f
Author: Paul A. Clarke <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M disas/ppc.c
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
M target/ppc/translate/fp-impl.inc.c
M target/ppc/translate/fp-ops.inc.c
Log Message:
-----------
ppc: Add support for 'mffsl' instruction
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.
'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from the FPSCR.
On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction
will execute identically to 'mffs'.
Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which
is both bits of the FPSCR rounding mode, as defined in the ISA.
I also fixed a typo in the definition of FPSCR_FR.
Signed-off-by: Paul A. Clarke <address@hidden>
v4:
- nit: added some braces to resolve a checkpatch complaint.
v3:
- Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a
temporary, per review from Richard Henderson.
v2:
- I found that I copied too much of the 'mffs' implementation.
The 'Rc' condition code bits are not needed for 'mffsl'. Removed.
- I now free the (renamed) 'tmask' temporary.
- I now bail early for older ISA to the original 'mffs' implementation.
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e6f1bfb21121b5aaf6f5ff339157c0d55e8b9fe2
https://github.com/qemu/qemu/commit/e6f1bfb21121b5aaf6f5ff339157c0d55e8b9fe2
Author: Paul A. Clarke <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
ppc: conform to processor User's Manual for xscvdpspn
The POWER8 and POWER9 User's Manuals specify the implementation
behavior for what the ISA leaves "undefined" behavior for the
xscvdpspn and xscvdpsp instructions. This patch corrects the QEMU
implementation to match the hardware implementation for that case.
ISA 3.0B has xscvdpspn leaving its result in word 0 of the target register,
with the other words of the target register left "undefined".
The User's Manuals specify:
VSX scalar convert from double-precision to single-precision (xscvdpsp,
xscvdpspn).
VSR[32:63] is set to VSR[0:31].
So, words 0 and 1 both contain the result.
Note: this is important because GCC as of version 8 or so, assumes and takes
advantage of this behavior to optimize the following sequence:
xscvdpspn vs0,vs1
mffprwz r8,f0
ISA 3.0B has xscvdpspn leaving its result in word 0 of the target register,
and mffprwz expecting its input to come from word 1 of the source register.
This sequence fails with QEMU, as a shift is required between those two
instructions. However, since the hardware splats the result to both words 0
and 1 of its output register, the shift is not necessary.
Expect a future revision of the ISA to specify this behavior.
Signed-off-by: Paul A. Clarke <address@hidden>
v2
- Splitting patch "ppc: Three floating point fixes"; this is just one part.
- Updated commit message to clarify behavior is documented in User's Manuals.
- Updated commit message to correct which words are in output and source of
xscvdpspn and mffprz.
- No source changes to this part of the original patch.
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a7b7b98318f7d483e016f0f412df2b8a7dc1d636
https://github.com/qemu/qemu/commit/a7b7b98318f7d483e016f0f412df2b8a7dc1d636
Author: Paul A. Clarke <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
ppc: Fix emulated INFINITY and NAN conversions
helper_todouble() was not properly converting INFINITY from 32 bit
float to 64 bit double.
(Normalized operand conversion is unchanged, other than indentation.)
Signed-off-by: Paul A. Clarke <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c0e6616b6685ffdb4c5e091bc152e46e14703dd1
https://github.com/qemu/qemu/commit/c0e6616b6685ffdb4c5e091bc152e46e14703dd1
Author: Paul A. Clarke <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
ppc: Fix emulated single to double denormalized conversions
helper_todouble() was not properly converting any denormalized 32 bit
float to 64 bit double.
Fix-suggested-by: Richard Henderson <address@hidden>
Signed-off-by: Paul A. Clarke <address@hidden>
v2:
- Splitting patch "ppc: Three floating point fixes"; this is just one part.
- Original suggested "fix" was likely flawed. v2 is rewritten by
Richard Henderson (Thanks, Richard!); I reformatted the comments in a
couple of places, compiled, and tested.
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e65472c7bc413d79faa61eb1d05c540b03945894
https://github.com/qemu/qemu/commit/e65472c7bc413d79faa61eb1d05c540b03945894
Author: Peter Maydell <address@hidden>
Date: 2019-08-21 (Wed, 21 Aug 2019)
Changed paths:
M disas/ppc.c
A docs/specs/ppc-spapr-uv-hcalls.txt
M hw/arm/virt.c
M hw/char/spapr_vty.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/intc/pnv_xive.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M hw/ppc/Makefile.objs
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtas.c
A hw/ppc/spapr_tpm_proxy.c
M hw/ppc/trace-events
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/i386/pc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
M include/hw/ppc/spapr_irq.h
A include/hw/ppc/spapr_tpm_proxy.h
M include/hw/ppc/xive.h
M include/hw/ppc/xive_regs.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/kvm.c
M target/ppc/translate.c
M target/ppc/translate/fp-impl.inc.c
M target/ppc/translate/fp-ops.inc.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate_init.inc.c
M vl.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20190821' into
staging
ppc patch queue for 2019-08-21
First ppc and spapr pull request for qemu-4.2. Includes:
* Some TCG emulation fixes and performance improvements
* Support for the mffsl instruction in TCG
* Added missing DPDES SPR
* Some enhancements to the emulation of the XIVE interrupt
controller
* Cleanups to spapr MSI management
* Some new suspend/resume infrastructure and a draft suspend
implementation for spapr
* New spapr hypercall for TPM communication (will be needed for
secure guests under an Ultravisor)
* Fix several memory leaks
And a few other assorted fixes.
# gpg: Signature made Wed 21 Aug 2019 08:24:44 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.2-20190821: (42 commits)
ppc: Fix emulated single to double denormalized conversions
ppc: Fix emulated INFINITY and NAN conversions
ppc: conform to processor User's Manual for xscvdpspn
ppc: Add support for 'mffsl' instruction
target/ppc: Add Directed Privileged Door-bell Exception State (DPDES) SPR
spapr/xive: Mask the EAS when allocating an IRQ
spapr: Implement better workaround in spapr-vty device
spapr/irq: Drop spapr_irq_msi_reset()
spapr/pci: Free MSIs during reset
spapr/pci: Consolidate de-allocation of MSIs
ppc: remove idle_timer logic
spapr: Implement ibm,suspend-me
i386: use machine class ->wakeup method
machine: Add wakeup method to MachineClass
ppc/xive: Improve 'info pic' support
ppc/xive: Provide silent escalation support
ppc/xive: Provide unconditional escalation support
ppc/xive: Provide escalation support
ppc/xive: Provide backlog support
ppc/xive: Implement TM_PULL_OS_CTX special command
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/f2cfa1229e53...e65472c7bc41
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