[Qemu-commits] [qemu/qemu] 38fc68: target/ppc: Remove unused PPC_INPUT_INT defines

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 38fc68a4895803f0841b46f1d01113cdcd36541d
      
https://github.com/qemu/qemu/commit/38fc68a4895803f0841b46f1d01113cdcd36541d
  Author: Fabiano Rosas <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc: Remove unused PPC_INPUT_INT defines

They were added in "16415335be Use correct input constant" with a
single use in kvm_arch_pre_run but that function's implementation was
removed by "1e8f51e856 ppc: remove idle_timer logic".

Signed-off-by: Fabiano Rosas <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bc5fdfc0a1377418902e215f8d7be00e46b9ac9c
      
https://github.com/qemu/qemu/commit/bc5fdfc0a1377418902e215f8d7be00e46b9ac9c
  Author: Fabiano Rosas <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Handle AIL=0 in ppc_excp_vector_offset

The exception vector offset calculation was moved into a function but
the case when AIL=0 was not checked.

The reason we got away with this is that the sole caller of
ppc_excp_vector_offset checks the AIL before calling the function:

    /* Handle AIL */
    if (ail) {
        ...
        vector |= ppc_excp_vector_offset(cs, ail);
    }

Fixes: 2586a4d7a0 ("target/ppc: Move exception vector offset computation into a 
function")
Signed-off-by: Fabiano Rosas <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 50fd0c375bef09d22b6828972c4ed4f945c95ed8
      
https://github.com/qemu/qemu/commit/50fd0c375bef09d22b6828972c4ed4f945c95ed8
  Author: Bharata B Rao <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M include/standard-headers/asm-x86/bootparam.h
    M include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/input-event-codes.h
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/rdma/vmw_pvrdma-abi.h
    M linux-headers/linux/kvm.h

  Log Message:
  -----------
  linux-headers: Update

Update to mainline commit: d1eef1c61974 ("Linux 5.5-rc2")

Signed-off-by: Bharata B Rao <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 905db91697f53377b70c86fa8521308cdc25510b
      
https://github.com/qemu/qemu/commit/905db91697f53377b70c86fa8521308cdc25510b
  Author: Bharata B Rao <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/spapr.c
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  ppc/spapr: Support reboot of secure pseries guest

A pseries guest can be run as a secure guest on Ultravisor-enabled
POWER platforms. When such a secure guest is reset, we need to
release/reset a few resources both on ultravisor and hypervisor side.
This is achieved by invoking this new ioctl KVM_PPC_SVM_OFF from the
machine reset path.

As part of this ioctl, the secure guest is essentially transitioned
back to normal mode so that it can reboot like a regular guest and
become secure again.

This ioctl has no effect when invoked for a normal guest. If this ioctl
fails for a secure guest, the guest is terminated.

Signed-off-by: Bharata B Rao <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8f06e3705e83c9df5a8dc61bd72b4ccf2794f076
      
https://github.com/qemu/qemu/commit/8f06e3705e83c9df5a8dc61bd72b4ccf2794f076
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c

  Log Message:
  -----------
  ppc/pnv: Modify the powerdown notifier to get the PowerNV machine

Use container_of() instead of qdev_get_machine()

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 068fe58cf93030fd96b7659bfc7626867ecd518a
      
https://github.com/qemu/qemu/commit/068fe58cf93030fd96b7659bfc7626867ecd518a
  Author: Laurent Vivier <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/misc/mos6522.c
    M include/hw/misc/mos6522.h

  Log Message:
  -----------
  mos6522: remove anh register

Register addr 1 is defined as buffer A with handshake (vBufAH),
register addr 15 is also defined as buffer A without handshake (vBufA).

As both addresses access the same register, remove the definition of
'anh' and use only 'a' (with VIA_REG_ANH and VIA_REG_A).

Fixes: 51f233ec92cd ("misc: introduce new mos6522 VIA device and enable it for 
ppc builds")
Signed-off-by: Laurent Vivier <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6cc64796f2b031186b6ae9c6c5932ea972a8c6cd
      
https://github.com/qemu/qemu/commit/6cc64796f2b031186b6ae9c6c5932ea972a8c6cd
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/spapr_xive.c
    M include/hw/ppc/spapr_xive.h

  Log Message:
  -----------
  spapr/xive: Use device_class_set_parent_realize()

The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0b731978818ff4dd21eb250e8d8d2803015afba3
      
https://github.com/qemu/qemu/commit/0b731978818ff4dd21eb250e8d8d2803015afba3
  Author: Bharata B Rao <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG

Invoking KVM_SVM_OFF ioctl for TCG guests will lead to a QEMU crash.
Fix this by ensuring that we don't call KVM_SVM_OFF ioctl on TCG.

Reported-by: Alexey Kardashevskiy <address@hidden>
Fixes: 4930c1966249 ("ppc/spapr: Support reboot of secure pseries guest")
Signed-off-by: Bharata B Rao <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9b6c1da5e9fb765a675d6cf85325946825bae541
      
https://github.com/qemu/qemu/commit/9b6c1da5e9fb765a675d6cf85325946825bae541
  Author: Daniel Henrique Barboza <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr.c: remove 'out' label in spapr_dt_cas_updates()

'out' can be replaced by 'return' with the appropriate
return value.

CC: David Gibson <address@hidden>
CC: address@hidden
Signed-off-by: Daniel Henrique Barboza <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 400431ef48306248d6420b713287e921051d2b2d
      
https://github.com/qemu/qemu/commit/400431ef48306248d6420b713287e921051d2b2d
  Author: Daniel Henrique Barboza <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/ppc440_bamboo.c

  Log Message:
  -----------
  ppc440_bamboo.c: remove label from bamboo_load_device_tree()

'out' label can be replaced by 'return -1' in all cases.

CC: David Gibson <address@hidden>
CC: address@hidden
Signed-off-by: Daniel Henrique Barboza <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e44acde2f89e72139a44bc2db8183286ba5d4e07
      
https://github.com/qemu/qemu/commit/e44acde2f89e72139a44bc2db8183286ba5d4e07
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c

  Log Message:
  -----------
  ppc/pnv: Drop "num-chips" machine property

The number of CPU chips of the powernv machine is configurable through a
"num-chips" property. This doesn't fit well with the CPU topology, eg.
some configurations can come up with more CPUs than the maximum of CPUs
set in the toplogy. This causes assertion to be hit with mttcg:

   -machine powernv,num-chips=2 -smp cores=2 -accel tcg,thread=multi

ERROR:
tcg/tcg.c:789:tcg_register_thread: assertion failed: (n < ms->smp.max_cpus)
Aborted (core dumped)

Mttcg mandates the CPU topology to be dimensioned to the actual number
of CPUs, depending on the number of chips the user asked for. That is,
'-machine num-chips=N' should always have a '-smp' companion with a
topology that meats the resulting number of CPUs, typically
'-smp sockets=N'.

It thus seems that "num-chips" doesn't bring anything but forcing the user
to specify the requested number of chips on the command line twice. Simplify
the command line by computing the number of chips based on the CPU topology
exclusively. The powernv machine isn't a production thing ; it is mostly
used by developpers to prepare the bringup of real HW. Because of this and
for simplicity, this deliberately ignores the official deprecation process
and dumps "num-chips" right away : '-smp sockets=N' is now the only way to
control the number of CPU chips.

This is done at machine init because smp_parse() is called after instance
init.

Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: baa45b17101c5375be031edb863e94a79c75b86c
      
https://github.com/qemu/qemu/commit/baa45b17101c5375be031edb863e94a79c75b86c
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr/xive: remove redundant check in spapr_match_nvt()

spapr_match_nvt() is a XIVE operation and is used by the machine to
look for a matching target when an event notification is being
delivered. An assert checks that spapr_match_nvt() is called only when
the machine has selected the XIVE interrupt mode but it is redundant
with the XIVE_PRESENTER() dynamic cast.

Apply the cast to spapr->active_intc and remove the assert.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 34bdca8faebf59dff71bc6eae89f54926362b45e
      
https://github.com/qemu/qemu/commit/34bdca8faebf59dff71bc6eae89f54926362b45e
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_psi.c

  Log Message:
  -----------
  ppc/pnv: Introduce a "xics" property alias under the PSI model

This removes the need of the intermediate link under PSI to pass the
XICS link to the underlying ICSState object.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 245cdb7f547db0a99fb5f4847f929a508cf82351
      
https://github.com/qemu/qemu/commit/245cdb7f547db0a99fb5f4847f929a508cf82351
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Introduce a "xics" property under the POWER8 chip

POWER8 is the only chip using the XICS interface. Add a "xics" link
and a XICSFabric attribute under this chip to remove the use of
qdev_get_machine()

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0da41d3c5af7897e742c2fa4f6a5c5609b86c493
      
https://github.com/qemu/qemu/commit/0da41d3c5af7897e742c2fa4f6a5c5609b86c493
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/pnv_xive.c
    M include/hw/ppc/pnv_xive.h

  Log Message:
  -----------
  pnv/xive: Use device_class_set_parent_realize()

The XIVE router base class currently inherits an empty realize hook
from the sysbus device base class, but it will soon implement one
of its own to perform some sanity checks. Do the preliminary plumbing
to have it called.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d1214b819f26dcf95329af624e74bf42eeeb1a9a
      
https://github.com/qemu/qemu/commit/d1214b819f26dcf95329af624e74bf42eeeb1a9a
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/xive.c
    M hw/ppc/pnv.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router

In order to get rid of qdev_get_machine(), first add a pointer to the
XIVE fabric under the XIVE router and make it configurable through a
QOM link property.

Configure it in the spapr and pnv machine. In the case of pnv, the XIVE
routers are under the chip, so this is done with a QOM alias property of
the POWER9 pnv chip.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 53981dd50566288904c03e5e7d31b43bc587cb37
      
https://github.com/qemu/qemu/commit/53981dd50566288904c03e5e7d31b43bc587cb37
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/xive.c

  Log Message:
  -----------
  xive: Use the XIVE fabric link under the XIVE router

Now that the spapr and pnv machines do set the "xive-fabric" link, the
use of the XIVE fabric pointer becomes mandatory. This is checked with
an assert() in a new realize hook. Since the XIVE router is realized at
machine init for the all the machine's life time, no risk to abort an
already running guest (ie. not a hotplug path).

This gets rid of a qdev_get_machine() call.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 764f9b2559f0dac7d24da2920445a42a5edf158b
      
https://github.com/qemu/qemu/commit/764f9b2559f0dac7d24da2920445a42a5edf158b
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Add an "nr-threads" property to the base chip class

Set it at chip creation and forward it to the cores. This allows to drop
a call to qdev_get_machine().

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d8137bb7296e55c74b081b48f8cf31aad3b7632e
      
https://github.com/qemu/qemu/commit/d8137bb7296e55c74b081b48f8cf31aad3b7632e
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_bmc.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Add a "pnor" const link property to the BMC internal simulator

This allows to get rid of a call to qdev_get_machine().

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 479509463b4dc126d2324f046c5e92bd5f0160ef
      
https://github.com/qemu/qemu/commit/479509463b4dc126d2324f046c5e92bd5f0160ef
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/spapr_xive.c
    M hw/intc/xive.c
    M hw/ppc/pnv.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  xive: Add a "presenter" link property to the TCTX object

This will be used in subsequent patches to access the XIVE associated to
a TCTX without reaching out to the machine through qdev_get_machine().

Signed-off-by: Cédric Le Goater <address@hidden>
[ groug: - split patch
         - write subject and changelog ]
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 74e51a38f74537d7260f0d45fb01e675f1558163
      
https://github.com/qemu/qemu/commit/74e51a38f74537d7260f0d45fb01e675f1558163
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/spapr_xive_kvm.c

  Log Message:
  -----------
  spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr

And use it instead of reaching out to the machine. This allows to get rid
of a call to qdev_get_machine() and to reduce the scope of another one so
that it is only used within the argument list of error_append_hint(). This
is an acceptable tradeoff compared to all it would require to know about
the maximum number of CPUs here without calling qdev_get_machine().

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 806fed593d0ed88d2f11e45cc54612daec98fe27
      
https://github.com/qemu/qemu/commit/806fed593d0ed88d2f11e45cc54612daec98fe27
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/intc/pnv_xive.c
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr

And use it instead of reaching out to the machine. This allows to get
rid of pnv_get_chip().

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fcb7e4a8f4e220306ac0c5acda66ca255d79f658
      
https://github.com/qemu/qemu/commit/fcb7e4a8f4e220306ac0c5acda66ca255d79f658
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv_psi.c

  Log Message:
  -----------
  pnv/psi: Add device reset hook

And call it from a QEMU reset handler. This allows each PNV child class to
override the reset hook if needed, eg. POWER8 doesn't but POWER9 does.
The proper way to do that would be to use device_class_set_parent_reset(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_reset
pointer adds a fair amount of code. Calling pnv_psi_reset() explicitely is
fine for now.

A subsequent patch will consolidate the call to qemu_register_reset() in
a single place.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b91cad2f0751ab5c2e1b746a835ec0f45fec1c23
      
https://github.com/qemu/qemu/commit/b91cad2f0751ab5c2e1b746a835ec0f45fec1c23
  Author: Greg Kurz <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv_psi.c

  Log Message:
  -----------
  pnv/psi: Consolidate some duplicated code in pnv_psi_realize()

The proper way to do that would be to use device_class_set_parent_realize(),
but defining a Pnv8PsiClass and a Pnv9PsiClass types with a parent_realize
pointer adds a fair amount of code. Calling pnv_psi_realize() explicitely
is fine for now.

This should probably be achieved with a device realize hook in the
PSI base class and device_class_set_parent_realize() in the children
classes.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3a688294e2c36575fd3e259a64a066b38e164cbb
      
https://github.com/qemu/qemu/commit/3a688294e2c36575fd3e259a64a066b38e164cbb
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv_pnor.c

  Log Message:
  -----------
  ppc/pnv: check return value of blk_pwrite()

When updating the PNOR file contents, we should check for a possible
failure of blk_pwrite().

Fixes Coverity issue CID 1412228.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fc2527fb024abf92719952c939d751739455bd6b
      
https://github.com/qemu/qemu/commit/fc2527fb024abf92719952c939d751739455bd6b
  Author: Cédric Le Goater <address@hidden>
  Date:   2020-01-08 (Wed, 08 Jan 2020)

  Changed paths:
    M hw/ppc/pnv_pnor.c
    M include/hw/ppc/pnv_pnor.h

  Log Message:
  -----------
  ppc/pnv: fix check on return value of blk_getlength()

blk_getlength() returns an int64_t but the result is stored in a
uint32_t. Errors (negative values) won't be caught by the check in
pnv_pnor_realize() and blk_blockalign() will allocate a very large
buffer in such cases.

Fixes Coverity issue CID 1412226.

Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: dc65a5bdc9fa543690a775b50d4ffbeb22c56d6d
      
https://github.com/qemu/qemu/commit/dc65a5bdc9fa543690a775b50d4ffbeb22c56d6d
  Author: Peter Maydell <address@hidden>
  Date:   2020-01-10 (Fri, 10 Jan 2020)

  Changed paths:
    M hw/intc/pnv_xive.c
    M hw/intc/spapr_xive.c
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/xive.c
    M hw/misc/mos6522.c
    M hw/ppc/pnv.c
    M hw/ppc/pnv_bmc.c
    M hw/ppc/pnv_pnor.c
    M hw/ppc/pnv_psi.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_irq.c
    M include/hw/misc/mos6522.h
    M include/hw/ppc/pnv.h
    M include/hw/ppc/pnv_pnor.h
    M include/hw/ppc/pnv_xive.h
    M include/hw/ppc/spapr_xive.h
    M include/hw/ppc/xive.h
    M include/standard-headers/asm-x86/bootparam.h
    M include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/input-event-codes.h
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/rdma/vmw_pvrdma-abi.h
    M linux-headers/linux/kvm.h
    M target/ppc/excp_helper.c
    M target/ppc/kvm.c
    M target/ppc/kvm_ppc.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200108' into 
staging

ppc patch queue 2020-01-08

Here's another pull request for qemu-5.0 of ppc related changes.
Highlights are:
 * First parts of support for POWER Secure VMs
 * Rework to clean up how we pass context information to the various
   components of the pnv machine (reduces usage of qdev_get_machine())
 * Assorted cleanups and bugfixes

# gpg: Signature made Wed 08 Jan 2020 05:22:08 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.0-20200108: (26 commits)
  ppc/pnv: fix check on return value of blk_getlength()
  ppc/pnv: check return value of blk_pwrite()
  pnv/psi: Consolidate some duplicated code in pnv_psi_realize()
  pnv/psi: Add device reset hook
  pnv/xive: Deduce the PnvXive pointer from XiveTCTX::xptr
  spapr/xive: Deduce the SpaprXive pointer from XiveTCTX::xptr
  xive: Add a "presenter" link property to the TCTX object
  ppc/pnv: Add a "pnor" const link property to the BMC internal simulator
  ppc/pnv: Add an "nr-threads" property to the base chip class
  xive: Use the XIVE fabric link under the XIVE router
  spapr, pnv, xive: Add a "xive-fabric" link to the XIVE router
  pnv/xive: Use device_class_set_parent_realize()
  ppc/pnv: Introduce a "xics" property under the POWER8 chip
  ppc/pnv: Introduce a "xics" property alias under the PSI model
  spapr/xive: remove redundant check in spapr_match_nvt()
  ppc/pnv: Drop "num-chips" machine property
  ppc440_bamboo.c: remove label from bamboo_load_device_tree()
  spapr.c: remove 'out' label in spapr_dt_cas_updates()
  ppc/spapr: Don't call KVM_SVM_OFF ioctl on TCG
  spapr/xive: Use device_class_set_parent_realize()
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f38a71b01f83...dc65a5bdc9fa