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[Qemu-commits] [qemu/qemu] ed5abf: target/riscv: Correctly implement TSR

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] ed5abf: target/riscv: Correctly implement TSR trap
Date: Tue, 17 Mar 2020 06:00:16 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ed5abf46b3c414ef58e647145f19b3966700b206
  Author: Alistair Francis <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  target/riscv: Correctly implement TSR trap

As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Jonathan Behrens <address@hidden
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: bfd05e8127353339e905a45990f3af379a2c2aec
  Author: Bin Meng <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/opensbi

  Log Message:
  roms: opensbi: Upgrade from v0.5 to v0.6

Upgrade OpenSBI from v0.5 to v0.6 and the pre-built bios images.

The v0.6 release includes the following commits:

dd8ef28 firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils
98f4a20 firmware: Introduce relocation lottery
f728a0b include: Sync-up encoding with priv v1.12-draft and hypervisor 
18897aa include: Use _UL() and _ULL() for defines in riscv_encoding.h
7a13beb firmware: Add preferred boot HART field in struct fw_dynamic_info
215421c lib: Remove date and time from init message
838657c include: Remove ilen member of struct unpriv_trap
b1d8c98 lib: No need to set VSSTATUS.MXR bit in get_insn()
0e1322b lib: Better naming of unpriv APIs for wider use
75f903d lib: Simplify trap parameters in sbi_ecall functions
c96cc03 lib: Fix CPU capabilities detection function
ab14f94 lib: Fix probe extension
813f7f4 lib: Add error detection for misa_extension
dc40042 include: sbi_platform: fix compilation for GCC-9
bd732ae include: Add guest external interrupt related defines
6590a7d lib: Delegate guest page faults to HS-mode
4370f18 include: Extend struct sbi_trap_info for mtval2 and mtinst
086dbdf lib: Fix sbi_get_insn() for load guest page fault
2be424b lib: Extend trap redirection for hypervisor v0.5 spec
7219477 lib: Use MTINST CSR in misaligned load/store emulation
b8732fe lib: Add replacement extension and function ids
aa0ed1d lib: Remove redundant IPI types
1092663 lib: Add TIME extension in SBI
9777aee lib: Add IPI extension in SBI
9407202 lib: Add hfence instruction encoding
331ff6a lib: Support stage1 and stage2 tlb flushing
86a31f5 lib: Implement RFENCE extension
c7d1b12 firmware: Return real DTB address when FW_xyz_FDT_ADDR is not defined
9beb573 firmware: Improve comments for fw_prev_arg1() and fw_next_arg1()
fc6bd90 docs: Improve docs for FDT address passing
46a90d9 lib: utils: Support CLINT with 32bit MMIO access on RV64 system
c0849cd platform: Add T-head C910 initial support
e746673 lib: Remove unnecessary checks from init_coldboot() and init_warmboot()
c3e406f lib: Add initial sbi_exit() API
55e191e lib: Add system early_exit and final_exit APIs
6469ed1 lib: Add timer exit API
b325f6b lib: Add ipi exit API
1993182 lib: Add irqchip exit API
2aa43a1 lib: save/restore MIE CSR in sbi_hart_wait_for_coldboot()
b0c9787 lib: do sbi_exit() upon halt IPI
15ed1e7 lib: improve system reboot and shutdown implementation
73c19e6 lib: zero-out memory allocated using sbi_scratch_alloc_offset()
a67fd68 lib: Add sbi_init_count() API
049ad0b build: Use -ffreestanding
e340bbf include: Add OPENSBI_EXTERNAL_SBI_TYPES in sbi_types.h
b28b8ac docs: Add description of using OPENSBI_EXTERNAL_SBI_TYPES
adf8b73 platform: thead/c910: Remove SBI_PLATFORM_HAS_PMP
f95dd39 docs: platform: Update SiFive FU540 doc as-per U-Boot v2020.01
6ffe1be firmware: Fix placement of .align directives
7daccae platform: thead/c910: Don't enable L2 cache in warm boot
a73d45c platform: thead/c910: Don't set plic/clint address in warm boot
30cdf00 scripts: Add C910 to platform list in the binary archive script
0492c5d include: Typo fix in comment for SBI_SCRATCH_SIZE define
046cc16 lib: Move struct sbi_ipi_data definition to sbi_ipi.c
3d2aaac lib: Introduce sbi_ipi_send_smode() API
da9b76b lib: Introduce sbi_ipi_send_halt() API
a8b4b83 lib: Introduce sbi_tlb_fifo_request() API
5f762d1 lib: Introduce sbi_ipi_event_create/destroy() APIs
817d50d lib: Drop _fifo from the name of various sbi_tlb_fifo_xyz() functions
84cd4fc lib: Initialize TLB management directly from coldboot/warmboot path
0a411bf include: Add generic and simple list handling APIs
37923c4 lib: Add dynamic registration of SBI extensions
7668502 lib: Factor-out SBI legacy extension
161b348 lib: Factor-out SBI replacement extensions
43ac621 lib: Factor-out SBI vendor extension
021b9e7 lib: Factor-out SBI base extension
85647a1 platform: template: typo fix in system reboot/shutdown names
ac1c229 platform: Update UART base addresses for qemu/sifve_u
d79173b platform: Add an platform ops to return platform specific tlb flush 
2c2bbe7 platform: sifive/fu540: Set tlb range flush limit to zero
5ff1ab0 makefile: add support for building on macOS
6d0b4c5 platform: Drop qemu/sifive_u support
9a717ec platform: sifive: fu540: Add platform specific 'make run' cmd
d6fa7f9 doc: sifive: fu540: Update QEMU instruction when using U-Boot as the 
179edde lib: sbi_scratch: use bitwise ops in sbi_scratch_alloc_offset()
897b8fb lib: Use __builtin_ctzl() in pmp_get()
1a8ca08 lib: Initialize out value in SBI calls
c2bfa2b lib: irqchip/plic: Disable all contexts and IRQs
c2f23cc platform: Add Spike initial support
a062200 platform: Remove stale options from config.mk files
c03c8a1 scripts: Add Spike to platform list of binary archive script
29bb2a6 docs: platform: Add documentation for Spike platform
48b06ad ThirdPartyNotices: Fix doc styles
892e879 doc: coreboot: Fix doc styles
fdfb533 doc: payload_linux: Fix doc styles
44d1296 doc: andes-ae350: Fix doc styles
a8ef0b5 doc: ariane-fpga: Fix doc styles
82fd42f doc: qemu_virt: Fix doc styles
f8ce996 doc: sifive_fu540: Fix doc styles
27a5c7f doc: thead-c910: Fix doc styles
0b41453 Revert "lib: Use __builtin_ctzl() in pmp_get()"
c66543d lib: utils: htif: Fix 32-bit build
bc874e3 lib: Don't check MIDELEG and MEDELEG at end of delegate_traps()
24c3082 lib: Print interrupt and exception delegation in boot prints
66fb729 platform: sifive: fu540: Add 32-bit specific fdt/payload addresses
3e7d666 platform: qemu: virt: Correct the typo in config.mk
c3b3b8f lib: Fix typo in atomic exchange functions
3936243 lib: Use available hart mask for correct hbase value
f8b3bb8 lib: Simplify the for-loop in sbi_ipi_send_many()
ac5e821 include: Bump-up version to 0.6

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: a6fcc80bea1f062ffad330a1dcbc1e3d463a4493
  Author: Bin Meng <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M Makefile
    A pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    M roms/Makefile

  Log Message:
  roms: opensbi: Add 32-bit firmware image for sifive_u machine

Although the real world SiFive HiFive Unleashed board is a 64-bit
hardware configuration, with QEMU it is possible to test 32-bit
configuration with the same hardware features.

This updates the roms Makefile to add the build rules for creating
the 32-bit OpenSBI firmware image for sifive_u machine. A pre-built
OpenSBI v0.6 image has been added as the default bios for 32-bit
sifive_u machine.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: b78c3296314b5bbb5f837e9b1dee7b8dde25573b
  Author: Bin Meng <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  riscv: sifive_u: Update BIOS_FILENAME for 32-bit

Update BIOS_FILENAME to consider 32-bit bios image file name.

Tested booting Linux v5.5 32-bit image (built from rv32_defconfig
plus CONFIG_SOC_SIFIVE) with the default 32-bit bios image.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: c6fc0fc1a71a0cb09b472cf36dded3c52bd77880
  Author: Bin Meng <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    A .gitlab-ci-opensbi.yml
    A .gitlab-ci.d/opensbi/Dockerfile
    M .gitlab-ci.yml

  Log Message:
  gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries

Add two GitLab jobs to build the OpenSBI firmware binaries.

The first job builds a Docker image with the packages requisite
to build OpenSBI, and stores this image in the GitLab registry.
The second job pulls the image from the registry and builds the
OpenSBI firmware binaries.

The docker image is only rebuilt if the GitLab YAML or the
Dockerfile is updated. The second job is only built when the
roms/opensbi/ submodule is updated, when a git-ref starts with
'opensbi' or when the last commit contains 'OpenSBI'. The files
generated are archived in the artifacts.zip file.

With OpenSBI v0.6, it took 2 minutes 56 seconds to build
the docker image, and 1 minute 24 seconds to generate the
artifacts.zip with the firmware binaries (filesize: 111KiB).

See: https://gitlab.com/lbmeng/qemu/pipelines/120520138

Suggested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: c5969a3a3c2cb9ea02ffb7e86acb059d3cf8c264
  Author: Rajnesh Kanwal <address@hidden>
  Date:   2020-03-16 (Mon, 16 Mar 2020)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  target/riscv: Fix VS mode interrupts forwarding.

Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.

Signed-off-by: Rajnesh Kanwal <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>

  Commit: 3189e9d38c82266ea5750a81255fd229c7ddf1e6
  Author: Peter Maydell <address@hidden>
  Date:   2020-03-17 (Tue, 17 Mar 2020)

  Changed paths:
    A .gitlab-ci-opensbi.yml
    A .gitlab-ci.d/opensbi/Dockerfile
    M .gitlab-ci.yml
    M Makefile
    M hw/riscv/sifive_u.c
    A pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv32-virt-fw_jump.bin
    M pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
    M pc-bios/opensbi-riscv64-virt-fw_jump.bin
    M roms/Makefile
    M roms/opensbi
    M target/riscv/cpu_helper.c
    M target/riscv/op_helper.c

  Log Message:
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf5' 
into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 5

This tag contains the last of the patches I'd like to target for the 5.0 soft
freeze.  At this point we're mostly collecting fixes, but there are a few new
features.  The changes include:

* An OpenSBI update, including the various bits necessary to put CI together
  and an image for the 32-bit sifive_u board.
* A fix that disallows TSR when outside of machine mode.
* A fix for VS-mode interrupt forwarding.

# gpg: Signature made Tue 17 Mar 2020 03:59:58 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf5:
  target/riscv: Fix VS mode interrupts forwarding.
  gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries
  riscv: sifive_u: Update BIOS_FILENAME for 32-bit
  roms: opensbi: Add 32-bit firmware image for sifive_u machine
  roms: opensbi: Upgrade from v0.5 to v0.6
  target/riscv: Correctly implement TSR trap

Signed-off-by: Peter Maydell <address@hidden>

Compare: https://github.com/qemu/qemu/compare/a98135f72759...3189e9d38c82

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