[Qemu-commits] [qemu/qemu] f48996: hw/arm/aspeed: Remove extraneous Memo

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[Qemu-commits] [qemu/qemu] f48996: hw/arm/aspeed: Remove extraneous Memo

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] f48996: hw/arm/aspeed: Remove extraneous MemoryRegion obje...
Date:	Fri, 26 Jun 2020 12:00:31 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f489960d36c49e91cf57c185b70cd028aa4976e7
      
https://github.com/qemu/qemu/commit/f489960d36c49e91cf57c185b70cd028aa4976e7
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: Remove extraneous MemoryRegion object owner

I'm confused by this code, 'bmc' is created as:

  bmc = g_new0(AspeedBoardState, 1);

Then we use it as QOM owner for different MemoryRegion objects.
But looking at memory_region_init_ram (similarly for ROM):

  void memory_region_init_ram(MemoryRegion *mr,
                              struct Object *owner,
                              const char *name,
                              uint64_t size,
                              Error **errp)
  {
      DeviceState *owner_dev;
      Error *err = NULL;

      memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
      if (err) {
          error_propagate(errp, err);
          return;
      }
      /* This will assert if owner is neither NULL nor a DeviceState.
       * We only want the owner here for the purposes of defining a
       * unique name for migration. TODO: Ideally we should implement
       * a naming scheme for Objects which are not DeviceStates, in
       * which case we can relax this restriction.
       */
      owner_dev = DEVICE(owner);
      vmstate_register_ram(mr, owner_dev);
  }

The expected assertion is not triggered ('bmc' is not NULL neither
a DeviceState).

'bmc' structure is defined as:

  struct AspeedBoardState {
      AspeedSoCState soc;
      MemoryRegion ram_container;
      MemoryRegion max_ram;
  };

What happens is when using 'OBJECT(bmc)', the QOM macros cast the
memory pointed by bmc, which first member is 'soc', which is
initialized ...:

  object_initialize_child(OBJECT(machine), "soc",
                          &bmc->soc, amc->soc_name);

The 'soc' object is indeed a DeviceState, so the assertion passes.

Since this is fragile and only happens to work by luck, remove the
dangerous OBJECT(bmc) owner argument.

Note, this probably breaks migration for this machine.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200623072132.2868-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 612b219a2a6e3d8192ce1d2408780be655f60359
      
https://github.com/qemu/qemu/commit/612b219a2a6e3d8192ce1d2408780be655f60359
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/aspeed.c
    M include/hw/arm/aspeed.h

  Log Message:
  -----------
  hw/arm/aspeed: Rename AspeedBoardState as AspeedMachineState

To have a more consistent naming, rename AspeedBoardState
as AspeedMachineState.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072132.2868-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 888b2b034a29fa8fe99417c9665e0d671a9f33fb
      
https://github.com/qemu/qemu/commit/888b2b034a29fa8fe99417c9665e0d671a9f33fb
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/aspeed.c
    M include/hw/arm/aspeed.h

  Log Message:
  -----------
  hw/arm/aspeed: QOM'ify AspeedMachineState

AspeedMachineState seems crippled. We use incorrectly 2
different structures to do the same thing. Merge them
altogether:
- Move AspeedMachine fields to AspeedMachineState
- AspeedMachineState is now QOM
- Remove unused AspeedMachine structure

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072132.2868-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d88c42ff2c5cdcaecd02e6b31ea4c134b02be084
      
https://github.com/qemu/qemu/commit/d88c42ff2c5cdcaecd02e6b31ea4c134b02be084
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/i2c/core.c
    M include/hw/i2c/i2c.h

  Log Message:
  -----------
  hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref()

Extract i2c_try_create_slave() and i2c_realize_and_unref()
from i2c_create_slave().
We can now set properties on a I2CSlave before it is realized.

This is in line with the recent qdev/QOM changes merged
in commit 6675a653d2e.

Reviewed-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8208335b9539e7b5aa4702b36e2f9a8abd704079
      
https://github.com/qemu/qemu/commit/8208335b9539e7b5aa4702b36e2f9a8abd704079
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M include/hw/misc/pca9552.h

  Log Message:
  -----------
  hw/misc/pca9552: Rename 'nr_leds' as 'pin_count'

The PCA9552 device does not expose LEDs, but simple pins
to connnect LEDs to. To be clearer with the device model,
rename 'nr_leds' as 'pin_count'.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ec17228a25e7fd46287842322f8dc4923eccca92
      
https://github.com/qemu/qemu/commit/ec17228a25e7fd46287842322f8dc4923eccca92
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M include/hw/misc/pca9552.h

  Log Message:
  -----------
  hw/misc/pca9552: Rename generic code as pca955x

Various code from the PCA9552 device model is generic to the
PCA955X family. We'll split the generic code in a base class
in the next commit. To ease review, first do a dumb renaming.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 736132e455eea08e37fe21b4140b8088f2c0956b
      
https://github.com/qemu/qemu/commit/736132e455eea08e37fe21b4140b8088f2c0956b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M include/hw/misc/pca9552.h

  Log Message:
  -----------
  hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552

Extract the code common to the PCA955x family in PCA955xClass,
keeping the PCA9552 specific parts into pca9552_class_init().
Remove the 'TODO' comment added in commit 5141d4158cf.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2df252d8793097386d4972640653da93f7857da1
      
https://github.com/qemu/qemu/commit/2df252d8793097386d4972640653da93f7857da1
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M include/hw/misc/pca9552.h

  Log Message:
  -----------
  hw/misc/pca9552: Add a 'description' property for debugging purpose

Add a description field to distinguish between multiple devices.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-6-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b989b89f672597cc0e780b5ce95e604d4f49247a
      
https://github.com/qemu/qemu/commit/b989b89f672597cc0e780b5ce95e604d4f49247a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M hw/misc/trace-events

  Log Message:
  -----------
  hw/misc/pca9552: Trace GPIO High/Low events

Add a trivial representation of the PCA9552 GPIOs.

Example booting obmc-phosphor-image:

  $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_status
  1592689902.327837:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[*...............]
  1592689902.329934:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[**..............]
  1592689902.330717:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[***.............]
  1592689902.331431:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****............]
  1592689902.332163:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........*..]
  1592689902.332888:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........**.]
  1592689902.333629:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........***]
  1592690032.793289:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........*.*]
  1592690033.303163:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........***]
  1592690033.812962:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........*.*]
  1592690034.323234:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........***]
  1592690034.832922:pca955x_gpio_status pca-unspecified GPIOs 0-15 
[****.........*.*]

We notice the GPIO #14 (front-power LED) starts to blink.

This LED is described in the witherspoon device-tree [*]:

  front-power {
      retain-state-shutdown;
      default-state = "keep";
      gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
  };

[*] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=b1f9be9392f0#n140

Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 15ce12cfdd3740d38a7ab19ad0f5c812ff649fed
      
https://github.com/qemu/qemu/commit/15ce12cfdd3740d38a7ab19ad0f5c812ff649fed
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  hw/arm/aspeed: Describe each PCA9552 device

We have 2 distinct PCA9552 devices. Set their description
to distinguish them when looking at the trace events.

Description name taken from:
https://github.com/open-power/witherspoon-xml/blob/master/witherspoon.xml

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d82ab2931d14c1d8aa27a330b03fe5bf944130cf
      
https://github.com/qemu/qemu/commit/d82ab2931d14c1d8aa27a330b03fe5bf944130cf
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M hw/misc/trace-events

  Log Message:
  -----------
  hw/misc/pca9552: Trace GPIO change events

Emit a trace event when a GPIO change its state.

Example booting obmc-phosphor-image:

  $ qemu-system-arm -M witherspoon-bmc -trace pca955x_gpio_change
  1592690552.687372:pca955x_gpio_change pca1 GPIO id:0 status: 0 -> 1
  1592690552.690169:pca955x_gpio_change pca1 GPIO id:1 status: 0 -> 1
  1592690552.691673:pca955x_gpio_change pca1 GPIO id:2 status: 0 -> 1
  1592690552.696886:pca955x_gpio_change pca1 GPIO id:3 status: 0 -> 1
  1592690552.698614:pca955x_gpio_change pca1 GPIO id:13 status: 0 -> 1
  1592690552.699833:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1
  1592690552.700842:pca955x_gpio_change pca1 GPIO id:15 status: 0 -> 1
  1592690683.841921:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0
  1592690683.861660:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1
  1592690684.371460:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0
  1592690684.882115:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1
  1592690685.391411:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0
  1592690685.901391:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1
  1592690686.411678:pca955x_gpio_change pca1 GPIO id:14 status: 1 -> 0
  1592690686.921279:pca955x_gpio_change pca1 GPIO id:14 status: 0 -> 1

We notice the GPIO #14 (front-power LED) starts to blink.

This LED is described in the witherspoon device-tree [*]:

  front-power {
      retain-state-shutdown;
      default-state = "keep";
      gpios = <&pca0 14 GPIO_ACTIVE_LOW>;
  };

[*] 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts?id=b1f9be9392f0#n140

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-9-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 586f495b1e78c27e141ff432dd971eb41866fb80
      
https://github.com/qemu/qemu/commit/586f495b1e78c27e141ff432dd971eb41866fb80
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/misc/pca9552.c
    M include/hw/misc/pca9552.h

  Log Message:
  -----------
  hw/misc/pca9552: Model qdev output GPIOs

The PCA9552 has 16 GPIOs which can be used as input,
output or PWM mode. QEMU models the output GPIO with
the qemu_irq type. Let the device expose the 16 GPIOs
to allow us to later connect LEDs to these outputs.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20200623072723.6324-10-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c7fd0baac0c24defec66263799faa8618327b352
      
https://github.com/qemu/qemu/commit/c7fd0baac0c24defec66263799faa8618327b352
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add isar tests for mte

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 252e8c69669599b4bcff802df300726300292f47
      
https://github.com/qemu/qemu/commit/252e8c69669599b4bcff802df300726300292f47
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Improve masking of SCR RES0 bits

Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f00faf130d5dcf64b04f71a95f14745845ca1014
      
https://github.com/qemu/qemu/commit/f00faf130d5dcf64b04f71a95f14745845ca1014
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for MTE to SCTLR_ELx

This does not attempt to rectify all of the res0 bits, but does
clear the mte bits when not enabled.  Since there is no high-part
mapping of SCTLR, aa32 mode cannot write to these bits.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8ddb300bf60a5f3d358dd6fbf81174f6c03c1d9f
      
https://github.com/qemu/qemu/commit/8ddb300bf60a5f3d358dd6fbf81174f6c03c1d9f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for MTE to HCR_EL2 and SCR_EL3

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 14407ec2007e18536ed34772eef46f6e0a0e3d0e
      
https://github.com/qemu/qemu/commit/14407ec2007e18536ed34772eef46f6e0a0e3d0e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT

Emphasize that the is_jmp option exits to the main loop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 329833286d7a1b0ef8c7daafe13c6ae32429694e
      
https://github.com/qemu/qemu/commit/329833286d7a1b0ef8c7daafe13c6ae32429694e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add DISAS_UPDATE_NOCHAIN

Add an option that writes back the PC, like DISAS_UPDATE_EXIT,
but does not exit back to the main loop.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5
      
https://github.com/qemu/qemu/commit/4b779cebb3e5ab30b945181f1ba3932f5f8a1cb5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add MTE system registers

This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 81ae05fa2d21ac1a0054935b74342aa38a5ecef7
      
https://github.com/qemu/qemu/commit/81ae05fa2d21ac1a0054935b74342aa38a5ecef7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add MTE bits to tb_flags

Cache the composite ATA setting.

Cache when MTE is fully enabled, i.e. access to tags are enabled
and tag checks affect the PE.  Do this for both the normal context
and the UNPRIV context.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: da54941f45b820cbaca72aa6efd5669b3dc86e2f
      
https://github.com/qemu/qemu/commit/da54941f45b820cbaca72aa6efd5669b3dc86e2f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/helper-a64.h
    M target/arm/internals.h
    A target/arm/mte_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement the IRG instruction

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 21a8b343eaae63f6984f9a200092b0ea167647f1
      
https://github.com/qemu/qemu/commit/21a8b343eaae63f6984f9a200092b0ea167647f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Revise decoding for disas_add_sub_imm

The current Arm ARM has adjusted the official decode of
"Add/subtract (immediate)" so that the shift field is only bit 22,
and bit 23 is part of the op1 field of the parent category
"Data processing - immediate".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-11-richard.henderson@linaro.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: efbc78ad978763aedd11cb718eb1ff8db3fc9152
      
https://github.com/qemu/qemu/commit/efbc78ad978763aedd11cb718eb1ff8db3fc9152
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/internals.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement the ADDG, SUBG instructions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 438efea0bb639c9c2dfb42c8d9459e21aa183c8a
      
https://github.com/qemu/qemu/commit/438efea0bb639c9c2dfb42c8d9459e21aa183c8a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement the GMI instruction

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dad3015f55f8d48f84f0eae36021a9c6f9587e57
      
https://github.com/qemu/qemu/commit/dad3015f55f8d48f84f0eae36021a9c6f9587e57
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement the SUBP instruction

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0d1762e931f8a694f261c604daba605bcda70928
      
https://github.com/qemu/qemu/commit/0d1762e931f8a694f261c604daba605bcda70928
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/tlb_helper.c

  Log Message:
  -----------
  target/arm: Define arm_cpu_do_unaligned_access for user-only

Use the same code as system mode, so that we generate the same
exception + syndrome for the unaligned access.

For the moment, if MTE is enabled so that this path is reachable,
this would generate a SIGSEGV in the user-only cpu_loop.  Decoding
the syndrome to produce the proper SIGBUS will be done later.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c15294c1e36a7dd9b25bd54d98178e80f4b64bc1
      
https://github.com/qemu/qemu/commit/c15294c1e36a7dd9b25bd54d98178e80f4b64bc1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/helper.h
    M target/arm/mte_helper.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement LDG, STG, ST2G instructions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6439d67fc944cf29de94a160e9450a2063c7b515
      
https://github.com/qemu/qemu/commit/6439d67fc944cf29de94a160e9450a2063c7b515
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement the STGP instruction

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a4157b80242bf1c8aa0ee77aae7458ba79012d5d
      
https://github.com/qemu/qemu/commit/a4157b80242bf1c8aa0ee77aae7458ba79012d5d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Restrict the values of DCZID.BS under TCG

We can simplify our DC_ZVA if we recognize that the largest BS
that we actually use in system mode is 64.  Let us just assert
that it fits within TARGET_PAGE_SIZE.

For DC_GVA and STZGM, we want to be able to write whole bytes
of tag memory, so assert that BS is >= 2 * TAG_GRANULE, or 32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e26d0d226892f67435cadcce86df0ddfb9943174
      
https://github.com/qemu/qemu/commit/e26d0d226892f67435cadcce86df0ddfb9943174
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.c

  Log Message:
  -----------
  target/arm: Simplify DC_ZVA

Now that we know that the operation is on a single page,
we need not loop over pages while probing.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5f716a82388eb09754dd900e7dbb8ffa15897a28
      
https://github.com/qemu/qemu/commit/5f716a82388eb09754dd900e7dbb8ffa15897a28
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Implement the LDGM, STGM, STZGM instructions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5463df160ecee510e78493993eb1bd38b4838a10
      
https://github.com/qemu/qemu/commit/5463df160ecee510e78493993eb1bd38b4838a10
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement the access tag cache flushes

Like the regular data cache flushes, these are nops within qemu.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9c7ab8fc8cb6d6e2fb7a82c1088691c7c23fa1b9
      
https://github.com/qemu/qemu/commit/9c7ab8fc8cb6d6e2fb7a82c1088691c7c23fa1b9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Move regime_el to internals.h

We will shortly need this in mte_helper.c as well.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 38659d311d05e6c5feff6bddcc1c33b60d3b86a1
      
https://github.com/qemu/qemu/commit/38659d311d05e6c5feff6bddcc1c33b60d3b86a1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Move regime_tcr to internals.h

We will shortly need this in mte_helper.c as well.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0a405be2b8fd9506a009b10d7d2d98c394b36db6
      
https://github.com/qemu/qemu/commit/0a405be2b8fd9506a009b10d7d2d98c394b36db6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/internals.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h

  Log Message:
  -----------
  target/arm: Add gen_mte_check1

Replace existing uses of check_data_tbi in translate-a64.c that
perform a single logical memory access.  Leave the helper blank
for now to reduce the patch size.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 73ceeb0011b23bac8bd2c09ebe3c18d034aa69ce
      
https://github.com/qemu/qemu/commit/73ceeb0011b23bac8bd2c09ebe3c18d034aa69ce
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h

  Log Message:
  -----------
  target/arm: Add gen_mte_checkN

Replace existing uses of check_data_tbi in translate-a64.c that
perform multiple logical memory access.  Leave the helper blank
for now to reduce the patch size.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2e34ff45f32cb032883616a1cc5ea8ac96f546d5
      
https://github.com/qemu/qemu/commit/2e34ff45f32cb032883616a1cc5ea8ac96f546d5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/internals.h
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Implement helper_mte_check1

Fill out the stub that was added earlier.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5add8248556a3c1006018d7d8e601c9572b280a9
      
https://github.com/qemu/qemu/commit/5add8248556a3c1006018d7d8e601c9572b280a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/internals.h
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Implement helper_mte_checkN

Fill out the stub that was added earlier.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 46dc1bc0601554823a42ad27f236da2ad8f3bdc6
      
https://github.com/qemu/qemu/commit/46dc1bc0601554823a42ad27f236da2ad8f3bdc6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-a64.h
    M target/arm/mte_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add helper_mte_check_zva

Use a special helper for DC_ZVA, rather than the more
general mte_checkN.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b2aa8879b884cd66acde4123899dd92a38fe6527
      
https://github.com/qemu/qemu/commit/b2aa8879b884cd66acde4123899dd92a38fe6527
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use mte_checkN for sve unpredicated loads

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bba87d0a0f480805223a6428a7942a51733c488a
      
https://github.com/qemu/qemu/commit/bba87d0a0f480805223a6428a7942a51733c488a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use mte_checkN for sve unpredicated stores

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4ac430e1f1eb1d27913a9f800a5965b281ac1b76
      
https://github.com/qemu/qemu/commit/4ac430e1f1eb1d27913a9f800a5965b281ac1b76
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use mte_check1 for sve LD1R

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c0ed9166b1aea86a2fbaada1195aacd1049f9e85
      
https://github.com/qemu/qemu/commit/c0ed9166b1aea86a2fbaada1195aacd1049f9e85
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Tidy trans_LD1R_zpri

Move the variable declarations to the top of the function,
but do not create a new label before sve_access_check.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d
      
https://github.com/qemu/qemu/commit/149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add arm_tlb_bti_gp

Introduce an lvalue macro to wrap target_tlb_bit0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 206adacfb8d35e671e3619591608c475aa046b63
      
https://github.com/qemu/qemu/commit/206adacfb8d35e671e3619591608c475aa046b63
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper-sve.h
    M target/arm/internals.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Add mte helpers for sve scalar + int loads

Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 71b9f3948c75bb97641a3c8c7de96d1cb47cdc07
      
https://github.com/qemu/qemu/commit/71b9f3948c75bb97641a3c8c7de96d1cb47cdc07
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Add mte helpers for sve scalar + int stores

Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: aa13f7c3c378fa41366b9fcd6c29af1c3d81126a
      
https://github.com/qemu/qemu/commit/aa13f7c3c378fa41366b9fcd6c29af1c3d81126a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Add mte helpers for sve scalar + int ff/nf loads

Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9473d0ecafcffc8b258892b1f9f18e037bdba958
      
https://github.com/qemu/qemu/commit/9473d0ecafcffc8b258892b1f9f18e037bdba958
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Handle TBI for sve scalar + int memory ops

We still need to handle tbi for user-only when mte is inactive.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d28d12f008ee44dc2cc2ee5d8f673be9febc951e
      
https://github.com/qemu/qemu/commit/d28d12f008ee44dc2cc2ee5d8f673be9febc951e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Add mte helpers for sve scatter/gather memory ops

Because the elements are non-sequential, we cannot eliminate many
tests straight away like we can for sequential operations.  But
we often have the PTE details handy, so we can test for Tagged.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c4af8ba19b9d22aac79cab679a20b159af9d6809
      
https://github.com/qemu/qemu/commit/c4af8ba19b9d22aac79cab679a20b159af9d6809
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Complete TBI clearing for user-only for SVE

There are a number of paths by which the TBI is still intact
for user-only in the SVE helpers.

Because we currently always set TBI for user-only, we do not
need to pass down the actual TBI setting from above, and we
can remove the top byte in the inner-most primitives, so that
none are forgotten.  Moreover, this keeps the "dirty" pointer
around at the higher levels, where we need it for any MTE checking.

Since the normal case, especially for user-only, goes through
RAM, this clearing merely adds two insns per page lookup, which
will be completely in the noise.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: eb821168db798302bd124a3b000cebc23bd0a395
      
https://github.com/qemu/qemu/commit/eb821168db798302bd124a3b000cebc23bd0a395
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement data cache set allocation tags

This is DC GVA and DC GZVA, and the tag check for DC ZVA.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 34669338bd9d66255fceaa84c314251ca49ca8d5
      
https://github.com/qemu/qemu/commit/34669338bd9d66255fceaa84c314251ca49ca8d5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Set PSTATE.TCO on exception entry

D1.10 specifies that exception handlers begin with tag checks overridden.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7e98e21c09871cddc20946c8f3f3595e93154ecb
      
https://github.com/qemu/qemu/commit/7e98e21c09871cddc20946c8f3f3595e93154ecb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/m_helper.c
    M target/arm/tlb_helper.c

  Log Message:
  -----------
  target/arm: Always pass cacheattr to get_phys_addr

We need to check the memattr of a page in order to determine
whether it is Tagged for MTE.  Between Stage1 and Stage2,
this becomes simpler if we always collect this data, instead
of occasionally being presented with NULL.

Use the nonnull attribute to allow the compiler to check that
all pointer arguments are non-null.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 337a03f07ff0f9e6295662f4094e03a045b60bdc
      
https://github.com/qemu/qemu/commit/337a03f07ff0f9e6295662f4094e03a045b60bdc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/helper.c
    M target/arm/tlb_helper.c

  Log Message:
  -----------
  target/arm: Cache the Tagged bit for a page in MemTxAttrs

This "bit" is a particular value of the page's MemAttr.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8bce44a2f6beb388a3f157652b46e99929839a96
      
https://github.com/qemu/qemu/commit/8bce44a2f6beb388a3f157652b46e99929839a96
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Create tagged ram when MTE is enabled

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200626033144.790098-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e4d5bf4fbd5abfc3727e711eda64a583cab4d637
      
https://github.com/qemu/qemu/commit/e4d5bf4fbd5abfc3727e711eda64a583cab4d637
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Add allocation tag storage for system mode

Look up the physical address for the given virtual address,
convert that to a tag physical address, and finally return
the host address that backs it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-45-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c7459633baa71d1781fde4a245d6ec9ce2f008cf
      
https://github.com/qemu/qemu/commit/c7459633baa71d1781fde4a245d6ec9ce2f008cf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable MTE

We now implement all of the components of MTE, without actually
supporting any tagged memory.  All MTE instructions will work,
trivially, so we can enable support.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 553cf5d7c47bee05a3dec9461c1f8430316d516b
      
https://github.com/qemu/qemu/commit/553cf5d7c47bee05a3dec9461c1f8430316d516b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2020-06-26 (Fri, 26 Jun 2020)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/virt.c
    M hw/i2c/core.c
    M hw/misc/pca9552.c
    M hw/misc/trace-events
    M include/hw/arm/aspeed.h
    M include/hw/i2c/i2c.h
    M include/hw/misc/pca9552.h
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper-sve.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/m_helper.c
    A target/arm/mte_helper.c
    M target/arm/op_helper.c
    M target/arm/sve_helper.c
    M target/arm/tlb_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate-vfp.inc.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200626' 
into staging

target-arm queue:
 * hw/arm/aspeed: improve QOM usage
 * hw/misc/pca9552: trace GPIO change events
 * target/arm: Implement ARMv8.5-MemTag for system emulation

# gpg: Signature made Fri 26 Jun 2020 16:13:27 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200626: (57 commits)
  target/arm: Enable MTE
  target/arm: Add allocation tag storage for system mode
  target/arm: Create tagged ram when MTE is enabled
  target/arm: Cache the Tagged bit for a page in MemTxAttrs
  target/arm: Always pass cacheattr to get_phys_addr
  target/arm: Set PSTATE.TCO on exception entry
  target/arm: Implement data cache set allocation tags
  target/arm: Complete TBI clearing for user-only for SVE
  target/arm: Add mte helpers for sve scatter/gather memory ops
  target/arm: Handle TBI for sve scalar + int memory ops
  target/arm: Add mte helpers for sve scalar + int ff/nf loads
  target/arm: Add mte helpers for sve scalar + int stores
  target/arm: Add mte helpers for sve scalar + int loads
  target/arm: Add arm_tlb_bti_gp
  target/arm: Tidy trans_LD1R_zpri
  target/arm: Use mte_check1 for sve LD1R
  target/arm: Use mte_checkN for sve unpredicated stores
  target/arm: Use mte_checkN for sve unpredicated loads
  target/arm: Add helper_mte_check_zva
  target/arm: Implement helper_mte_checkN
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/3591ddd39987...553cf5d7c47b
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