[Qemu-commits] [qemu/qemu] 9be02c: target/riscv: Remove privilege v1.9 s

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[Qemu-commits] [qemu/qemu] 9be02c: target/riscv: Remove privilege v1.9 s

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 9be02c: target/riscv: Remove privilege v1.9 specific CSR r...
Date:	Wed, 05 May 2021 11:08:46 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 9be02c4a863ec42a01e48570fc2cef1135271659
      
https://github.com/qemu/qemu/commit/9be02c4a863ec42a01e48570fc2cef1135271659
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove privilege v1.9 specific CSR related code

Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
 - Rebase on latest patches
 - Bump the vmstate_riscv_cpu version_id and minimum_version_id
 ]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ef473442070be46d0b2dabbed7a6a86042508bad
      
https://github.com/qemu/qemu/commit/ef473442070be46d0b2dabbed7a6a86042508bad
  Author: Axel Heider <axelheider@gmx.de>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M docs/system/generic-loader.rst

  Log Message:
  -----------
  docs/system/generic-loader.rst: Fix style

Fix style to have a proper description of the parameter 'force-raw'.

Signed-off-by: Axel Heider <axelheider@gmx.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1dcd9496011aa393c28010bfadad4500082f9003
      
https://github.com/qemu/qemu/commit/1dcd9496011aa393c28010bfadad4500082f9003
  Author: Dylan Jhong <dylan@andestech.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Align the data type of reset vector address

Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ffcd4e535e22fb614106ff454a51695c5ab5209c
      
https://github.com/qemu/qemu/commit/ffcd4e535e22fb614106ff454a51695c5ab5209c
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

This was accidentally dropped before. Add it back.

Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b4ec1523a5ab7acd75e8e7e74232847279c4c499
      
https://github.com/qemu/qemu/commit/b4ec1523a5ab7acd75e8e7e74232847279c4c499
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add Shakti C class CPU

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0291a2f34e770f8702855b767d53cf31bd537d0d
      
https://github.com/qemu/qemu/commit/0291a2f34e770f8702855b767d53cf31bd537d0d
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M MAINTAINERS
    M default-configs/devices/riscv64-softmmu.mak
    M hw/riscv/Kconfig
    M hw/riscv/meson.build
    A hw/riscv/shakti_c.c
    A include/hw/riscv/shakti_c.h

  Log Message:
  -----------
  riscv: Add initial support for Shakti C machine

Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.

https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1f6e390282bc814e925dff5980072b4be6108477
      
https://github.com/qemu/qemu/commit/1f6e390282bc814e925dff5980072b4be6108477
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M MAINTAINERS
    M hw/char/meson.build
    A hw/char/shakti_uart.c
    M hw/char/trace-events
    A include/hw/char/shakti_uart.h

  Log Message:
  -----------
  hw/char: Add Shakti UART emulation

This is the initial implementation of Shakti UART.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-4-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f00741631300b2b3830372ed6e669c1966631d26
      
https://github.com/qemu/qemu/commit/f00741631300b2b3830372ed6e669c1966631d26
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M hw/riscv/shakti_c.c
    M include/hw/riscv/shakti_c.h

  Log Message:
  -----------
  hw/riscv: Connect Shakti UART to Shakti platform

Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 68a5cb8446df60c63f67d8edd97ec26f284c6f67
      
https://github.com/qemu/qemu/commit/68a5cb8446df60c63f67d8edd97ec26f284c6f67
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Convert the RISC-V exceptions to an enum

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com


  Commit: 042ef92b751cc30d6607c441950bed1445654dcd
      
https://github.com/qemu/qemu/commit/042ef92b751cc30d6607c441950bed1445654dcd
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Use the RISCVException enum for CSR predicates

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com


  Commit: e814d4b642e01d79b17d6ea71a7f7962900588d8
      
https://github.com/qemu/qemu/commit/e814d4b642e01d79b17d6ea71a7f7962900588d8
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix 32-bit HS mode access permissions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com


  Commit: 80341e20e680dc98fdfdeb9c4e06320501343783
      
https://github.com/qemu/qemu/commit/80341e20e680dc98fdfdeb9c4e06320501343783
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Use the RISCVException enum for CSR operations

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com


  Commit: da57b5294073dd3f8efdccdf73fbb9cf3934b268
      
https://github.com/qemu/qemu/commit/da57b5294073dd3f8efdccdf73fbb9cf3934b268
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Use RISCVException enum for CSR access

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com


  Commit: 2046187673fee9b28af7ce78a42215b1ad3194fd
      
https://github.com/qemu/qemu/commit/2046187673fee9b28af7ce78a42215b1ad3194fd
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update the RISC-V CPU Maintainers

Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.

Also add Bin who has been helping with reviews.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 
6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com


  Commit: e2e4c765938c3ac94980e6170e40b6a052a7df26
      
https://github.com/qemu/qemu/commit/e2e4c765938c3ac94980e6170e40b6a052a7df26
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M hw/intc/ibex_plic.c
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/opentitan: Update the interrupt layout

Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com


  Commit: 5cce7533e1e7a40e5b6d7773c759654269e272f7
      
https://github.com/qemu/qemu/commit/5cce7533e1e7a40e5b6d7773c759654269e272f7
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine

imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:

qemu-system-riscv64: Virtio VGA not available

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com


  Commit: ed5298c1a7162d921d22ce8071a5b5dc10d842ed
      
https://github.com/qemu/qemu/commit/ed5298c1a7162d921d22ce8071a5b5dc10d842ed
  Author: Jade Fink <qemu@jade.fyi>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: don't look at SUM when accessing memory from a debugger context

Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.

Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 00eb7fac053db30857a2fce9d89ce86bcdbe1c8e
      
https://github.com/qemu/qemu/commit/00eb7fac053db30857a2fce9d89ce86bcdbe1c8e
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Fixup saturate subtract function

The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8c7c8cde1250fc53906902b9c86ab9ea7a39a855
      
https://github.com/qemu/qemu/commit/8c7c8cde1250fc53906902b9c86ab9ea7a39a855
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    A docs/system/riscv/shakti-c.rst

  Log Message:
  -----------
  docs: Add documentation for shakti_c machine

Add documentation for Shakti C reference platform.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ab6d4f18dc3098f3719ef6833b54a0b9b9b4bfde
      
https://github.com/qemu/qemu/commit/ab6d4f18dc3098f3719ef6833b54a0b9b9b4bfde
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Fix the PMP is locked check when using TOR

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com


  Commit: 494e64a5459be75bc31f1020b780ff47359a08da
      
https://github.com/qemu/qemu/commit/494e64a5459be75bc31f1020b780ff47359a08da
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Define ePMP mseccfg

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: 213f080bbc84a8efaf80f8448e969c2641287398
      
https://github.com/qemu/qemu/commit/213f080bbc84a8efaf80f8448e969c2641287398
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add the ePMP feature

The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com


  Commit: c5e6fb3e4884e8f896cde3b928e47d1e570d6053
      
https://github.com/qemu/qemu/commit/c5e6fb3e4884e8f896cde3b928e47d1e570d6053
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/trace-events

  Log Message:
  -----------
  target/riscv: Add ePMP CSR access functions

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Fix build errors
 - Fix some style issues
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: c2d8003ba3c6c19f928e43ca1dc67147293c141e
      
https://github.com/qemu/qemu/commit/c2d8003ba3c6c19f928e43ca1dc67147293c141e
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Implementation of enhanced PMP (ePMP)

This commit adds support for ePMP v0.9.1.

The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Update to latest spec
 - Use a switch case to handle ePMP MML permissions
 - Fix a few bugs
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c1e624249d5242445570a40c4e6bb6952bdffb8d
      
https://github.com/qemu/qemu/commit/c1e624249d5242445570a40c4e6bb6952bdffb8d
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a config option for ePMP

Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: eddf6fdd43140f71a1898cc5cfd36caa49c765d6
      
https://github.com/qemu/qemu/commit/eddf6fdd43140f71a1898cc5cfd36caa49c765d6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp: Remove outdated comment

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com


  Commit: 3be4ea96d3024edb68ed87a52d30841f639413d4
      
https://github.com/qemu/qemu/commit/3be4ea96d3024edb68ed87a52d30841f639413d4
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Add ePMP support for the Ibex CPU

The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com


  Commit: 97c6776a75c92f553673c29b395d1c2c07f4c73f
      
https://github.com/qemu/qemu/commit/97c6776a75c92f553673c29b395d1c2c07f4c73f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: fix vrgather macro index variable type bug

ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f6551d7e31c31fef8584afcb1750c6709164ab9b
      
https://github.com/qemu/qemu/commit/f6551d7e31c31fef8584afcb1750c6709164ab9b
  Author: Emmanuel Blot <emmanuel.blot@sifive.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: fix exception index on instruction access fault

When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 26c6a14da04a615c6f51bb5cbbd5b9d6ba6ec412
      
https://github.com/qemu/qemu/commit/26c6a14da04a615c6f51bb5cbbd5b9d6ba6ec412
  Author: Alexander Wagner <alexander.wagner@ulal.de>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: Fix OT IBEX reset vector

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] 
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 34d0cb3a0f1375d325f4217b82a423b6433b233f
      
https://github.com/qemu/qemu/commit/34d0cb3a0f1375d325f4217b82a423b6433b233f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M fpu/softfloat-specialize.c.inc

  Log Message:
  -----------
  fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 21be64abd94df16d4490c7a5fe3fc9038d2e1e53
      
https://github.com/qemu/qemu/commit/21be64abd94df16d4490c7a5fe3fc9038d2e1e53
  Author: Emmanuel Blot <emmanuel.blot@sifive.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: fix a typo with interrupt names

Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7aaf6b3805940539461dd397a605a6684a02527a
      
https://github.com/qemu/qemu/commit/7aaf6b3805940539461dd397a605a6684a02527a
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Remove the hardcoded RVXLEN macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com


  Commit: 49d3904e4937495bb2c0a8fc176ef18de210d65b
      
https://github.com/qemu/qemu/commit/49d3904e4937495bb2c0a8fc176ef18de210d65b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded SSTATUS_SD macro

This also ensures that the SD bit is not writable.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com


  Commit: 16ad6fc093f7f2903f4cf62b5d4480222e391af2
      
https://github.com/qemu/qemu/commit/16ad6fc093f7f2903f4cf62b5d4480222e391af2
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded HGATP_MODE macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com


  Commit: 0c0fec56bee0298e82fa2427456a65f345326473
      
https://github.com/qemu/qemu/commit/0c0fec56bee0298e82fa2427456a65f345326473
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded MSTATUS_SD macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com


  Commit: 7af1cf733a0e80239d18bb9661309b66f1fcd06b
      
https://github.com/qemu/qemu/commit/7af1cf733a0e80239d18bb9661309b66f1fcd06b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/monitor.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded SATP_MODE macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com


  Commit: 5d04ea49660a80bde3d9879b21b90524580cbb7b
      
https://github.com/qemu/qemu/commit/5d04ea49660a80bde3d9879b21b90524580cbb7b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Remove the unused HSTATUS_WPRI macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com


  Commit: a315daf902d8c23aed72a9a4e3880b028cfcda7b
      
https://github.com/qemu/qemu/commit/a315daf902d8c23aed72a9a4e3880b028cfcda7b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove an unused CASE_OP_32_64 macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com


  Commit: baa3b31522008b6a53c6332bbb7d5bb3fd594016
      
https://github.com/qemu/qemu/commit/baa3b31522008b6a53c6332bbb7d5bb3fd594016
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    R target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/meson.build
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Consolidate RV32/64 32-bit instructions

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com


  Commit: 9d84ea6e7397bdd6d2b2277182f42dc9d81c15a9
      
https://github.com/qemu/qemu/commit/9d84ea6e7397bdd6d2b2277182f42dc9d81c15a9
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    R target/riscv/insn16-32.decode
    R target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/meson.build

  Log Message:
  -----------
  target/riscv: Consolidate RV32/64 16-bit instructions

This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com


  Commit: 7a98eab3a704139020bdad35bfae0356d2a31fa0
      
https://github.com/qemu/qemu/commit/7a98eab3a704139020bdad35bfae0356d2a31fa0
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: Fix the RV64H decode comment

BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com


  Commit: 8667cf18b08098f9450b150d21b147ae5924f0d3
      
https://github.com/qemu/qemu/commit/8667cf18b08098f9450b150d21b147ae5924f0d3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-05 (Wed, 05 May 2021)

  Changed paths:
    M MAINTAINERS
    M default-configs/devices/riscv64-softmmu.mak
    M docs/system/generic-loader.rst
    A docs/system/riscv/shakti-c.rst
    M fpu/softfloat-specialize.c.inc
    M hw/char/meson.build
    A hw/char/shakti_uart.c
    M hw/char/trace-events
    M hw/intc/ibex_plic.c
    M hw/riscv/Kconfig
    M hw/riscv/meson.build
    M hw/riscv/opentitan.c
    A hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    A include/hw/char/shakti_uart.h
    M include/hw/riscv/opentitan.h
    A include/hw/riscv/shakti_c.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/gdbstub.c
    M target/riscv/helper.h
    R target/riscv/insn16-32.decode
    R target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    R target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/monitor.c
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/trace-events
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210504-2' into staging

A large collection of RISC-V fixes, improvements and features

 - Clenaup some left over v1.9 code
 - Documentation improvements
 - Support for the shakti_c machine
 - Internal cleanup of the CSR accesses
 - Updates to the OpenTitan platform
 - Support for the virtio-vga
 - Fix for the saturate subtract in vector extensions
 - Experimental support for the ePMP spec
 - A range of other internal code cleanups and bug fixes

# gpg: Signature made Mon 03 May 2021 23:12:36 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210504-2: (42 commits)
  target/riscv: Fix the RV64H decode comment
  target/riscv: Consolidate RV32/64 16-bit instructions
  target/riscv: Consolidate RV32/64 32-bit instructions
  target/riscv: Remove an unused CASE_OP_32_64 macro
  target/riscv: Remove the unused HSTATUS_WPRI macro
  target/riscv: Remove the hardcoded SATP_MODE macro
  target/riscv: Remove the hardcoded MSTATUS_SD macro
  target/riscv: Remove the hardcoded HGATP_MODE macro
  target/riscv: Remove the hardcoded SSTATUS_SD macro
  target/riscv: Remove the hardcoded RVXLEN macro
  target/riscv: fix a typo with interrupt names
  fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
  hw/riscv: Fix OT IBEX reset vector
  target/riscv: fix exception index on instruction access fault
  target/riscv: fix vrgather macro index variable type bug
  target/riscv: Add ePMP support for the Ibex CPU
  target/riscv/pmp: Remove outdated comment
  target/riscv: Add a config option for ePMP
  target/riscv: Implementation of enhanced PMP (ePMP)
  target/riscv: Add ePMP CSR access functions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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