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[Qemu-commits] [qemu/qemu] 03b354: hw/ppc/mac_newworld: Restrict RAM to
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 03b354: hw/ppc/mac_newworld: Restrict RAM to 2 GiB |
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Date: |
Thu, 06 May 2021 10:55:45 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 03b3542ac93cb196bf6a6d85e92fa68a894f5256
https://github.com/qemu/qemu/commit/03b3542ac93cb196bf6a6d85e92fa68a894f5256
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/mac_newworld.c
Log Message:
-----------
hw/ppc/mac_newworld: Restrict RAM to 2 GiB
On Mac99 and newer machines, the Uninorth PCI host bridge maps
the PCI hole region at 2GiB, so the RAM area beside 2GiB is not
accessible by the CPU. Restrict the memory to 2GiB to avoid
problems such the one reported in the buglink.
Buglink: https://bugs.launchpad.net/qemu/+bug/1922391
Reported-by: Håvard Eidnes <he@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210406084842.2859664-1-f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 8a05fd9a22aa16d8a076a5dc9af2b5ed3658243c
https://github.com/qemu/qemu/commit/8a05fd9a22aa16d8a076a5dc9af2b5ed3658243c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
A target/ppc/helper_regs.c
M target/ppc/helper_regs.h
M target/ppc/int_helper.c
M target/ppc/meson.build
Log Message:
-----------
target/ppc: Move helper_regs.h functions out-of-line
Move the functions to a new file, helper_regs.c.
Note int_helper.c was relying on helper_regs.h to
indirectly include qemu/log.h.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-2-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 1828504672cece95f7b38e9e63eb2dfeeb447830
https://github.com/qemu/qemu/commit/1828504672cece95f7b38e9e63eb2dfeeb447830
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/misc_helper.c
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: Move 601 hflags adjustment to hreg_compute_hflags
Keep all hflags computation in one place, as this will be
especially important later.
Introduce a new POWERPC_FLAG_HID0_LE bit to indicate when
LE should be taken from HID0. This appears to be set if
and only if POWERPC_FLAG_RTC_CLK is set, but we're not
short of bits and having both names will avoid confusion.
Note that this was the only user of hflags_nmsr, so we can
perform a straight assignment rather than mask and set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-3-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: dafe299cf0249d2a83fd2d9262796a90c50fc1d3
https://github.com/qemu/qemu/commit/dafe299cf0249d2a83fd2d9262796a90c50fc1d3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Properly sync cpu state with new msr in cpu_load_old
Match cpu_post_load in using ppc_store_msr to set all of
the cpu state implied by the value of msr. Do not restore
hflags or hflags_nmsr, as we recompute them in ppc_store_msr.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-4-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: da77d2b03708c4b2a8cd32f689a6d65af243952d
https://github.com/qemu/qemu/commit/da77d2b03708c4b2a8cd32f689a6d65af243952d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Do not call hreg_compute_mem_idx after ppc_store_msr
In ppc_store_msr we call hreg_compute_hflags, which itself
calls hreg_compute_mem_idx. Rely on ppc_store_msr to update
everything required by the msr update.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-5-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f7a7b6525c5b5f06553582d8617052bf43678984
https://github.com/qemu/qemu/commit/f7a7b6525c5b5f06553582d8617052bf43678984
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Retain hflags_nmsr only for migration
We have eliminated all normal uses of hflags_nmsr. We need
not even compute it except when we want to migrate. Rename
the field to emphasize this.
Remove the fixme comment for migrating access_type. This value
is only ever used with the current executing instruction, and
is never live when the cpu is halted for migration.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-6-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 56ced49760df758650e852361b1b1a359ca6c904
https://github.com/qemu/qemu/commit/56ced49760df758650e852361b1b1a359ca6c904
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Fix comment for MSR_FE{0,1}
As per hreg_compute_hflags:
We 'forget' FE0 & FE1: we'll never generate imprecise exceptions
remove the hflags marker from the respective comments.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-7-richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: bd4160bc6adc2fd5484a9c1cee6df65e6f2f4508
https://github.com/qemu/qemu/commit/bd4160bc6adc2fd5484a9c1cee6df65e6f2f4508
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
hw/ppc/pnv_core: Update hflags after setting msr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-15-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: e81f17a3f616a4f2c803aafed60500ac45df9b3d
https://github.com/qemu/qemu/commit/e81f17a3f616a4f2c803aafed60500ac45df9b3d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_rtas.c
Log Message:
-----------
hw/ppc/spapr_rtas: Update hflags after setting msr
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210315184615.1985590-16-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: edece45d4ac2a12a7183d8fb1ddd7f7984910ab8
https://github.com/qemu/qemu/commit/edece45d4ac2a12a7183d8fb1ddd7f7984910ab8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/machine.c
Log Message:
-----------
target/ppc: Extract post_load_update_msr
Extract post_load_update_msr to share between cpu_load_old
and cpu_post_load in updating the msr.
Suggested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-2-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 2df4fe7abeed5be7c4350c12cfe33242261b28ef
https://github.com/qemu/qemu/commit/2df4fe7abeed5be7c4350c12cfe33242261b28ef
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Disconnect hflags from MSR
Copying flags directly from msr has drawbacks: (1) msr bits
mean different things per cpu, (2) msr has 64 bits on 64 cpus
while tb->flags has only 32 bits.
Create a enum to define these bits. Document the origin of each bit
and validate those bits that must match MSR. This fixes the
truncation of env->hflags to tb->flags, because we no longer
have hflags bits set above bit 31.
Most of the code in ppc_tr_init_disas_context is moved over to
hreg_compute_hflags. Some of it is simple extractions from msr,
some requires examining other cpu flags. Anything that is moved
becomes a simple extract from hflags in ppc_tr_init_disas_context.
Several existing bugs are left in ppc_tr_init_disas_context, where
additional changes are required -- to be addressed in future patches.
Remove a broken #if 0 block.
Reported-by: Ivan Warren <ivan@vmfacility.fr>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-3-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 26c55599b8c79887040c6910054a8c3f3f6f9147
https://github.com/qemu/qemu/commit/26c55599b8c79887040c6910054a8c3f3f6f9147
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Reduce env->hflags to uint32_t
It will be stored in tb->flags, which is also uint32_t,
so let's use the correct size.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-4-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 7da31f260d194d203c83712cfa7b2dfe605375fd
https://github.com/qemu/qemu/commit/7da31f260d194d203c83712cfa7b2dfe605375fd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/helper_regs.c
M target/ppc/misc_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Put dbcr0 single-step bits into hflags
Because these bits were not in hflags, the code generated
for single-stepping on BookE was essentially random.
Recompute hflags when storing to dbcr0.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-5-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f43520e5b233828bd4d98b4a1300ddb475e7486a
https://github.com/qemu/qemu/commit/f43520e5b233828bd4d98b4a1300ddb475e7486a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Create helper_scv
Perform the test against FSCR_SCV at runtime, in the helper.
This means we can remove the incorrect set against SCV in
ppc_tr_init_disas_context and do not need to add an HFLAGS bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-6-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f03de3b44b1053c3c82f41a22ae452d1ecfdd8c5
https://github.com/qemu/qemu/commit/f03de3b44b1053c3c82f41a22ae452d1ecfdd8c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Put LPCR[GTSE] in hflags
Because this bit was not in hflags, the privilege check
for tlb instructions was essentially random.
Recompute hflags when storing to LPCR.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-7-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 0e6bac3edb42b284aad329313e3a65c451af1d52
https://github.com/qemu/qemu/commit/0e6bac3edb42b284aad329313e3a65c451af1d52
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Remove MSR_SA and MSR_AP from hflags
Nothing within the translator -- or anywhere else for that
matter -- checks MSR_SA or MSR_AP on the 602. This may be
a mistake. However, for the moment, we need not record these
bits in hflags.
This allows us to simplify HFLAGS_VSX computation by moving
it to overlap with MSR_VSX.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-8-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: d764184ddb22a7a41a293e54c26cfe1717167a3f
https://github.com/qemu/qemu/commit/d764184ddb22a7a41a293e54c26cfe1717167a3f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
M target/ppc/helper_regs.h
M target/ppc/machine.c
M target/ppc/mem_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove env->immu_idx and env->dmmu_idx
We weren't recording MSR_GS in hflags, which means that BookE
memory accesses were essentially random vs Guest State.
Instead of adding this bit directly, record the completed mmu
indexes instead. This makes it obvious that we are recording
exactly the information that we need.
This also means that we can stop directly recording MSR_IR.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-9-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 75da499733696889453b3fda9ae0f0f5c28fcd6b
https://github.com/qemu/qemu/commit/75da499733696889453b3fda9ae0f0f5c28fcd6b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M linux-user/ppc/cpu_loop.c
M linux-user/ppc/signal.c
Log Message:
-----------
linux-user/ppc: Fix msr updates for signal handling
In save_user_regs, there are two bugs where we OR in a bit number
instead of the bit, clobbering the low bits of MSR. However:
The MSR_VR and MSR_SPE bits control the availability of the insns.
If the bits were not already set in MSR, then any attempt to access
those registers would result in SIGILL.
For linux-user, we always initialize MSR to the capabilities
of the cpu. We *could* add checks vs MSR where we currently
check insn_flags and insn_flags2, but we know they match.
Also, there's a stray cut-and-paste comment in restore.
Then, do not force little-endian binaries into big-endian mode.
Finally, use ppc_store_msr for the update to affect hflags.
Which is the reason none of these bugs were previously noticed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-10-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 2da8a6bcdca72c7a79a9c732133eaeb9452242cc
https://github.com/qemu/qemu/commit/2da8a6bcdca72c7a79a9c732133eaeb9452242cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Validate hflags with CONFIG_DEBUG_TCG
Verify that hflags was updated correctly whenever we change
cpu state that is used by hflags.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210323184340.619757-11-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f028c2ded2ccbd6a15493e6e0f292542d417b969
https://github.com/qemu/qemu/commit/f028c2ded2ccbd6a15493e6e0f292542d417b969
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
vt82c686: QOM-ify superio related functionality
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id:
<fbcc8cc8baf83f327612a1ef1c14bcbcdb0e7edb.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: ab74864fed2dcebe9a2ece659253e1bb2ead75ce
https://github.com/qemu/qemu/commit/ab74864fed2dcebe9a2ece659253e1bb2ead75ce
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Add VT8231_SUPERIO based on VIA_SUPERIO
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<8108809321f9ecf3fb1aea22ddaeccc7c3a57c8e.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 2e84e107a0309073d2427dc2c400d02a554afd9d
https://github.com/qemu/qemu/commit/2e84e107a0309073d2427dc2c400d02a554afd9d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/pci/pci_ids.h
Log Message:
-----------
vt82c686: Introduce abstract TYPE_VIA_ISA and base vt82c686b_isa on it
To allow reusing ISA bridge emulation for vt8231_isa move the device
state of vt82c686b_isa emulation in an abstract via_isa class. This
change breaks migration back compatibility but this is not an issue
for Fuloong2E machine which is not versioned or migration supported.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<0cb8fc69c7aaa555589181931b881335fecd2ef3.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f9f0c9e2faab18a44d9f60a8653688a8f841a909
https://github.com/qemu/qemu/commit/f9f0c9e2faab18a44d9f60a8653688a8f841a909
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
M include/hw/pci/pci_ids.h
Log Message:
-----------
vt82c686: Add emulation of VT8231 south bridge
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<10abc9f89854e7c980b9731c33d25a2e307e9c4f.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: dcdf98a90155545eeadb63edccd41b7ee5ce201d
https://github.com/qemu/qemu/commit/dcdf98a90155545eeadb63edccd41b7ee5ce201d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/pci-host/Kconfig
M hw/pci-host/meson.build
A hw/pci-host/mv64361.c
A hw/pci-host/mv643xx.h
M hw/pci-host/trace-events
A include/hw/pci-host/mv64361.h
M include/hw/pci/pci_ids.h
Log Message:
-----------
hw/pci-host: Add emulation of Marvell MV64361 PPC system controller
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
only fixing white space errors, removing not needed parts and changing
formatting for QEMU coding style.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<79545ebd03bfe0665b73d2d7cbc74fdf3d62629e.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: ba7e5ac18e7b3232ec93e0d3324bba167b965d70
https://github.com/qemu/qemu/commit/ba7e5ac18e7b3232ec93e0d3324bba167b965d70
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M MAINTAINERS
M default-configs/devices/ppc-softmmu.mak
M hw/ppc/Kconfig
M hw/ppc/meson.build
A hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc: Add emulation of Genesi/bPlan Pegasos II
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware ROM
image is needed to boot and only MorphOS has a video driver to produce
graphics output. Linux could work too but distros that supported this
machine don't include usual video drivers so those only run with
serial console for now.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<30cbfb9cbe6f46a1e15a69a75fac45ac39340122.1616680239.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 4b98e72d973f8612d3f65fd1dbcdd232a62bd6d6
https://github.com/qemu/qemu/commit/4b98e72d973f8612d3f65fd1dbcdd232a62bd6d6
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Rename RTAS_MAX_ADDR to FDT_MAX_ADDR
SLOF instantiates RTAS since
744a928ccee9 ("spapr: Stop providing RTAS blob")
so the max address applies to the FDT only.
This renames the macro and fixes up the comment.
This should not cause any behavioral change.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20210331025123.29310-1-aik@ozlabs.ru>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 53d7d7e2b164f97ae36bca3cb3b3cf1ba2abe4c0
https://github.com/qemu/qemu/commit/53d7d7e2b164f97ae36bca3cb3b3cf1ba2abe4c0
Author: Vaibhav Jain <vaibhav@linux.ibm.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_nvdimm.c
M include/hw/ppc/spapr.h
Log Message:
-----------
ppc/spapr: Add support for implement support for H_SCM_HEALTH
Add support for H_SCM_HEALTH hcall described at [1] for spapr
nvdimms. This enables guest to detect the 'unarmed' status of a
specific spapr nvdimm identified by its DRC and if its unarmed, mark
the region backed by the nvdimm as read-only.
The patch adds h_scm_health() to handle the H_SCM_HEALTH hcall which
returns two 64-bit bitmaps (health bitmap, health bitmap mask) derived
from 'struct nvdimm->unarmed' member.
Linux kernel side changes to enable handling of 'unarmed' nvdimms for
ppc64 are proposed at [2].
References:
[1] "Hypercall Op-codes (hcalls)"
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/powerpc/papr_hcalls.rst#n220
[2] "powerpc/papr_scm: Mark nvdimm as unarmed if needed during probe"
https://lore.kernel.org/linux-nvdimm/20210329113103.476760-1-vaibhav@linux.ibm.com/
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Message-Id: <20210402102128.213943-1-vaibhav@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 8c8a7ed50ca538f743810cda8d06010498ef1f62
https://github.com/qemu/qemu/commit/8c8a7ed50ca538f743810cda8d06010498ef1f62
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M roms/Makefile
Log Message:
-----------
roms/Makefile: Update ppce500 u-boot build directory name
Currently building ppce500 u-boot image results in
modified: roms/u-boot (untracked content)
As roms/u-boot/.gitignore indicates, update the build directory
name to build-e500 to eliminate this message.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 335b6389374a53e012382f4dd9338f9ab61ff902
https://github.com/qemu/qemu/commit/335b6389374a53e012382f4dd9338f9ab61ff902
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M pc-bios/u-boot.e500
M roms/u-boot
Log Message:
-----------
roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support
When QEMU originally supported the ppce500 machine back in Jan 2014,
it was created with a 1:1 mapping of PCI bus address. Things seemed
to change rapidly that in Nov 2014 with the following QEMU commits:
commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of
address space")
and
commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs")
the PCI memory and IO physical address were moved to beyond 4 GiB,
but PCI bus address remained below 4 GiB, hence a non-identity
mapping was created. Unfortunately corresponding U-Boot updates
were missed along with the QEMU changes and the U-Boot QEMU ppce500
PCI support has been broken since then, until this issue was fixed
recently in U-Boot mainline v2021.04 release, specifically by the
following U-Boot series:
http://patchwork.ozlabs.org/project/uboot/list/?series=230985&state=*
The cross-compilation toolchain used to build the U-Boot image is:
https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/10.1.0/x86_64-gcc-10.1.0-nolibc-powerpc-linux.tar.xz
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 37337472e77ee51f3d35b377684fd70368261c3d
https://github.com/qemu/qemu/commit/37337472e77ee51f3d35b377684fd70368261c3d
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
A docs/system/ppc/ppce500.rst
M docs/system/target-ppc.rst
Log Message:
-----------
docs/system: ppc: Add documentation for ppce500 machine
This adds detailed documentation for PowerPC `ppce500` machine,
including the following information:
- Supported devices
- Hardware configuration information
- Boot options
- Running Linux kernel
- Running U-Boot
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 9827f20863df9583efb8abfa89d8cb1a4eda4884
https://github.com/qemu/qemu/commit/9827f20863df9583efb8abfa89d8cb1a4eda4884
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour
ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
the LPCR[AIL] value can apply to hypervisor interrupts.
This affects machines that emulate HV=1 mode (i.e., powernv9).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210415054227.1793812-2-npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 98a6a3658805213a259b98687a84d37db8f43b01
https://github.com/qemu/qemu/commit/98a6a3658805213a259b98687a84d37db8f43b01
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: POWER10 supports scv
This must have slipped through the cracks between adding POWER10 support
and scv support.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210415054227.1793812-3-npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: a7913d5e3fb35572f9ff033e7c1c7f1af6f5f0f7
https://github.com/qemu/qemu/commit/a7913d5e3fb35572f9ff033e7c1c7f1af6f5f0f7
Author: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M include/hw/ppc/spapr.h
M target/ppc/cpu.h
M target/ppc/translate_init.c.inc
Log Message:
-----------
ppc: Rename current DAWR macros and variables
Power10 is introducing second DAWR. Use real register names (with
suffix 0) from ISA for current macros and variables used by Qemu.
One exception to this is KVM_REG_PPC_DAWR[X]. This is from kernel
uapi header and thus not changed in kernel as well as Qemu.
Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210412114433.129702-3-ravi.bangoria@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 5642e4513e60b46473422902d7cc34e894e8793d
https://github.com/qemu/qemu/commit/5642e4513e60b46473422902d7cc34e894e8793d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr.c: do not use MachineClass::max_cpus to limit CPUs
Up to this patch, 'max_cpus' value is hardcoded to 1024 (commit
6244bb7e5811). In theory this patch would simply bump it to 2048, since
it's the default NR_CPUS kernel setting for ppc64 servers nowadays, but
the whole mechanic of MachineClass:max_cpus is flawed for the pSeries
machine. The two supported accelerators, KVM and TCG, can live without
it.
TCG guests don't have a theoretical limit. The user must be free to
emulate as many CPUs as the hardware is capable of. And even if there
were a limit, max_cpus is not the proper way to report it since it's a
common value checked by SMP code in machine_smp_parse() for KVM as well.
For KVM guests, the proper way to limit KVM CPUs is by host
configuration via NR_CPUS, not a QEMU hardcoded value. There is no
technical reason for a pSeries QEMU guest to forcefully stay below
NR_CPUS.
This hardcoded value also disregard hosts that might have a lower
NR_CPUS limit, say 512. In this case, machine.c:machine_smp_parse() will
allow a 1024 value to pass, but then kvm_init() will complain about it
because it will exceed NR_CPUS:
Number of SMP cpus requested (1024) exceeds the maximum cpus supported
by KVM (512)
A better 'max_cpus' value would consider host settings, but
MachineClass::max_cpus is defined well before machine_init() and
kvm_init(). We can't check for KVM limits because it's too soon, so we
end up making a guess.
This patch makes MachineClass:max_cpus settings innocuous by setting it
to INT32_MAX. machine.c:machine_smp_parse() will not fail the
verification based on max_cpus, letting kvm_init() do the checking with
actual host settings. And TCG guests get to do whatever the hardware is
capable of emulating.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20210408204049.221802-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: b7573092ab6749bff4b50a7b291a74d1cbb42f57
https://github.com/qemu/qemu/commit/b7573092ab6749bff4b50a7b291a74d1cbb42f57
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr.h: increase FDT_MAX_SIZE
Certain SMP topologies stress, e.g. 1 thread/core, 2048 cores and
1 socket, stress the current maximum size of the pSeries FDT:
Calling ibm,client-architecture-support...qemu-system-ppc64: error
creating device tree: (fdt_setprop(fdt, offset,
"ibm,processor-segment-sizes", segs, sizeof(segs))): FDT_ERR_NOSPACE
2048 is the default NR_CPUS value for the pSeries kernel. It's expected
that users will want QEMU to be able to handle this kind of
configuration.
Bumping FDT_MAX_SIZE to 2MB is enough for these setups to be created.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20210408204049.221802-3-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 87758fed7a7a7c00c1bd0c965ae8b94e04ea9359
https://github.com/qemu/qemu/commit/87758fed7a7a7c00c1bd0c965ae8b94e04ea9359
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_drc.c
Log Message:
-----------
spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()
At this moment, PAPR does not provide a way to report errors during a
device removal operation. This led the pSeries machine to implement
extra mechanisms to try to fallback and recover from an error that might
have happened during the hotunplug in the guest side. This started to
change a bit with commit fe1831eff8a4 ("spapr_drc.c: use DRC
reconfiguration to cleanup DIMM unplug state"), where one way to
fallback from a memory removal error was introduced.
Around the same time, in [1], the idea of using RTAS set-indicator for
this role was first introduced. The RTAS set-indicator call, when
attempting to UNISOLATE a DRC that is already UNISOLATED or CONFIGURED,
returns RTAS_OK and does nothing else for both QEMU and phyp. This gives
us an opportunity to use this behavior to signal the hypervisor layer
when a device removal errir happens, allowing QEMU/phyp to do a proper
error handling. Using set-indicator to report HP errors isn't strange to
PAPR, as per R1-13.5.3.4-4. of table 13.7 of current PAPR [2]:
"For all DR options: If this is a DR operation that involves the user
insert- ing a DR entity, then if the firmware can determine that the
inserted entity would cause a system disturbance, then the set-indicator
RTAS call must not unisolate the entity and must return an error status
which is unique to the particular error."
A change was proposed to the pSeries Linux kernel to call set-indicator
to move a DRC to 'unisolate' in the case of a hotunplug error in the
guest side [3]. Setting a DRC that is already unisolated or configured to
'unisolate' is a no-op (returns RTAS_OK) for QEMU and also for phyp.
Being a benign change for hypervisors that doesn't care about handling
such errors, we expect the kernel to accept this change at some point.
This patch prepares the pSeries machine for this new kernel feature by
changing drc_unisolate_logical() to handle guest side hotunplug errors.
For CPUs it's a simple matter of setting drc->unplug_requested to 'false',
while for LMBs the process is similar to the rollback that is done in
rtas_ibm_configure_connector().
[1] https://lists.gnu.org/archive/html/qemu-devel/2021-02/msg06395.html
[2]
https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200611.pdf
[3]
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20210416210216.380291-3-danielhb413@gmail.com/
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20210420165100.108368-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 35a5d74e8248c09e66deefa82f8af5ffc83be5ef
https://github.com/qemu/qemu/commit/35a5d74e8248c09e66deefa82f8af5ffc83be5ef
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/gdbstub.c
M target/ppc/internal.h
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: code motion from translate_init.c.inc to gdbstub.c
All the code related to gdb has been moved from translate_init.c.inc
file to the gdbstub.c file, where it makes more sense.
Version 4 fixes the omission of internal.h in gdbstub, mentioned in
<87sg3d2gf5.fsf@linux.ibm.com>, and the extra blank line.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Suggested-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210426184706.48040-1-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 7468e2c8428d5455ae3efff929dc152bbbe8e6e9
https://github.com/qemu/qemu/commit/7468e2c8428d5455ae3efff929dc152bbbe8e6e9
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/internal.h
M target/ppc/translate.c
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: move opcode table logic to translate.c
code motion to remove opcode callback table from
translate_init.c.inc to translate.c in preparation to remove
the #include <translate_init.c.inc> from translate.c. Also created
destroy_ppc_opcodes and removed that logic from ppc_cpu_unrealize
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210429162130.2412-2-bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 8b7e6b07a46809a75b857d30ae47e697e0f9b724
https://github.com/qemu/qemu/commit/8b7e6b07a46809a75b857d30ae47e697e0f9b724
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: rework AIL logic in interrupt delivery
The AIL logic is becoming unmanageable spread all over powerpc_excp(),
and it is slated to get even worse with POWER10 support.
Move it all to a new helper function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-2-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 526cdce771fa27c37b68fd235ff9f1caa0bdd563
https://github.com/qemu/qemu/commit/526cdce771fa27c37b68fd235ff9f1caa0bdd563
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_hcall.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 61135639821566fe347332e8a01812df2fdd0237
https://github.com/qemu/qemu/commit/61135639821566fe347332e8a01812df2fdd0237
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: Clean up _spr_register et al
Introduce 3 helper macros to elide arguments that we cannot supply.
This reduces the repetition required to get the job done.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210501022923.1179736-2-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 72369f5c959bfdade757d89248b260bc6c648130
https://github.com/qemu/qemu/commit/72369f5c959bfdade757d89248b260bc6c648130
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: Reduce the size of ppc_spr_t
We elide values when registering sprs, we might as well
save space in the array as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210501022923.1179736-3-richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: f350982f5e1715875e547f639baea8c1c9e60bba
https://github.com/qemu/qemu/commit/f350982f5e1715875e547f639baea8c1c9e60bba
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M target/ppc/translate_init.c.inc
Log Message:
-----------
target/ppc: removed VSCR from SPR registration
Since vscr is not an spr, its initialization was removed from the
spr registration functions, and moved to the relevant init_procs.
We may look into adding vscr to the reset path instead of the init
path (as suggested by David Gibson), but this looked like a good
enough solution for now.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210430193533.82136-6-bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: b2df46fd80d9cebc8d9cd3690ec425273c55b434
https://github.com/qemu/qemu/commit/b2df46fd80d9cebc8d9cd3690ec425273c55b434
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/intc/spapr_xive.c
Log Message:
-----------
hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset()
The h_int_reset() function resets the XIVE interrupt controller via
device_legacy_reset(). We know that the interrupt controller does
not have a qbus of its own, so the new device_cold_reset() function
(which resets both the device and its child buses) is equivalent here
to device_legacy_reset() and we can just switch to the new API.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210503151849.8766-2-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 3e1c8ba98844254cbf2e8134697c3f20faf461d4
https://github.com/qemu/qemu/commit/3e1c8ba98844254cbf2e8134697c3f20faf461d4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/spapr_vio.c
Log Message:
-----------
hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset()
The spapr_vio_quiesce_one() function resets the TCE table object
(TYPE_SPAPR_TCE_TABLE) via device_legacy_reset(). We know that
objects of that type do not have a qbus of their own, so the new
device_cold_reset() function (which resets both the device and its
child buses) is equivalent here to device_legacy_reset() and we can
just switch to the new API.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210503151849.8766-3-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 4bb32cd7b1e42c46d274b727c8be8e45b4df3814
https://github.com/qemu/qemu/commit/4bb32cd7b1e42c46d274b727c8be8e45b4df3814
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-05-04 (Tue, 04 May 2021)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset()
The pnv_psi.c code uses device_legacy_reset() for two purposes:
* to reset itself from its qemu_register_reset() handler
* to reset a XiveSource object it has
Neither it nor the XiveSource have any qbuses, so the new
device_cold_reset() function (which resets both the device and its
child buses) is equivalent here to device_legacy_reset() and we can
just switch to the new API.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210503151849.8766-4-peter.maydell@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: d90f154867ec0ec22fd719164b88716e8fd48672
https://github.com/qemu/qemu/commit/d90f154867ec0ec22fd719164b88716e8fd48672
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-05-05 (Wed, 05 May 2021)
Changed paths:
M MAINTAINERS
M default-configs/devices/ppc-softmmu.mak
A docs/system/ppc/ppce500.rst
M docs/system/target-ppc.rst
M hw/intc/spapr_xive.c
M hw/isa/vt82c686.c
M hw/pci-host/Kconfig
M hw/pci-host/meson.build
A hw/pci-host/mv64361.c
A hw/pci-host/mv643xx.h
M hw/pci-host/trace-events
M hw/ppc/Kconfig
M hw/ppc/mac_newworld.c
M hw/ppc/meson.build
A hw/ppc/pegasos2.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_psi.c
M hw/ppc/spapr.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_nvdimm.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_vio.c
M include/hw/isa/vt82c686.h
A include/hw/pci-host/mv64361.h
M include/hw/pci/pci_ids.h
M include/hw/ppc/spapr.h
M linux-user/ppc/cpu_loop.c
M linux-user/ppc/signal.c
M pc-bios/u-boot.e500
M roms/Makefile
M roms/u-boot
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/gdbstub.c
M target/ppc/helper.h
A target/ppc/helper_regs.c
M target/ppc/helper_regs.h
M target/ppc/int_helper.c
M target/ppc/internal.h
M target/ppc/machine.c
M target/ppc/mem_helper.c
M target/ppc/meson.build
M target/ppc/misc_helper.c
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
M target/ppc/translate_init.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210504'
into staging
ppc patch queue 2021-05-04
Here's the first ppc pull request for qemu-6.1. It has a wide variety
of stuff accumulated during the 6.0 freeze. Highlights are:
* Multi-phase reset cleanups for PAPR
* Preliminary cleanups towards allowing !CONFIG_TCG for the ppc target
* Cleanup of AIL logic and extension to POWER10
* Further improvements to handling of hot unplug failures on PAPR
* Allow much larger numbers of CPU on pseries
* Support for the H_SCM_HEALTH hypercall
* Add support for the Pegasos II board
* Substantial cleanup to hflag handling
* Assorted minor fixes and cleanups
# gpg: Signature made Tue 04 May 2021 06:52:39 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
[full]
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dg-gitlab/tags/ppc-for-6.1-20210504: (46 commits)
hw/ppc/pnv_psi: Use device_cold_reset() instead of device_legacy_reset()
hw/ppc/spapr_vio: Reset TCE table object with device_cold_reset()
hw/intc/spapr_xive: Use device_cold_reset() instead of device_legacy_reset()
target/ppc: removed VSCR from SPR registration
target/ppc: Reduce the size of ppc_spr_t
target/ppc: Clean up _spr_register et al
target/ppc: Add POWER10 exception model
target/ppc: rework AIL logic in interrupt delivery
target/ppc: move opcode table logic to translate.c
target/ppc: code motion from translate_init.c.inc to gdbstub.c
spapr_drc.c: handle hotunplug errors in drc_unisolate_logical()
spapr.h: increase FDT_MAX_SIZE
spapr.c: do not use MachineClass::max_cpus to limit CPUs
ppc: Rename current DAWR macros and variables
target/ppc: POWER10 supports scv
target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour
docs/system: ppc: Add documentation for ppce500 machine
roms/u-boot: Bump ppce500 u-boot to v2021.04 to fix broken pci support
roms/Makefile: Update ppce500 u-boot build directory name
ppc/spapr: Add support for implement support for H_SCM_HEALTH
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d45a5270d075...d90f154867ec