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[Qemu-commits] [qemu/qemu] cb53b2: hw/riscv: sifive_u: Switch to use qem
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] cb53b2: hw/riscv: sifive_u: Switch to use qemu_fdt_setprop... |
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Date: |
Tue, 08 Jun 2021 09:51:34 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: cb53b283b5adf4123273d07eee5e186e2e0a1b5b
https://github.com/qemu/qemu/commit/cb53b283b5adf4123273d07eee5e186e2e0a1b5b
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array
helper"),
we can use the new helper to set the clock name for the ethernet
controller node.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2cc04550ac222237b979b5a45679ff746fc99a46
https://github.com/qemu/qemu/commit/2cc04550ac222237b979b5a45679ff746fc99a46
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper
Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array
helper"),
we can use the new helper to set the compatible strings for the
SiFive test device node.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7cfbb17f023dc014d366b2f30af852aa62a5c3b1
https://github.com/qemu/qemu/commit/7cfbb17f023dc014d366b2f30af852aa62a5c3b1
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Support the official CLINT DT bindings
Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 60bb5407f02b9d7cf7078ff339cbae961b7e98cc
https://github.com/qemu/qemu/commit/60bb5407f02b9d7cf7078ff339cbae961b7e98cc
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Support the official PLIC DT bindings
The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3ede8967c8a586c226da21d04283c72e24a2385e
https://github.com/qemu/qemu/commit/3ede8967c8a586c226da21d04283c72e24a2385e
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M docs/system/riscv/microchip-icicle-kit.rst
M docs/system/riscv/sifive_u.rst
Log Message:
-----------
docs/system/riscv: Correct the indentation level of supported devices
The supported device bullet list has an additional space before each
entry, which makes a wrong indentation level. Correct it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0147af69abb17a1ab5780821659c2e71d081c1e2
https://github.com/qemu/qemu/commit/0147af69abb17a1ab5780821659c2e71d081c1e2
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M docs/system/riscv/sifive_u.rst
Log Message:
-----------
docs/system/riscv: sifive_u: Document '-dtb' usage
Update the 'sifive_u' machine documentation to mention the '-dtb'
option that can be used to pass a custom DTB to QEMU.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a0acd0a175891afe554c907c4ecc941abbd98602
https://github.com/qemu/qemu/commit/a0acd0a175891afe554c907c4ecc941abbd98602
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: Use macros for BIOS image names
The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 143897b50140cfd7540f867edca5d658e76aa9bf
https://github.com/qemu/qemu/commit/143897b50140cfd7540f867edca5d658e76aa9bf
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M docs/system/riscv/microchip-icicle-kit.rst
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: microchip_pfsoc: Support direct kernel boot
At present the Microchip Icicle Kit machine only supports using
'-bios' to load the HSS, and does not support '-kernel' for direct
kernel booting just like other RISC-V machines do. One has to use
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
This is not so convenient.
Adding '-kernel' support together with the existing '-bios', we
follow the following table to select which payload we execute:
-bios | -kernel | payload
------+------------+--------
N | N | HSS
Y | don't care | HSS
N | Y | kernel
This ensures backwards compatibility with how we used to expose
'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
must be present to provide a valid device tree for the board,
as we don't generate device tree.
When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
is used to boot a payload like U-Boot or OS kernel directly.
Documentation is updated to describe the direct kernel boot. Note
as of today there is still no PolarFire SoC support in the upstream
Linux kernel hence the document does not include instructions for
that. It will be updated in the future.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-8-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 719f0f603c2289f438b8d6ef4358d9407b4c2905
https://github.com/qemu/qemu/commit/719f0f603c2289f438b8d6ef4358d9407b4c2905
Author: Jose Martins <josemartins90@gmail.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: fix wfi exception behavior
The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:
If supervisor mode is not present:
- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.
If supervisor mode is present:
- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.
Plus, if the hypervisor extensions are enabled:
- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.
Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6debd840c8fedee6a378b05800d3382864e3564d
https://github.com/qemu/qemu/commit/6debd840c8fedee6a378b05800d3382864e3564d
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M docs/system/target-riscv.rst
Log Message:
-----------
docs/system: Move the RISC-V -bios information to removed
QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
Commit: bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3
https://github.com/qemu/qemu/commit/bbf3d1b48fe170c0220a2267117d8a1ea9c2c2a3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Do not include 'pmp.h' in user emulation
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210516205333.696094-1-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9a575d33fba497db48cda36273bde8710651888e
https://github.com/qemu/qemu/commit/9a575d33fba497db48cda36273bde8710651888e
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Remove unnecessary riscv_*_names[] declaration
riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210514052435.2203156-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a722701dd364b82dc115e94a29d767949f796000
https://github.com/qemu/qemu/commit/a722701dd364b82dc115e94a29d767949f796000
Author: Changbin Du <changbin.du@gmail.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Dump CSR mscratch/sscratch/satp
This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.
Signed-off-by: Changbin Du <changbin.du@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210519155738.20486-1-changbin.du@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 787a4baf91fa2ff36b901c0b31ea73f3f0739415
https://github.com/qemu/qemu/commit/787a4baf91fa2ff36b901c0b31ea73f3f0739415
Author: Alistair Francis <alistair.francis@wdc.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv/pmp: Add assert for ePMP operations
Although we construct epmp_operation in such a way that it can only be
between 0 and 15 Coverity complains that we don't handle the other
possible cases. To fix Coverity and make it easier for humans to read
add a default case to the switch statement that calls
g_assert_not_reached().
Fixes: CID 1453108
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id:
ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
Commit: eee2d61e202b5bd49a5eb211e347e02c86287ef4
https://github.com/qemu/qemu/commit/eee2d61e202b5bd49a5eb211e347e02c86287ef4
Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Pass the same value to oprsz and maxsz.
Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
is still zero(as we don't use this field), simd_desc will trigger an
assert.
Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
Here we pass the value to maxsz and oprsz to bypass the assert.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210521054816.1784297-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 00718208c127315d82f1f1f8383ef29bc478628e
https://github.com/qemu/qemu/commit/00718208c127315d82f1f1f8383ef29bc478628e
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
Log Message:
-----------
target/riscv: reformat @sh format encoding for B-extension
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 438240185a9456747b19a29290018316271a3762
https://github.com/qemu/qemu/commit/438240185a9456747b19a29290018316271a3762
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: count leading/trailing zeros
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1e16310ca1bd368f20eb93683cc37389d5db185d
https://github.com/qemu/qemu/commit/1e16310ca1bd368f20eb93683cc37389d5db185d
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: count bits set
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0bcdb686e586d8f5bfa2b2f9261d75a76b15e3cb
https://github.com/qemu/qemu/commit/0bcdb686e586d8f5bfa2b2f9261d75a76b15e3cb
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvb: logic-with-negate
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 6ef5843182382f6a84995590ad91047b0f2bc1fa
https://github.com/qemu/qemu/commit/6ef5843182382f6a84995590ad91047b0f2bc1fa
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: pack two words into one register
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82655d8115f022a0132a74e0229dc7fa9b623b87
https://github.com/qemu/qemu/commit/82655d8115f022a0132a74e0229dc7fa9b623b87
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvb: min/max instructions
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-7-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2a81973829d0e77bbfdcf9ca217de8fde5cff88f
https://github.com/qemu/qemu/commit/2a81973829d0e77bbfdcf9ca217de8fde5cff88f
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
Log Message:
-----------
target/riscv: rvb: sign-extend instructions
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210505160620.15723-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 981d3568dfa8b5180de1719fa590db558e9720b7
https://github.com/qemu/qemu/commit/981d3568dfa8b5180de1719fa590db558e9720b7
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-9-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 23cd17773bdc559877cc81b7129c4dd41ae53e4f
https://github.com/qemu/qemu/commit/23cd17773bdc559877cc81b7129c4dd41ae53e4f
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: single-bit instructions
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-10-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 91d8fc676819eff4ffcb7a8038e6de7d1dd381d3
https://github.com/qemu/qemu/commit/91d8fc676819eff4ffcb7a8038e6de7d1dd381d3
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: shift ones
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e58529a8d03ab8e9127f3e7cdf757ff84af75698
https://github.com/qemu/qemu/commit/e58529a8d03ab8e9127f3e7cdf757ff84af75698
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: rotate (left/right)
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 831ec7f3d1ede387eca225ccaccb2845cbbca85e
https://github.com/qemu/qemu/commit/831ec7f3d1ede387eca225ccaccb2845cbbca85e
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
A target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: generalized reverse
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c24f0422fbc0924389c1345ee30d8f87730ae633
https://github.com/qemu/qemu/commit/c24f0422fbc0924389c1345ee30d8f87730ae633
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/bitmanip_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: generalized or-combine
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-14-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 920a1f9955c528f2be3ff9c9e1cbf40ddad1b192
https://github.com/qemu/qemu/commit/920a1f9955c528f2be3ff9c9e1cbf40ddad1b192
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: address calculation
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3a4a43e4e213a18d1ee4ed97090a5e86401c85bc
https://github.com/qemu/qemu/commit/3a4a43e4e213a18d1ee4ed97090a5e86401c85bc
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: rvb: add/shift with prefix zero-extend
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-16-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d52e94081e626b6b4b181dc7a6fc8f0b98e7d403
https://github.com/qemu/qemu/commit/d52e94081e626b6b4b181dc7a6fc8f0b98e7d403
Author: Kito Cheng <kito.cheng@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: rvb: support and turn on B-extension from command line
B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-17-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d2c1a177b138be35cb96216baa870c3564b123e4
https://github.com/qemu/qemu/commit/d2c1a177b138be35cb96216baa870c3564b123e4
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: rvb: add b-ext version cpu option
Default b-ext version is v0.93.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-18-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a4716fd8d7c877185652f5f8e25032dc7699d51b
https://github.com/qemu/qemu/commit/a4716fd8d7c877185652f5f8e25032dc7699d51b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-08 (Tue, 08 Jun 2021)
Changed paths:
M docs/system/deprecated.rst
M docs/system/removed-features.rst
M docs/system/riscv/microchip-icicle-kit.rst
M docs/system/riscv/sifive_u.rst
M docs/system/target-riscv.rst
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
A target/riscv/bitmanip_helper.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvb.c.inc
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/meson.build
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging
Second RISC-V PR for QEMU 6.1
- Update the PLIC and CLINT DT bindings
- Improve documentation for RISC-V machines
- Support direct kernel boot for microchip_pfsoc
- Fix WFI exception behaviour
- Improve CSR printing
- Initial support for the experimental Bit Manip extension
# gpg: Signature made Tue 08 Jun 2021 01:28:27 BST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits)
target/riscv: rvb: add b-ext version cpu option
target/riscv: rvb: support and turn on B-extension from command line
target/riscv: rvb: add/shift with prefix zero-extend
target/riscv: rvb: address calculation
target/riscv: rvb: generalized or-combine
target/riscv: rvb: generalized reverse
target/riscv: rvb: rotate (left/right)
target/riscv: rvb: shift ones
target/riscv: rvb: single-bit instructions
target/riscv: add gen_shifti() and gen_shiftiw() helper functions
target/riscv: rvb: sign-extend instructions
target/riscv: rvb: min/max instructions
target/riscv: rvb: pack two words into one register
target/riscv: rvb: logic-with-negate
target/riscv: rvb: count bits set
target/riscv: rvb: count leading/trailing zeros
target/riscv: reformat @sh format encoding for B-extension
target/riscv: Pass the same value to oprsz and maxsz.
target/riscv/pmp: Add assert for ePMP operations
target/riscv: Dump CSR mscratch/sscratch/satp
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/33ba8b0adc91...a4716fd8d7c8
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