[Qemu-commits] [qemu/qemu] 385487: target/arm: Implement MVE VRMLALDAVH,

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 385487: target/arm: Implement MVE VRMLALDAVH,

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 385487: target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
Date:	Thu, 24 Jun 2021 07:01:01 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 38548747335a0796ab1d636c8b5bcf5c248ce437
      
https://github.com/qemu/qemu/commit/38548747335a0796ab1d636c8b5bcf5c248ce437
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-21 (Mon, 21 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH

Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate
the results of a rounded multiply of pairs of elements into a 72-bit
accumulator, returning the top 64 bits in a pair of general purpose
registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-22-peter.maydell@linaro.org


  Commit: e51896b3866ffb74df5aaa3b33c35e7113e5c6b9
      
https://github.com/qemu/qemu/commit/e51896b3866ffb74df5aaa3b33c35e7113e5c6b9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VADD (scalar)

Implement the scalar form of the MVE VADD insn. This takes the
scalar operand from a general purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-23-peter.maydell@linaro.org


  Commit: 91a358fdfb3b116a6ea72a38d5c217caad1d45b5
      
https://github.com/qemu/qemu/commit/91a358fdfb3b116a6ea72a38d5c217caad1d45b5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VSUB, VMUL (scalar)

Implement the scalar forms of the MVE VSUB and VMUL insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-24-peter.maydell@linaro.org


  Commit: 644f717c35ec29d53f6fc34523e096fbad6eeaf9
      
https://github.com/qemu/qemu/commit/644f717c35ec29d53f6fc34523e096fbad6eeaf9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VHADD, VHSUB (scalar)

Implement the scalar variants of the MVE VHADD and VHSUB insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-25-peter.maydell@linaro.org


  Commit: b050543b68308427792cc024fb2905b041ebc253
      
https://github.com/qemu/qemu/commit/b050543b68308427792cc024fb2905b041ebc253
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VBRSR

Implement the MVE VBRSR insn, which reverses a specified
number of bits in each element, setting the rest to zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-26-peter.maydell@linaro.org


  Commit: 387debdb93d2635fb6d62bff38887d17ef4d8117
      
https://github.com/qemu/qemu/commit/387debdb93d2635fb6d62bff38887d17ef4d8117
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/mve.decode
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VPST

Implement the MVE VPST insn, which sets the predicate mask
fields in the VPR to the immediate value encoded in the insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-27-peter.maydell@linaro.org


  Commit: 39f2ec8592dd3c823034dc4decc64c7e4cc42bfd
      
https://github.com/qemu/qemu/commit/39f2ec8592dd3c823034dc4decc64c7e4cc42bfd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQADD and VQSUB

Implement the MVE VQADD and VQSUB insns, which perform saturating
addition of a scalar to each element.  Note that individual bytes of
each result element are used or discarded according to the predicate
mask, but FPSCR.QC is only set if the predicate mask for the lowest
byte of the element is set.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-28-peter.maydell@linaro.org


  Commit: 66c0576754b100606e041fef54e5b897417426c7
      
https://github.com/qemu/qemu/commit/66c0576754b100606e041fef54e5b897417426c7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)

Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply
elements by the scalar, double, possibly round, take the high half
and saturate.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-29-peter.maydell@linaro.org


  Commit: a88903537d73b1d9728e3d824920b4d0096f10bc
      
https://github.com/qemu/qemu/commit/a88903537d73b1d9728e3d824920b4d0096f10bc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMULL scalar

Implement the MVE VQDMULL scalar insn. This multiplies the top or
bottom half of each element by the scalar, doubles and saturates
to a double-width result.

Note that this encoding overlaps with VQADD and VQSUB; it uses
what in VQADD and VQSUB would be the 'size=0b11' encoding.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-30-peter.maydell@linaro.org


  Commit: 380caf6c0762f43a9468aeebaf4ba7e1dd8edc9a
      
https://github.com/qemu/qemu/commit/380caf6c0762f43a9468aeebaf4ba7e1dd8edc9a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMULH, VQRDMULH (vector)

Implement the vector forms of the MVE VQDMULH and VQRDMULH insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-31-peter.maydell@linaro.org


  Commit: f741707bb36f7281ceccbdc0c44dcce61fbe1023
      
https://github.com/qemu/qemu/commit/f741707bb36f7281ceccbdc0c44dcce61fbe1023
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQADD, VQSUB (vector)

Implement the vector forms of the MVE VQADD and VQSUB insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-32-peter.maydell@linaro.org


  Commit: 483da6613937ea34fbf4b970668021dd76e46636
      
https://github.com/qemu/qemu/commit/483da6613937ea34fbf4b970668021dd76e46636
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQSHL (vector)

Implement the MVE VQSHL insn (encoding T4, which is the
vector-shift-by-vector version).

The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from
the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-33-peter.maydell@linaro.org


  Commit: 9dc868c41d8c630f3c13040e2732b4df6d4739de
      
https://github.com/qemu/qemu/commit/9dc868c41d8c630f3c13040e2732b4df6d4739de
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQRSHL

Implement the MV VQRSHL (vector) insn.  Again, the code to perform
the actual shifts is borrowed from neon_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-34-peter.maydell@linaro.org


  Commit: 0372cad813193bab3fb88985129ac59c801ca065
      
https://github.com/qemu/qemu/commit/0372cad813193bab3fb88985129ac59c801ca065
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VSHL insn

Implement the MVE VSHL insn (vector form).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-35-peter.maydell@linaro.org


  Commit: bb002345ebfe09f6f96fc41043f93d2e286cd136
      
https://github.com/qemu/qemu/commit/bb002345ebfe09f6f96fc41043f93d2e286cd136
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VRSHL

Implement the MVE VRSHL insn (vector form).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-36-peter.maydell@linaro.org


  Commit: fd677f8055fa88d72f01eb9aeb1dd90606d85444
      
https://github.com/qemu/qemu/commit/fd677f8055fa88d72f01eb9aeb1dd90606d85444
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMLADH and VQRDMLADH

Implement the MVE VQDMLADH and VQRDMLADH insns.  These multiply
elements, and then add pairs of products, double, possibly round,
saturate and return the high half of the result.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-37-peter.maydell@linaro.org


  Commit: 92f117326af14d9bffc2ec99e0f112d33c0615ca
      
https://github.com/qemu/qemu/commit/92f117326af14d9bffc2ec99e0f112d33c0615ca
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMLSDH and VQRDMLSDH

Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are
like VQDMLADH and VQRDMLADH except that products are subtracted
rather than added.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-38-peter.maydell@linaro.org


  Commit: 43364321f354b8722d5bab730052b625adc3a92c
      
https://github.com/qemu/qemu/commit/43364321f354b8722d5bab730052b625adc3a92c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQDMULL (vector)

Implement the vector form of the MVE VQDMULL insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-39-peter.maydell@linaro.org


  Commit: 1eb987a89d944515b05ccd8b913bee7fd0d547ae
      
https://github.com/qemu/qemu/commit/1eb987a89d944515b05ccd8b913bee7fd0d547ae
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VRHADD

Implement the MVE VRHADD insn, which performs a rounded halving
addition.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-40-peter.maydell@linaro.org


  Commit: 89bc4c4f78c2435fdf8dc10b650cfe73c75f1f2c
      
https://github.com/qemu/qemu/commit/89bc4c4f78c2435fdf8dc10b650cfe73c75f1f2c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VADC, VSBC

Implement the MVE VADC and VSBC insns.  These perform an
add-with-carry or subtract-with-carry of the 32-bit elements in each
lane of the input vectors, where the carry-out of each add is the
carry-in of the next.  The initial carry input is either 1 or is from
FPSCR.C; the carry out at the end is written back to FPSCR.C.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-41-peter.maydell@linaro.org


  Commit: 67ec113b119360092dee679ca0f5eca8ac60992c
      
https://github.com/qemu/qemu/commit/67ec113b119360092dee679ca0f5eca8ac60992c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VCADD

Implement the MVE VCADD insn, which performs a complex add with
rotate.  Note that the size=0b11 encoding is VSBC.

The architecture grants some leeway for the "destination and Vm
source overlap" case for the size MO_32 case, but we choose not to
make use of it, instead always calculating all 16 bytes worth of
results before setting the destination register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-42-peter.maydell@linaro.org


  Commit: 8625693ac48f54e87f663736c0bbde7ea450f1f7
      
https://github.com/qemu/qemu/commit/8625693ac48f54e87f663736c0bbde7ea450f1f7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VHCADD

Implement the MVE VHCADD insn, which is similar to VCADD
but performs a halving step. This one overlaps with VADC.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-43-peter.maydell@linaro.org


  Commit: 6f060a636bf46869e43a28a0f426ddaea16314f9
      
https://github.com/qemu/qemu/commit/6f060a636bf46869e43a28a0f426ddaea16314f9
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VADDV

Implement the MVE VADDV insn, which performs an addition
across vector lanes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-44-peter.maydell@linaro.org


  Commit: 4f57ef959cf83cc780658c7e97ba5f737aa666f2
      
https://github.com/qemu/qemu/commit/4f57ef959cf83cc780658c7e97ba5f737aa666f2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/arm/translate-a32.h
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Make VMOV scalar <-> gpreg beatwise for MVE

In a CPU with MVE, the VMOV (vector lane to general-purpose register)
and VMOV (general-purpose register to vector lane) insns are not
predicated, but they are subject to beatwise execution if they
are not in an IT block.

Since our implementation always executes all 4 beats in one tick,
this means only that we need to handle PSR.ECI:
 * we must do the usual check for bad ECI state
 * we must advance ECI state if the insn succeeds
 * if ECI says we should not be executing the beat corresponding
   to the lane of the vector register being accessed then we
   should skip performing the move

Note that if PSR.ECI is non-zero then we cannot be in an IT block.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-45-peter.maydell@linaro.org


  Commit: 86f0d4c7290eb2b21ec3eb44956ec245441275db
      
https://github.com/qemu/qemu/commit/86f0d4c7290eb2b21ec3eb44956ec245441275db
  Author: Peter Collingbourne <pcc@google.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu64.c
    M target/arm/mte_helper.c

  Log Message:
  -----------
  target/arm: Implement MTE3

MTE3 introduces an asymmetric tag checking mode, in which loads are
checked synchronously and stores are checked asynchronously. Add
support for it.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210616195614.11785-1-pcc@google.com
[PMM: Add line to emulation.rst]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 90a76c6316cfe6416fc33814a838fb3928f746ee
      
https://github.com/qemu/qemu/commit/90a76c6316cfe6416fc33814a838fb3928f746ee
  Author: Alexandre Iooss <erdnaxe@crans.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M MAINTAINERS
    A docs/system/arm/nrf.rst
    M docs/system/target-arm.rst

  Log Message:
  -----------
  docs/system: arm: Add nRF boards description

This adds the target guide for BBC Micro:bit.

Information is taken from https://wiki.qemu.org/Features/MicroBit
and from hw/arm/nrf51_soc.c.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20210621075625.540471-1-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ecba223da6215d6f6ce2d343b70b2e9a19bfb90b
      
https://github.com/qemu/qemu/commit/ecba223da6215d6f6ce2d343b70b2e9a19bfb90b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M MAINTAINERS
    A docs/system/arm/emulation.rst
    A docs/system/arm/nrf.rst
    M docs/system/target-arm.rst
    A hw/acpi/ghes-stub.c
    M hw/acpi/ghes.c
    M hw/acpi/meson.build
    M include/hw/acpi/ghes.h
    M include/tcg/tcg-op.h
    M include/tcg/tcg.h
    M target/arm/cpu64.c
    A target/arm/helper-mve.h
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/m-nocp.decode
    M target/arm/meson.build
    M target/arm/mte_helper.c
    M target/arm/mve.decode
    A target/arm/mve_helper.c
    M target/arm/translate-a32.h
    M target/arm/translate-m-nocp.c
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c
    M target/arm/translate.h
    M target/arm/vfp.decode
    M tcg/tcg-op-gvec.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210624' 
into staging

target-arm queue:
 * Don't require 'virt' board to be compiled in for ACPI GHES code
 * docs: Document which architecture extensions we emulate
 * Fix bugs in M-profile FPCXT_NS accesses
 * First slice of MVE patches
 * Implement MTE3
 * docs/system: arm: Add nRF boards description

# gpg: Signature made Thu 24 Jun 2021 14:59:16 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210624: (57 commits)
  docs/system: arm: Add nRF boards description
  target/arm: Implement MTE3
  target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
  target/arm: Implement MVE VADDV
  target/arm: Implement MVE VHCADD
  target/arm: Implement MVE VCADD
  target/arm: Implement MVE VADC, VSBC
  target/arm: Implement MVE VRHADD
  target/arm: Implement MVE VQDMULL (vector)
  target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
  target/arm: Implement MVE VQDMLADH and VQRDMLADH
  target/arm: Implement MVE VRSHL
  target/arm: Implement MVE VSHL insn
  target/arm: Implement MVE VQRSHL
  target/arm: Implement MVE VQSHL (vector)
  target/arm: Implement MVE VQADD, VQSUB (vector)
  target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
  target/arm: Implement MVE VQDMULL scalar
  target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
  target/arm: Implement MVE VQADD and VQSUB
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/e6350320b391...ecba223da621
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] 385487: target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell <=
Prev by Date: [Qemu-commits] [qemu/qemu] 82faef: hw/acpi: Provide stub version of acpi_ghes_record_...
Next by Date: [Qemu-commits] [qemu/qemu] 82faef: hw/acpi: Provide stub version of acpi_ghes_record_...
Previous by thread: [Qemu-commits] [qemu/qemu] 82faef: hw/acpi: Provide stub version of acpi_ghes_record_...
Next by thread: [Qemu-commits] [qemu/qemu] ddc3c1: target/i386: kvm: add support for TSC scaling
Index(es):
- Date
- Thread