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[Qemu-commits] [qemu/qemu] 5ecb12: Merge remote-tracking branch 'remotes

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 5ecb12: Merge remote-tracking branch 'remotes/rth-gitlab/t...
Date: Thu, 23 Sep 2021 02:26:43 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 5ecb128c9a7aeba179f4fb05efdeffd9256b8c9d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M include/exec/exec-all.h
    M include/hw/core/tcg-cpu-ops.h
    M target/alpha/cpu.h
    M target/arm/cpu.h
    M target/arm/internals.h
    M target/avr/cpu.h
    M target/cris/cpu.h
    M target/hexagon/cpu.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/i386/cpu.h
    M target/m68k/cpu.h
    M target/microblaze/cpu.h
    M target/mips/cpu.h
    M target/mips/internal.h
    M target/mips/tcg/tcg-internal.h
    M target/nios2/cpu.h
    M target/openrisc/cpu.h
    M target/ppc/cpu.h
    M target/ppc/internal.h
    M target/riscv/cpu.h
    M target/rx/cpu.h
    M target/s390x/cpu.h
    M target/s390x/s390x-internal.h
    M target/sh4/cpu.h
    M target/sparc/cpu.h
    M target/tricore/cpu.h
    M target/xtensa/cpu.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/region.c
    M tcg/riscv/tcg-target.c.inc
    M tcg/sparc/tcg-target.c.inc

  Log Message:
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210921' into 

Move cpu_signal_handler declaration.
Restrict cpu_handle_halt to sysemu.
Make do_unaligned_access noreturn.
Misc tcg/mips cleanup
Misc tcg/sparc cleanup
Misc tcg/riscv cleanup

# gpg: Signature made Wed 22 Sep 2021 03:47:29 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210921:
  tcg/riscv: Remove add with zero on user-only memory access
  hw/core: Make do_unaligned_access noreturn
  tcg/sparc: Introduce tcg_out_mov_delay
  tcg/sparc: Drop inline markers
  tcg/mips: Drop special alignment for code_gen_buffer
  tcg/mips: Unset TCG_TARGET_HAS_direct_jump
  tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr
  tcg/mips: Drop inline markers
  accel/tcg: Restrict cpu_handle_halt() to sysemu
  include/exec: Move cpu_signal_handler declaration

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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