qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 4825ea: Revert "arm: tcg: Adhere to SMCCC 1.3


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 4825ea: Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"
Date: Mon, 22 Nov 2021 07:41:33 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d
      
https://github.com/qemu/qemu/commit/4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-11-22 (Mon, 22 Nov 2021)

  Changed paths:
    M target/arm/psci.c

  Log Message:
  -----------
  Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"

This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4.

This change turns out to cause regressions, for instance on the
imx6ul boards as described here:
https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/

The primary cause of that regression is that the guest code running
at EL3 expects SMCs (not related to PSCI) to do what they would if
our PSCI emulation was not present at all, but after this change
they instead set a value in R0/X0 and continue.

We could fix that by a refactoring that allowed us to only turn on
the PSCI emulation if we weren't booting the guest at EL3, but there
is a more tangled problem with the highbank board, which:
 (1) wants to enable PSCI emulation
 (2) has a bit of guest code that it wants to run at EL3 and
     to perform SMC calls that trap to the monitor vector table:
     this is the boot stub code that is written to memory by
     arm_write_secure_board_setup_dummy_smc() and which the
     highbank board enables by setting bootinfo->secure_board_setup

We can't satisfy both of those and also have the PSCI emulation
handle all SMC instruction executions regardless of function
identifier value.

This is too tricky to try to sort out before 6.2 is released;
revert this commit so we can take the time to get it right in
the 7.0 release.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211119163419.557623-1-peter.maydell@linaro.org


  Commit: 89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a
      
https://github.com/qemu/qemu/commit/89d2f9e4c63799f7f03e9180c63b7dc45fc2a04a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-11-22 (Mon, 22 Nov 2021)

  Changed paths:
    M target/arm/psci.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20211122' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * revert SMCCC/PSCI change, as it regresses some usecases for some boards

# gpg: Signature made Mon 22 Nov 2021 02:42:19 PM CET
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20211122' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2"

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/5d1f437fb42d...89d2f9e4c637



reply via email to

[Prev in Thread] Current Thread [Next in Thread]