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[Qemu-commits] [qemu/qemu] 702511: hw/openrisc: Split re-usable boot tim

From: Paolo Bonzini
Subject: [Qemu-commits] [qemu/qemu] 702511: hw/openrisc: Split re-usable boot time apis out to...
Date: Mon, 05 Sep 2022 15:03:21 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 7025114b1cd7683cb7fbef0810577c67aa3cbbd8
      
https://github.com/qemu/qemu/commit/7025114b1cd7683cb7fbef0810577c67aa3cbbd8
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    A hw/openrisc/boot.c
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c
    A include/hw/openrisc/boot.h

  Log Message:
  -----------
  hw/openrisc: Split re-usable boot time apis out to boot.c

These will be shared with the virt platform.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 0fd8a106efb6bc2e55b3e9629b106d13a7214570
      
https://github.com/qemu/qemu/commit/0fd8a106efb6bc2e55b3e9629b106d13a7214570
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M target/openrisc/mmu.c

  Log Message:
  -----------
  target/openrisc: Fix memory reading in debugger

In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined.  This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.

This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 65f5144e1726c36c97df7e70484250941aafaa27
      
https://github.com/qemu/qemu/commit/65f5144e1726c36c97df7e70484250941aafaa27
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M hw/m68k/virt.c
    M hw/rtc/goldfish_rtc.c
    M include/hw/rtc/goldfish_rtc.h

  Log Message:
  -----------
  goldfish_rtc: Add big-endian property

Add a new property "big-endian" to allow configuring the RTC as either
little or big endian, the default is little endian.

Currently overriding the default to big endian is only used by the m68k
virt platform.  New platforms should prefer to use little endian and not
set this.

Cc: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: b5fcfe927b7a9cbbc0864e7fc4f34bc94631ee0e
      
https://github.com/qemu/qemu/commit/b5fcfe927b7a9cbbc0864e7fc4f34bc94631ee0e
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M configs/devices/or1k-softmmu/default.mak
    M hw/openrisc/Kconfig
    M hw/openrisc/meson.build
    A hw/openrisc/virt.c

  Log Message:
  -----------
  hw/openrisc: Add the OpenRISC virtual machine

This patch adds the OpenRISC virtual machine 'virt' for OpenRISC.  This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.

Much of this has been sourced from the m68k and riscv virt platforms.

The platform provides:
 - OpenRISC SMP with up to 4 cpus
 - A virtio bus with up to 8 devices
 - Standard ns16550a serial
 - Goldfish RTC
 - SiFive TEST device for poweroff and reboot
 - Generated Device Tree to automatically configure the guest kernel

Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 40fef82c4e7ea723b52eb3d2a0c4a46189f1ad44
      
https://github.com/qemu/qemu/commit/40fef82c4e7ea723b52eb3d2a0c4a46189f1ad44
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M hw/openrisc/Kconfig
    M hw/openrisc/virt.c

  Log Message:
  -----------
  hw/openrisc: Add PCI bus support to virt

This is mostly borrowed from xtensa and riscv as examples.  The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.

Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 557e37071d4d4e6de577f5a4dfb012a6a733f319
      
https://github.com/qemu/qemu/commit/557e37071d4d4e6de577f5a4dfb012a6a733f319
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M hw/openrisc/cputimer.c

  Log Message:
  -----------
  hw/openrisc: Initialize timer time at startup

The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.

This patch moves timer initialization to the cpu reset.  There are two
resets registered here:

 1. Per cpu timer mask (ttmr) reset.
 2. Global cpu timer (last_clk and ttcr) reset, attached to the first
    cpu only.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: bbe6855ef80f61c6b00da22aa0cd550d79d8e381
      
https://github.com/qemu/qemu/commit/bbe6855ef80f61c6b00da22aa0cd550d79d8e381
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M target/openrisc/interrupt.c

  Log Message:
  -----------
  target/openrisc: Add interrupted CPU to log

When we are tracing it's helpful to know which CPU's are getting
interrupted, add that detail to the log line.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 6a0fc96ad2b16a264ead6b696bdb91a963450dbb
      
https://github.com/qemu/qemu/commit/6a0fc96ad2b16a264ead6b696bdb91a963450dbb
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M configs/targets/or1k-softmmu.mak
    M target/openrisc/cpu.h
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Enable MTTCG

This patch enables multithread TCG for OpenRISC.  Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: 66564c31e4e012c65c84d403c2dc14c0a754047f
      
https://github.com/qemu/qemu/commit/66564c31e4e012c65c84d403c2dc14c0a754047f
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Interrupt handling fixes

When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.

This looks to be caused by 2 issues in the openrisc interrupt handling
logic.

 1. After clearing an interrupt the openrisc_cpu_set_irq handler will
    always clear PICSR.  This is not correct as masked interrupts
    should still be visible in PICSR.
 2. After setting PICMR (mask register) and exposed interrupts should
    cause an interrupt to be raised.  This was not being done so add it.

This patch fixes both issues.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: c6fe3e6b4cd8d7b98ea37bf37fb3686ecd1304fe
      
https://github.com/qemu/qemu/commit/c6fe3e6b4cd8d7b98ea37bf37fb3686ecd1304fe
  Author: Jason A. Donenfeld <Jason@zx2c4.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    M hw/openrisc/virt.c

  Log Message:
  -----------
  hw/openrisc: virt: pass random seed to fdt

If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: b14df228d7c4fe6e86e7f8a4998e9ccf4967b678
      
https://github.com/qemu/qemu/commit/b14df228d7c4fe6e86e7f8a4998e9ccf4967b678
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2022-09-04 (Sun, 04 Sep 2022)

  Changed paths:
    A docs/system/openrisc/cpu-features.rst
    A docs/system/openrisc/emulation.rst
    A docs/system/openrisc/or1k-sim.rst
    A docs/system/openrisc/virt.rst
    A docs/system/target-openrisc.rst
    M docs/system/targets.rst

  Log Message:
  -----------
  docs/system: openrisc: Add OpenRISC documentation

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>


  Commit: fd28528ece590dc709d1a893fce2ff2f68ddca70
      
https://github.com/qemu/qemu/commit/fd28528ece590dc709d1a893fce2ff2f68ddca70
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2022-09-05 (Mon, 05 Sep 2022)

  Changed paths:
    M configs/devices/or1k-softmmu/default.mak
    M configs/targets/or1k-softmmu.mak
    A docs/system/openrisc/cpu-features.rst
    A docs/system/openrisc/emulation.rst
    A docs/system/openrisc/or1k-sim.rst
    A docs/system/openrisc/virt.rst
    A docs/system/target-openrisc.rst
    M docs/system/targets.rst
    M hw/m68k/virt.c
    M hw/openrisc/Kconfig
    A hw/openrisc/boot.c
    M hw/openrisc/cputimer.c
    M hw/openrisc/meson.build
    M hw/openrisc/openrisc_sim.c
    A hw/openrisc/virt.c
    M hw/rtc/goldfish_rtc.c
    A include/hw/openrisc/boot.h
    M include/hw/rtc/goldfish_rtc.h
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  Merge tag 'pull-or1k-20220904' of https://github.com/stffrdhrn/qemu into 
staging

OpenRISC updates for 7.2.0

Updates to add the OpenRISC virt plaform to QEMU. Highlights
include:

- New virt plaform with, virtio and pci bus support
- OpenRISC support for MTTCG
- Goldfish RTC device endianness is configurable now

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# gpg: Signature made Sun 04 Sep 2022 02:31:58 EDT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* tag 'pull-or1k-20220904' of https://github.com/stffrdhrn/qemu:
  docs/system: openrisc: Add OpenRISC documentation
  hw/openrisc: virt: pass random seed to fdt
  target/openrisc: Interrupt handling fixes
  target/openrisc: Enable MTTCG
  target/openrisc: Add interrupted CPU to log
  hw/openrisc: Initialize timer time at startup
  hw/openrisc: Add PCI bus support to virt
  hw/openrisc: Add the OpenRISC virtual machine
  goldfish_rtc: Add big-endian property
  target/openrisc: Fix memory reading in debugger
  hw/openrisc: Split re-usable boot time apis out to boot.c

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/2682d1ad9306...fd28528ece59
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