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[Qemu-commits] [qemu/qemu] 53bdce: MAINTAINERS: downgrade PPC KVM/TCG CP
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 53bdce: MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSerie... |
Date: |
Tue, 20 Dec 2022 10:50:31 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 53bdcef7674747730900d14e90909a29c3a60a1d
https://github.com/qemu/qemu/commit/53bdcef7674747730900d14e90909a29c3a60a1d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes'
The maintainer is no longer being paid to maintain these components. All
maintainership work is being done in his personal time since the middle
of the 7.2 development cycle.
Change the status of PPC KVM CPUs, PPC TCG CPUs and the pSeries machine
to 'Odd Fixes', reflecting that the maintainer no longer has exclusive
time to dedicate to them. It'll also (hopefully) keep expectations under
check when/if these components are used in a customer product.
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20221117153218.182835-1-danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 5218b3960738a6da041aa6f54ac4b37566311cca
https://github.com/qemu/qemu/commit/5218b3960738a6da041aa6f54ac4b37566311cca
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/sd/sdhci.c
Log Message:
-----------
hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221101222934.52444-2-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 38668c034b280305274cfa3069c7f37ee225fe86
https://github.com/qemu/qemu/commit/38668c034b280305274cfa3069c7f37ee225fe86
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/sd/sdhci-internal.h
M hw/sd/sdhci.c
M include/hw/sd/sdhci.h
Log Message:
-----------
hw/sd/sdhci: Support big endian SD host controller interfaces
Some SDHCI IP can be synthetized in various endianness:
https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be
determined by ESDHC IP's endian mode or processor's endian mode.
Our current implementation is little-endian. In order to support
big endianness:
- Rename current MemoryRegionOps as sdhci_mmio_le_ops ('le')
- Add an 'endianness' property to SDHCIState (default little endian)
- Set the 'io_ops' field in realize() after checking the property
- Add the sdhci_mmio_be_ops (big-endian) MemoryRegionOps.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 968ebd1d18d8bc9f9f3156d4b69fe2e9f91de9f8
https://github.com/qemu/qemu/commit/968ebd1d18d8bc9f9f3156d4b69fe2e9f91de9f8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M docs/system/ppc/ppce500.rst
M hw/ppc/Kconfig
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/e500plat.c
Log Message:
-----------
hw/ppc/e500: Add Freescale eSDHC to e500plat
Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221018210146.193159-8-shentey@gmail.com>
[PMD: Simplify using create_unimplemented_device("esdhc")]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221101222934.52444-4-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: da2aa9545ab60d4ff5d27ad43cc04aee488961e3
https://github.com/qemu/qemu/commit/da2aa9545ab60d4ff5d27ad43cc04aee488961e3
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h"
kvm_ppc.h is missing various declarations from "cpu.h":
target/ppc/kvm_ppc.h:128:40: error: unknown type name 'CPUPPCState'; did you
mean 'CPUState'?
static inline int kvmppc_get_hypercall(CPUPPCState *env,
^~~~~~~~~~~
CPUState
include/qemu/typedefs.h:45:25: note: 'CPUState' declared here
typedef struct CPUState CPUState;
^
target/ppc/kvm_ppc.h:134:40: error: unknown type name 'PowerPCCPU'
static inline int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
^
target/ppc/kvm_ppc.h:285:38: error: unknown type name 'hwaddr'
hwaddr ptex, int n)
^
target/ppc/kvm_ppc.h:220:15: error: unknown type name 'target_ulong'
static inline target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
^
target/ppc/kvm_ppc.h:286:38: error: unknown type name 'ppc_hash_pte64_t'
static inline void kvmppc_read_hptes(ppc_hash_pte64_t *hptes,
^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-2-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 4832f99a47093338d5769943060be97a532031f0
https://github.com/qemu/qemu/commit/4832f99a47093338d5769943060be97a532031f0
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M include/hw/ppc/vof.h
Log Message:
-----------
hw/ppc/vof: Do not include the full "cpu.h"
"vof.h" doesn't need the full "cpu.h" to get the target_ulong
definition, including "exec/cpu-defs.h" is enough.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: c21ad0be8e41847c8371a15ebee57bad21c3fee8
https://github.com/qemu/qemu/commit/c21ad0be8e41847c8371a15ebee57bad21c3fee8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
hw/ppc/spapr: Reduce "vof.h" inclusion
Currently objects including "hw/ppc/spapr.h" are forced to be
target specific due to the inclusion of "vof.h" in "spapr.h".
"spapr.h" only uses a Vof pointer, so doesn't require the structure
declaration. The only place where Vof structure is accessed is in
spapr.c, so include "vof.h" there, and forward declare the structure
in "spapr.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221213123550.39302-4-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 19fbec7b21482bb47dd4c990143e936692ddfb4f
https://github.com/qemu/qemu/commit/19fbec7b21482bb47dd4c990143e936692ddfb4f
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common: Log which effective address had no TLB entry found
Let's not leave developers in the dark where this log message comes
from.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-2-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: ce216f4aad84fafb1fca527557ab7d5143b97207
https://github.com/qemu/qemu/commit/ce216f4aad84fafb1fca527557ab7d5143b97207
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M target/ppc/mmu_common.c
Log Message:
-----------
target/ppc/mmu_common: Fix table layout of "info tlb" HMP command
Starting with the URWX columns the columns didn't line up.
Before:
QEMU 7.2.50 monitor - type 'help' for more information
(qemu) info tlb
TLB0:
Effective Physical Size TID TS SRWX URWX WIMGE U0123
0x0000000000a80000 0x000000000105d000 4K 117 0 SR--UR-- --M-- U----
0x0000000000100000 0x000000000114e000 4K 117 0 SR--UR-- --M-- U----
<snip
TLB1:
Effective Physical Size TID TS SRWX URWX WIMGE U0123
0x00000000c0000000 0x0000000000000000 16M 0 0 SR-XU--- --M-- U----
0x00000000c1000000 0x0000000001000000 16M 0 0 SRW-U--- --M-- U----
<snip>
(qemu)
After:
QEMU 7.2.50 monitor - type 'help' for more information
(qemu) info tlb
TLB0:
Effective Physical Size TID TS SRWX URWX WIMGE U0123
0x00000000b7a00000 0x000000000fcf5000 4K 18 0 SR-- UR-- --M-- U----
0x0000000000800000 0x000000000fd73000 4K 18 0 SR-- UR-X --M-- U----
<snip>
TLB1:
Effective Physical Size TID TS SRWX URWX WIMGE U0123
0x00000000c0000000 0x0000000000000000 16M 0 0 SR-X U--- --M-- U----
0x00000000c1000000 0x0000000001000000 16M 0 0 SRW- U--- --M-- U----
<snip>
(qemu)
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-3-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 1561bf4e227bbeab0f11eeea7475ad35ac5b71df
https://github.com/qemu/qemu/commit/1561bf4e227bbeab0f11eeea7475ad35ac5b71df
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/ppc/virtex_ml507.c
Log Message:
-----------
hw/ppc/virtex_ml507: Prefer local over global variable
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-4-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 30e1e0c5395fb9eb91afd4eaca635816f55466d2
https://github.com/qemu/qemu/commit/30e1e0c5395fb9eb91afd4eaca635816f55466d2
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Prefer local variable over qdev_get_machine()
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221216145709.271940-5-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 99c6bf195227dc7673eed713c09e9aa66561d67e
https://github.com/qemu/qemu/commit/99c6bf195227dc7673eed713c09e9aa66561d67e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Resolve variable shadowing
Assign to the outer variable instead which even saves some code.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221216145709.271940-6-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: d4eca6043b8d295e64ddf9ed9c6da1783a956a76
https://github.com/qemu/qemu/commit/d4eca6043b8d295e64ddf9ed9c6da1783a956a76
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M hw/ppc/e500.c
Log Message:
-----------
hw/ppc/e500: Move comment to more appropriate place
The TLB entries are set up in mmubooke_create_initial_mapping(), not in
booke206_page_size_to_tlb().
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221216145709.271940-7-shentey@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: 7799c5f2dfc9692d4bb6cb3dad5b5bd8c960438f
https://github.com/qemu/qemu/commit/7799c5f2dfc9692d4bb6cb3dad5b5bd8c960438f
Author: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Implement the DEXCR and HDEXCR
Define the DEXCR and HDEXCR as special purpose registers.
Each register occupies two SPR indicies, one which can be read in an
unprivileged state and one which can be modified in the appropriate
priviliged state, however both indicies refer to the same underlying
value.
Note that the ISA uses the abbreviation UDEXCR in two different
contexts: the userspace DEXCR, the SPR index which can be read from
userspace (implemented in this patch), and the ultravisor DEXCR, the
equivalent register for the ultravisor state (not implemented).
Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221220042330.2387944-2-nicholas@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: bac9fdfd3940f7b79735f85cd3a6dd319365e978
https://github.com/qemu/qemu/commit/bac9fdfd3940f7b79735f85cd3a6dd319365e978
Author: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Check DEXCR on hash{st, chk} instructions
Adds checks to the hashst and hashchk instructions to only execute if
enabled by the relevant aspect in the DEXCR and HDEXCR.
This behaviour is guarded behind TARGET_PPC64 since Power10 is
currently the only implementation which has the DEXCR.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Nicholas Miehlbradt <nicholas@linux.ibm.com>
Message-Id: <20221220042330.2387944-3-nicholas@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit: cb11e2ac35379abcafa405263f9cbb5b3b437c51
https://github.com/qemu/qemu/commit/cb11e2ac35379abcafa405263f9cbb5b3b437c51
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2022-12-20 (Tue, 20 Dec 2022)
Changed paths:
M MAINTAINERS
M docs/system/ppc/ppce500.rst
M hw/ppc/Kconfig
M hw/ppc/e500.c
M hw/ppc/e500.h
M hw/ppc/e500plat.c
M hw/ppc/spapr.c
M hw/ppc/virtex_ml507.c
M hw/sd/sdhci-internal.h
M hw/sd/sdhci.c
M include/hw/ppc/spapr.h
M include/hw/ppc/vof.h
M include/hw/sd/sdhci.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/kvm_ppc.h
M target/ppc/mmu_common.c
M target/ppc/spr_common.h
M target/ppc/translate.c
Log Message:
-----------
Merge tag 'pull-ppc-20221220' of https://gitlab.com/danielhb/qemu into staging
ppc patch queue for 2022-12-20:
This queue contains a MAINTAINERS update, the implementation of the
Freescale eSDHC, the introduction of the DEXCR/HDEXCR instructions and
other assorted fixes (most of them for the e500 board).
# gpg: Signature made Tue 20 Dec 2022 13:40:30 GMT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164
* tag 'pull-ppc-20221220' of https://gitlab.com/danielhb/qemu:
target/ppc: Check DEXCR on hash{st, chk} instructions
target/ppc: Implement the DEXCR and HDEXCR
hw/ppc/e500: Move comment to more appropriate place
hw/ppc/e500: Resolve variable shadowing
hw/ppc/e500: Prefer local variable over qdev_get_machine()
hw/ppc/virtex_ml507: Prefer local over global variable
target/ppc/mmu_common: Fix table layout of "info tlb" HMP command
target/ppc/mmu_common: Log which effective address had no TLB entry found
hw/ppc/spapr: Reduce "vof.h" inclusion
hw/ppc/vof: Do not include the full "cpu.h"
target/ppc/kvm: Add missing "cpu.h" and "exec/hwaddr.h"
hw/ppc/e500: Add Freescale eSDHC to e500plat
hw/sd/sdhci: Support big endian SD host controller interfaces
hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
MAINTAINERS: downgrade PPC KVM/TCG CPUs and pSeries to 'Odd Fixes'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/8540a1f69578...cb11e2ac3537
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