[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] e7a65b: hw/mips/malta: Split FPGA LEDs/ASCII
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] e7a65b: hw/mips/malta: Split FPGA LEDs/ASCII display updates |
|
Date: |
Mon, 16 Jan 2023 06:59:54 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e7a65ba694d84592d190644d8d0ae4ea9137c35d
https://github.com/qemu/qemu/commit/e7a65ba694d84592d190644d8d0ae4ea9137c35d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Split FPGA LEDs/ASCII display updates
No need to refresh the ASCII bar when a LED is toggled
(and vice versa).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-3-philmd@linaro.org>
Commit: 9f81e43f10496bc225a9bbed3d56a26b9f759fd6
https://github.com/qemu/qemu/commit/9f81e43f10496bc225a9bbed3d56a26b9f759fd6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
M hw/mips/trace-events
Log Message:
-----------
hw/mips/malta: Trace FPGA LEDs/ASCII display updates
The FPGA LEDs/ASCII display is mostly used by the bootloader
to show very low-level debug info. QEMU connects its output
to a character device backend, which is not very practical
to correlate with ASM instruction executed, interrupts or
MMIO accesses. Also, the display discard the previous states.
To ease bootloader debugging experience, add a pair of trace
events. Such events can be analyzed over time or diff-ed
between different runs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-4-philmd@linaro.org>
Commit: 65423e6efeac1ee1057870361337c572c941140c
https://github.com/qemu/qemu/commit/65423e6efeac1ee1057870361337c572c941140c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx_pci: Accumulate address space changes
Single registers access in ISD can produce multiple changes
in the address spaces. To reduce computational effort,
accumulate these as a single memory transaction.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-5-philmd@linaro.org>
Commit: 145e2198d749ec09a405f1607a9932499b76f1eb
https://github.com/qemu/qemu/commit/145e2198d749ec09a405f1607a9932499b76f1eb
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE MemoryRegionOps
GT64120's PCI endianness swapping works on little-endian hosts,
but doesn't on big-endian ones. Instead of complicating how
CFGADDR/CFGDATA registers deal with endianness, use the existing
MemoryRegionOps from hw/pci/pci_host.c. Doing so also reduce the
access to internal PCI_HOST_BRIDGE fields.
Map the PCI_HOST_BRIDGE MemoryRegionOps into the corresponding
CFGADDR/CFGDATA regions in the ISD MMIO and remove the unused
code in the current ISD read/write handlers.
Update the mapping when PCI0_CMD register is accessed (in case
the endianness is changed).
This allows using the GT64120 on a big-endian host (and boot
the MIPS Malta machine in little-endian).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-6-philmd@linaro.org>
Commit: 7c032bfbe838c24dcbdc8f9c452553b24f20daad
https://github.com/qemu/qemu/commit/7c032bfbe838c24dcbdc8f9c452553b24f20daad
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/Kconfig
M hw/mips/meson.build
Log Message:
-----------
hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20221209151533.69516-2-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 37e506b69a6791bede30677f05081296f3b77f77
https://github.com/qemu/qemu/commit/37e506b69a6791bede30677f05081296f3b77f77
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M configs/devices/mips-softmmu/common.mak
M hw/mips/Kconfig
M hw/mips/gt64xxx_pci.c
M hw/mips/malta.c
Log Message:
-----------
hw/mips/gt64xxx_pci: Let the GT64120 manage the lower 512MiB hole
Per the comment in the Malta board, the [0x0000.0000-0x2000.0000]
range is decoded by the GT64120, so move the "empty_slot" there.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221209151533.69516-3-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 81ad24762d4295bbe1e2216b21d1e90b81d351a6
https://github.com/qemu/qemu/commit/81ad24762d4295bbe1e2216b21d1e90b81d351a6
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields API
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221220113436.14299-4-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a699b915ded075b6253bebf50ec5dc2040d23612
https://github.com/qemu/qemu/commit/a699b915ded075b6253bebf50ec5dc2040d23612
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx_pci: Add a 'cpu-little-endian' qdev property
This device does not have to be TARGET-dependent.
Add a 'cpu_big_endian' property which sets the byte-swapping
options if required.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221220113436.14299-5-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fae45dd53dcf4029e30b0915efcc62dfd56bdee0
https://github.com/qemu/qemu/commit/fae45dd53dcf4029e30b0915efcc62dfd56bdee0
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Explicit GT64120 endianness upon device creation
Propagate the controller endianess from the machine, setting
the "cpu-little-endian" property.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221209151533.69516-6-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 90f7d0b4940be29259f6977d2df2ca09495680e7
https://github.com/qemu/qemu/commit/90f7d0b4940be29259f6977d2df2ca09495680e7
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/gt64xxx_pci.c
M hw/mips/meson.build
Log Message:
-----------
hw/mips/meson: Make gt64xxx_pci.c endian-agnostic
The single machine using this device explicitly sets its
endianness. We don't need to set a default. This allow us
to remove the target specificity from the build system.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20221209151533.69516-7-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a7db759ef70fdc6ec7e79c603d3daf7c87113bba
https://github.com/qemu/qemu/commit/a7db759ef70fdc6ec7e79c603d3daf7c87113bba
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M MAINTAINERS
M hw/mips/Kconfig
R hw/mips/gt64xxx_pci.c
M hw/mips/meson.build
M hw/mips/trace-events
M hw/pci-host/Kconfig
A hw/pci-host/gt64120.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
Log Message:
-----------
hw/mips/gt64xxx_pci: Move it to hw/pci-host/
The GT-64120 is a north-bridge, and it is not MIPS specific.
Move it with the other north-bridge devices.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221209151533.69516-8-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 14c2b18414ee88a175b4855361dfbdaa836e0491
https://github.com/qemu/qemu/commit/14c2b18414ee88a175b4855361dfbdaa836e0491
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M tests/avocado/machine_mips_malta.py
Log Message:
-----------
tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines
Add quick tests booting YAMON:
$ avocado --show=app,console run -t machine:malta
tests/avocado/machine_mips_malta.py
(1/2)
tests/avocado/machine_mips_malta.py:MaltaMachine.test_mipsel_malta_yamon:
console: YAMON ROM Monitor, Revision 02.22.
console: Copyright (c) 1999-2007 MIPS Technologies, Inc. - All Rights
Reserved.
console: For a list of available commands, type 'help'.
console: Compilation time = May 24 2013 12:16:34 (pburton)
console: Board type/revision = 0x02 (Malta) / 0x00
console: Core board type/revision = 0x01 (CoreLV) / 0x00
console: System controller/revision = Galileo / GT_64120A-B-0
console: FPGA revision = 0x0000
console: MAC address = ff.ff.ff.ff.ff.ff
console: Board S/N = 0123456789
console: PCI bus frequency = 33.33 MHz
console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00
console: Processor ID/revision = 0x93 (MIPS 24Kf) / 0x00
console: Endianness = Little
console: CPU/Bus frequency = 333 MHz / 419 MHz
console: Coherency = None
console: Flash memory size = 4 MByte
console: SDRAM size = 128 MByte
console: First free SDRAM address = 0x800c32f0
console: WARNING: Environment variable flash area is invalid!
console: HINT : Perform "erase -e"
console: YAMON>
PASS (1.88 s)
(2/2)
tests/avocado/machine_mips_malta.py:MaltaMachine.test_mips64el_malta_yamon:
...
console: System controller/revision = Galileo / GT_64120A-B-0
console: Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00
console: Processor ID/revision = 0x82 (MIPS 20Kc) / 0xa0
...
console: YAMON>
PASS (1.89 s)
RESULTS : PASS 2 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 4.57 s
YAMON does some endian-swapped acceses on the ISD<->PCI CFG/DATA
registers. These tests are useful to debug cross-endianness issues,
in particular on big-endian host.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-7-philmd@linaro.org>
Commit: cd5066f8618bc6c80ec9088923c58f4a42ab0e7a
https://github.com/qemu/qemu/commit/cd5066f8618bc6c80ec9088923c58f4a42ab0e7a
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/bootloader.c
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M hw/mips/malta.c
M include/hw/mips/bootloader.h
Log Message:
-----------
hw/mips/bootloader: Handle buffers as opaque arrays
It is irrelevant to the API what the buffers to fill are made of.
In particular, some MIPS ISA have 16-bit wide instructions.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-2-philmd@linaro.org>
Commit: cf386ca8ab20ecad5efa535f3d48750df740da39
https://github.com/qemu/qemu/commit/cf386ca8ab20ecad5efa535f3d48750df740da39
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/bootloader.c
Log Message:
-----------
hw/mips/bootloader: Implement nanoMIPS NOP opcode generator
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221211204533.85359-3-philmd@linaro.org>
Commit: 73be38cbe34df90be4ab9618e62859fa074015ff
https://github.com/qemu/qemu/commit/73be38cbe34df90be4ab9618e62859fa074015ff
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/bootloader.c
Log Message:
-----------
hw/mips/bootloader: Implement nanoMIPS SW opcode generator
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-4-philmd@linaro.org>
Commit: 5d380e4ca898e7f0ebd436e255a7da4869b15a71
https://github.com/qemu/qemu/commit/5d380e4ca898e7f0ebd436e255a7da4869b15a71
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/bootloader.c
Log Message:
-----------
hw/mips/bootloader: Implement nanoMIPS LI (LUI+ORI) opcode generator
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-5-philmd@linaro.org>
Commit: 9356a2d2be024480aa7f65a598f8c8283f04faa8
https://github.com/qemu/qemu/commit/9356a2d2be024480aa7f65a598f8c8283f04faa8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/bootloader.c
Log Message:
-----------
hw/mips/bootloader: Implement nanoMIPS JALRc opcode generator
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-6-philmd@linaro.org>
Commit: 391a2bdae99cb09e2cf88337898cb53385bddcc1
https://github.com/qemu/qemu/commit/391a2bdae99cb09e2cf88337898cb53385bddcc1
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (1/5)
Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
helper to set BAR registers") converted write_bootloader(), convert
the equivalent write_bootloader_nanomips(), allowing us to modify
the bootloader code more easily in the future.
Part 1/5: Convert PCI0 MEM1 BAR setup
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-7-philmd@linaro.org>
Commit: 262502a681e3e7efc54feb93a660a768c68e3395
https://github.com/qemu/qemu/commit/262502a681e3e7efc54feb93a660a768c68e3395
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)
Part 2/5: Convert PCI0 MEM0 BAR setup
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-8-philmd@linaro.org>
Commit: 02e0bec464ff3086446d4ad938e301bd85e57d89
https://github.com/qemu/qemu/commit/02e0bec464ff3086446d4ad938e301bd85e57d89
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)
Part 3/5: Convert PCI0 I/O BAR setup
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-9-philmd@linaro.org>
Commit: 3265f41fc7d988276c672e4bdc46ae60713f141c
https://github.com/qemu/qemu/commit/3265f41fc7d988276c672e4bdc46ae60713f141c
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)
Part 4/5: Convert GT64120 ISD base address setup
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-10-philmd@linaro.org>
Commit: 9f911a25277aceaad14dc1ce4ac330ad5b057d70
https://github.com/qemu/qemu/commit/9f911a25277aceaad14dc1ce4ac330ad5b057d70
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)
Part 5/5: Convert jumping to kernel
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-11-philmd@linaro.org>
Commit: 0e45355c5cf0f4ec88b5484c3bf2574bdc9c4e48
https://github.com/qemu/qemu/commit/0e45355c5cf0f4ec88b5484c3bf2574bdc9c4e48
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()
Merge common code shared between write_bootloader() and
write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-12-philmd@linaro.org>
Commit: 6dd92ce6c541d331f384b808173b7c97c09c8684
https://github.com/qemu/qemu/commit/6dd92ce6c541d331f384b808173b7c97c09c8684
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition
The PIIX4 PCI-ISA bridge function is always located at 10:0.
Since we want to re-use its address, add the PIIX4_PCI_DEVFN
definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221027204720.33611-2-philmd@linaro.org>
Commit: 1953dfa80e0fc44a8ccfc97b4ada941e9383bba7
https://github.com/qemu/qemu/commit/1953dfa80e0fc44a8ccfc97b4ada941e9383bba7
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/malta.c
Log Message:
-----------
hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
Linux kernel expects the northbridge & southbridge chipsets
configured by the BIOS firmware. We emulate that by writing
a tiny bootloader code in write_bootloader().
Upon introduction in commit 5c2b87e34d ("PIIX4 support"),
the PIIX4 configuration space included values specific to
the Malta board.
Set the Malta-specific IRQ routing values in the embedded
bootloader, so the next commit can remove the Malta specific
bits from the PIIX4 PCI-ISA bridge and make it generic
(matching the real hardware).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221027204720.33611-3-philmd@linaro.org>
Commit: c12b1e67d50c01f6ba78abcdaaa533abaf71b664
https://github.com/qemu/qemu/commit/c12b1e67d50c01f6ba78abcdaaa533abaf71b664
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Correct IRQRC[A:D] reset values
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221027204720.33611-4-philmd@linaro.org>
Commit: a844873512400fae6bed9e87694dc96ff2f15f39
https://github.com/qemu/qemu/commit/a844873512400fae6bed9e87694dc96ff2f15f39
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/mips/malta.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/sysemu/addr.c
M target/mips/sysemu/physaddr.c
Log Message:
-----------
mips: Remove support for trap and emulate KVM
This support was limited to the Malta board, drop it.
I do not have a machine that can run VZ KVM, so I am assuming
that it works for -M malta as well.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221221091718.71844-1-philmd@linaro.org>
Commit: f9950374300cb4d8d898bbfc694a0639e9aafdc3
https://github.com/qemu/qemu/commit/f9950374300cb4d8d898bbfc694a0639e9aafdc3
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M disas/meson.build
M include/exec/poison.h
M meson.build
M target/mips/cpu.c
Log Message:
-----------
mips: Always include nanomips disassembler
Since the nanomips disassembler is not C++ code anymore, it need not
depend on link_language == cpp. Always include it and remove the
CONFIG_NANOMIPS_DIS symbol.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20230110084942.299460-1-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 1bdad09bf3326b89add221ef092e57ed81f6e347
https://github.com/qemu/qemu/commit/1bdad09bf3326b89add221ef092e57ed81f6e347
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/pci/pci_host.c
Log Message:
-----------
hw/pci/pci_host: Trace config accesses on unexisting functions
Currently we only emit trace events for existing PCI functions.
In order to ease debugging PCI enumeration process, also emit
for unexisting functions:
$ qemu-system-foo -trace pci_cfg_\*
...
pci_cfg_read empty 00:0a.4 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0a.5 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0a.6 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0a.7 @0x0 -> 0xffffffff
pci_cfg_read pcnet 00:0b.0 @0x0 -> 0x20001022
pci_cfg_read empty 00:0c.0 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0d.0 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0e.0 @0x0 -> 0xffffffff
pci_cfg_read empty 00:0f.0 @0x0 -> 0xffffffff
pci_cfg_read empty 00:10.0 @0x0 -> 0xffffffff
pci_cfg_read empty 00:11.0 @0x0 -> 0xffffffff
pci_cfg_read cirrus-vga 00:12.0 @0x0 -> 0xb81013
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230104133935.4639-2-philmd@linaro.org>
Commit: f021f4e9d269746bc89dadf0cac117154733e4be
https://github.com/qemu/qemu/commit/f021f4e9d269746bc89dadf0cac117154733e4be
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/i386/pc_q35.c
M hw/isa/piix3.c
M hw/isa/piix4.c
M hw/pci-host/raven.c
M hw/pci-host/versatile.c
M hw/pci/pci.c
M hw/remote/machine.c
M hw/remote/vfio-user-obj.c
M include/hw/pci/pci.h
Log Message:
-----------
hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()
pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and
pci_map_irq_fn to a PCI bus. This coupling gets in the way when the
pci_map_irq_fn is board-specific while the pci_set_irq_fn is device-
specific.
For example, both of QEMU's PIIX south bridge models have different
pci_map_irq_fn implementations which are board-specific rather than
device-specific. These implementations should therefore reside in board
code. The pci_set_irq_fn's, however, should stay in the device models
because they access memory internal to the model.
Factoring out pci_bus_map_irqs() from pci_bus_irqs() allows the
assignments to be decoupled, resolving the problem described above.
Note also how pci_vpb_realize() which gets touched in this commit
assigns different pci_map_irq_fn's depending on the board.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230109172347.1830-5-shentey@gmail.com>
[PMD: Factor out in vfu_object_set_bus_irq()]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 738c2eb47f2fb150a337b6bfb151f4339d0bb8b3
https://github.com/qemu/qemu/commit/738c2eb47f2fb150a337b6bfb151f4339d0bb8b3
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/isa/piix3.c
Log Message:
-----------
hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific
pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's
pci_slot_get_pirq() to board code to not have PIIX3 make assuptions
about its board.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230109172347.1830-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 3c73d590e7b20c58061cc7a67ecc6e3f5bf39192
https://github.com/qemu/qemu/commit/3c73d590e7b20c58061cc7a67ecc6e3f5bf39192
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/isa/piix4.c
M hw/mips/malta.c
Log Message:
-----------
hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific
pci_map_irq_fn's in general seem to be board-specific, and PIIX4's
pci_slot_get_pirq() in particular seems very Malta-specific. So move the
latter to malta.c to 1/ keep the board logic in one place and 2/ avoid
PIIX4 to make assumptions about its board.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230109172347.1830-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: c451e07798e3640bed992cb43d8d867ef0ae1f4a
https://github.com/qemu/qemu/commit/c451e07798e3640bed992cb43d8d867ef0ae1f4a
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M configs/devices/mips-softmmu/common.mak
M hw/mips/Kconfig
Log Message:
-----------
hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
Tracking dependencies via Kconfig seems much cleaner.
Note that PIIX4 already depends on ACPI_PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230109172347.1830-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: f0712099a29aba335fd1dbf4b19811ad0f57d095
https://github.com/qemu/qemu/commit/f0712099a29aba335fd1dbf4b19811ad0f57d095
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/isa/piix4.c
M hw/usb/hcd-uhci.c
M hw/usb/hcd-uhci.h
Log Message:
-----------
hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20221204190553.3274-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2aaf0ec7ff239523ce2c8d913b120202c219af3e
https://github.com/qemu/qemu/commit/2aaf0ec7ff239523ce2c8d913b120202c219af3e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/intc/i8259.c
M include/hw/intc/i8259.h
M include/qemu/typedefs.h
Log Message:
-----------
hw/intc/i8259: Make using the isa_pic singleton more type-safe
This even spares some casts in hot code paths along the way.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230109172347.1830-10-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2b85e0cda4b066010efda63a2d2359872ba07a04
https://github.com/qemu/qemu/commit/2b85e0cda4b066010efda63a2d2359872ba07a04
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/i386/kvm/i8259.c
M hw/i386/kvm/ioapic.c
M hw/intc/apic.c
M hw/intc/apic_common.c
A hw/intc/kvm_irqcount.c
M hw/intc/meson.build
M hw/intc/trace-events
M hw/rtc/mc146818rtc.c
M include/hw/i386/apic.h
M include/hw/i386/apic_internal.h
A include/hw/intc/kvm_irqcount.h
Log Message:
-----------
hw/intc: Extract the IRQ counting functions into a separate file
These IRQ counting functions will soon be required in binaries that
do not include the APIC code, too, so let's extract them into a
separate file that can be linked independently of the APIC code.
While we're at it, change the apic_* prefix into kvm_* since the
functions are used from the i8259 PIC (i.e. not the APIC), too.
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230110095351.611724-2-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: aae167211fb326784b323b87a0e4c0fa832940b3
https://github.com/qemu/qemu/commit/aae167211fb326784b323b87a0e4c0fa832940b3
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/core/qdev-properties-system.c
Log Message:
-----------
hw/core/qdev-properties-system: Allow the 'slew' policy only on x86
The 'slew' tick policy is currently enforced to be only available on
x86 via some "#ifdef TARGET_I386" statements in mc146818rtc.c. We
want to get rid of those #ifdefs, so we need a different way of
checking whether the policy is allowed or not. Using the setter
function in hw/core/qdev-properties-system.c seems to be a good
place, so let's add a check here.
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20230110095351.611724-3-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e896d849331eb853cf3b7df6a24be279ae9a421d
https://github.com/qemu/qemu/commit/e896d849331eb853cf3b7df6a24be279ae9a421d
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/rtc/mc146818rtc.c
M hw/rtc/meson.build
M include/hw/rtc/mc146818rtc.h
Log Message:
-----------
hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent
The only reason for this code being target dependent was the IRQ-counting
related code in rtc_policy_slew_deliver_irq(). Since these functions have
been moved into a new, separate file (kvm_irqcount.c) which is now always
compiled and linked if necessary, we can get rid of the #ifdef TARGET_I386
switches in mc146818rtc.c and declare it in the softmmu_ss instead of
specific_ss, so that the code only gets compiled once for all targets.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230110095351.611724-4-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: e8dc34196b2a81b21469f6d95afc390ef645e63b
https://github.com/qemu/qemu/commit/e8dc34196b2a81b21469f6d95afc390ef645e63b
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M softmmu/rtc.c
Log Message:
-----------
softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818
The 'slew' lost tick policy is only available on systems with a mc146818
RTC. On other systems, "-rtc driftfix=slew" is currently silently ignored.
Let's emit at least a warning in this case to make the users aware that
there is something wrong in their command line settings.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230110095351.611724-5-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4dd5cb5d847ed887dd0a00c602b08bade6f6ffa2
https://github.com/qemu/qemu/commit/4dd5cb5d847ed887dd0a00c602b08bade6f6ffa2
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/pci-host/bonito.c
Log Message:
-----------
hw/pci-host/bonito: Convert to 3-phase reset
Convert the TYPE_PCI_BONITO class to use 3-phase reset.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230105130710.49264-2-philmd@linaro.org>
Commit: f9ab9c6e2b6091f1be519852eb2552a96e800a78
https://github.com/qemu/qemu/commit/f9ab9c6e2b6091f1be519852eb2552a96e800a78
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/pci-host/bonito.c
Log Message:
-----------
hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito_pcihost* as
bonito_host*.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230105130710.49264-3-philmd@linaro.org>
Commit: eb66dac46da958c0ba20a2803344b20c8f79c48b
https://github.com/qemu/qemu/commit/eb66dac46da958c0ba20a2803344b20c8f79c48b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/pci-host/bonito.c
Log Message:
-----------
hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito* as bonito_pci*.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230105130710.49264-4-philmd@linaro.org>
Commit: aad07969bb3bd7771678143119e53b86829f8746
https://github.com/qemu/qemu/commit/aad07969bb3bd7771678143119e53b86829f8746
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M MAINTAINERS
M hw/pci-host/bonito.c
A include/hw/pci-host/bonito.h
Log Message:
-----------
hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header
Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a
header to be able to access it from board code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230105130710.49264-8-philmd@linaro.org>
Commit: 026334610f40fe8c0abac9565eddee1d6cc99de7
https://github.com/qemu/qemu/commit/026334610f40fe8c0abac9565eddee1d6cc99de7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'
Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instance in create_fdt() where we're calling it 'mc'.
Cc: Paul Burton <paulburton@kernel.org>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20230111172133.334735-1-dbarboza@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 6ba97c48a64d059ddfa5400330dfaf5982f5f2c8
https://github.com/qemu/qemu/commit/6ba97c48a64d059ddfa5400330dfaf5982f5f2c8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M target/mips/cpu.c
M target/mips/sysemu/meson.build
A target/mips/sysemu/mips-qmp-cmds.c
Log Message:
-----------
target/mips: Restrict 'qapi-commands-machine.h' to system emulation
Since commit a0e61807a3 ("qapi: Remove QMP events and commands from
user-mode builds") we don't generate the "qapi-commands-machine.h"
header in a user-emulation-only build.
Extract the QMP functions from cpu.c (which is always compiled) to
the new 'sysemu/mips-qmp-cmds.c' unit (which is only compiled when
system emulation is selected).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221219211034.70491-4-philmd@linaro.org>
Commit: 4828656f65324249273ad2f2db80844ba90eeb9b
https://github.com/qemu/qemu/commit/4828656f65324249273ad2f2db80844ba90eeb9b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-01-13 (Fri, 13 Jan 2023)
Changed paths:
M scripts/git.orderfile
Log Message:
-----------
scripts/git.orderfile: Display MAINTAINERS changes first
If we get custom to see MAINTAINERS changes first,
we might catch missing MAINTAINERS updates easier.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221216225505.26052-1-philmd@linaro.org>
Commit: a8d6abe1292e1db1ad9be5b2b124b9c01bcda094
https://github.com/qemu/qemu/commit/a8d6abe1292e1db1ad9be5b2b124b9c01bcda094
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-01-16 (Mon, 16 Jan 2023)
Changed paths:
M MAINTAINERS
M configs/devices/mips-softmmu/common.mak
M disas/meson.build
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/core/qdev-properties-system.c
M hw/i386/kvm/i8259.c
M hw/i386/kvm/ioapic.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M hw/intc/i8259.c
A hw/intc/kvm_irqcount.c
M hw/intc/meson.build
M hw/intc/trace-events
M hw/isa/piix3.c
M hw/isa/piix4.c
M hw/mips/Kconfig
M hw/mips/bootloader.c
M hw/mips/boston.c
M hw/mips/fuloong2e.c
R hw/mips/gt64xxx_pci.c
M hw/mips/malta.c
M hw/mips/meson.build
M hw/mips/trace-events
M hw/pci-host/Kconfig
M hw/pci-host/bonito.c
A hw/pci-host/gt64120.c
M hw/pci-host/meson.build
M hw/pci-host/raven.c
M hw/pci-host/trace-events
M hw/pci-host/versatile.c
M hw/pci/pci.c
M hw/pci/pci_host.c
M hw/remote/machine.c
M hw/remote/vfio-user-obj.c
M hw/rtc/mc146818rtc.c
M hw/rtc/meson.build
M hw/usb/hcd-uhci.c
M hw/usb/hcd-uhci.h
M include/exec/poison.h
M include/hw/i386/apic.h
M include/hw/i386/apic_internal.h
M include/hw/intc/i8259.h
A include/hw/intc/kvm_irqcount.h
M include/hw/mips/bootloader.h
A include/hw/pci-host/bonito.h
M include/hw/pci/pci.h
M include/hw/rtc/mc146818rtc.h
M include/qemu/typedefs.h
M meson.build
M scripts/git.orderfile
M softmmu/rtc.c
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/kvm.c
M target/mips/sysemu/addr.c
M target/mips/sysemu/meson.build
A target/mips/sysemu/mips-qmp-cmds.c
M target/mips/sysemu/physaddr.c
M tests/avocado/machine_mips_malta.py
Log Message:
-----------
Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging
MIPS patches queue
A bunch of cleanups from various people.
- Improved GT64120 on big-endian hosts
- GT64120 north bridge and MC146818 RTC devices are now target independent
- Bonito64 north bridge converted to 3-phase reset API
- PCI refactors around PIIX devices
- Support for nanoMIPS in bootloader generator API
- New YAMON Malta Avocado test
- Removal of 'trap and emulate' KVM support
- System-specific QMP commands restricted to system emulation
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t
# wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww
# qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq
# 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL
# 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0
# v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn
# DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0
# 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A
# WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn
# 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O
# eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y
# w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY=
# =oXX+
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits)
scripts/git.orderfile: Display MAINTAINERS changes first
target/mips: Restrict 'qapi-commands-machine.h' to system emulation
hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'
hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header
hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code
hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code
hw/pci-host/bonito: Convert to 3-phase reset
softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818
hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent
hw/core/qdev-properties-system: Allow the 'slew' policy only on x86
hw/intc: Extract the IRQ counting functions into a separate file
hw/intc/i8259: Make using the isa_pic singleton more type-safe
hw/usb/hcd-uhci: Introduce TYPE_ defines for device models
hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig
hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific
hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific
hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()
hw/pci/pci_host: Trace config accesses on unexisting functions
mips: Always include nanomips disassembler
mips: Remove support for trap and emulate KVM
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/886fb67020e3...a8d6abe1292e