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[Qemu-commits] [qemu/qemu] 753ae9: hw/char: riscv_htif: Avoid using magi
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 753ae9: hw/char: riscv_htif: Avoid using magic numbers |
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Date: |
Sat, 21 Jan 2023 05:01:47 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 753ae97abc7459e69d48712355118fb54268f8cb
https://github.com/qemu/qemu/commit/753ae97abc7459e69d48712355118fb54268f8cb
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char: riscv_htif: Avoid using magic numbers
The Spike HTIF is poorly documented. The only relevant info we can
get from the internet is from Andrew Waterman at [1].
Add a comment block before htif_handle_tohost_write() to explain
the tohost register format, and use meaningful macros instead of
magic numbers in the codes.
While we are here, correct 2 multi-line comment blocks that have
wrong format.
Link:
https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754
[1]
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bc9c3b18626fbfe9eb8f37438b5fbb2f901c2460
https://github.com/qemu/qemu/commit/bc9c3b18626fbfe9eb8f37438b5fbb2f901c2460
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M include/hw/char/riscv_htif.h
Log Message:
-----------
hw/char: riscv_htif: Drop {to, from}host_size in HTIFState
These are not used anywhere. Drop them.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-3-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dc6882464161a7bf77c8b847cef6d4f2f9066361
https://github.com/qemu/qemu/commit/dc6882464161a7bf77c8b847cef6d4f2f9066361
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
Log Message:
-----------
hw/char: riscv_htif: Drop useless assignment of memory region
struct HTIFState has 3 members for address space and memory region,
and are initialized during htif_mm_init(). But they are actually
useless. Drop them.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-4-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: dadee9e3ce6ee6aad36fe3027eaa0f947358f812
https://github.com/qemu/qemu/commit/dadee9e3ce6ee6aad36fe3027eaa0f947358f812
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char: riscv_htif: Use conventional 's' for HTIFState
QEMU source codes tend to use 's' to represent the hardware state.
Let's use it for HTIFState.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-5-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1237c2d6942709cf82b999b6f6e8624b86ac495f
https://github.com/qemu/qemu/commit/1237c2d6942709cf82b999b6f6e8624b86ac495f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
M target/riscv/cpu.h
M target/riscv/machine.c
Log Message:
-----------
hw/char: riscv_htif: Move registers from CPUArchState to HTIFState
At present for some unknown reason the HTIF registers (fromhost &
tohost) are defined in the RISC-V CPUArchState. It should really
be put in the HTIFState struct as it is only meaningful to HTIF.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 03ef1899dd1194d58d51f41491ba24c87f901264
https://github.com/qemu/qemu/commit/03ef1899dd1194d58d51f41491ba24c87f901264
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M include/hw/char/riscv_htif.h
Log Message:
-----------
hw/char: riscv_htif: Remove forward declarations for non-existent variables
There are forward declarations for 'vmstate_htif' and 'htif_io_ops'
in riscv_htif.h however there are no definitions in the C codes.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-7-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a6e13e31d5c34d59c28e908f3e51cf87bc82666f
https://github.com/qemu/qemu/commit/a6e13e31d5c34d59c28e908f3e51cf87bc82666f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
Log Message:
-----------
hw/char: riscv_htif: Support console output via proxy syscall
At present the HTIF proxy syscall is unsupported. On RV32, only
device 0 is supported so there is no console device for RV32.
The only way to implement console funtionality on RV32 is to
support the SYS_WRITE syscall.
With this commit, the Spike machine is able to boot the 32-bit
OpenSBI generic image.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-8-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a8a7f680d25a6dc52b1a56a597563a6d6be5f8da
https://github.com/qemu/qemu/commit/a8a7f680d25a6dc52b1a56a597563a6d6be5f8da
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv: spike: Remove the out-of-date comments
Spike machine now supports OpenSBI plain binary bios image, so the
comments are no longer valid.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-9-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 808faef7cd38222ac02e5876e5170c7d00982876
https://github.com/qemu/qemu/commit/808faef7cd38222ac02e5876e5170c7d00982876
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: make riscv_find_firmware() static
The only caller is riscv_find_and_load_firmware(), which is in the same
file.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-10-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9d3f7108bc43e93ceef7faa27c87eea8295c33ed
https://github.com/qemu/qemu/commit/9d3f7108bc43e93ceef7faa27c87eea8295c33ed
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: introduce riscv_default_firmware_name()
Some boards are duplicating the 'riscv_find_and_load_firmware' call
because the 32 and 64 bits images have different names. Create
a function to handle this detail instead of hardcoding it in the boards.
Ideally we would bake this logic inside riscv_find_and_load_firmware(),
or even create a riscv_load_default_firmware(), but at this moment we
cannot infer whether the machine is running 32 or 64 bits without
accessing RISCVHartArrayState, which in turn can't be accessed via the
common code from boot.c. In the end we would exchange 'firmware_name'
for a flag with riscv_is_32bit(), which isn't much better than what we
already have today.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 8f6196266e607a4a014ef1a5ab05b93343f678df
https://github.com/qemu/qemu/commit/8f6196266e607a4a014ef1a5ab05b93343f678df
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: Introduce riscv_find_firmware()
Rename previous riscv_find_firmware() to riscv_find_bios(), and
introduce a new riscv_find_firmware() to implement the first half
part of the work done in riscv_find_and_load_firmware().
This new API is helpful for machine that wants to know the final
chosen firmware file name but does not want to load it.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-12-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 71d68c48be96366fb89f7a2dd9d82dd86bcbe542
https://github.com/qemu/qemu/commit/71d68c48be96366fb89f7a2dd9d82dd86bcbe542
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/spike.c
M include/hw/char/riscv_htif.h
Log Message:
-----------
hw/riscv: spike: Decouple create_fdt() dependency to ELF loading
At present create_fdt() calls htif_uses_elf_symbols() to determine
whether to insert a <reg> property for the HTIF. This unfortunately
creates a hidden dependency to riscv_load_{firmware,kernel} that
create_fdt() must be called after the ELF {firmware,kernel} image
has been loaded.
Decouple such dependency be adding a new parameter to create_fdt(),
whether custom HTIF base address is used. The flag will be set if
non ELF {firmware,kernel} image is given by user.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 44e7372b213bad4e4589d765f011b25c897c8ab1
https://github.com/qemu/qemu/commit/44e7372b213bad4e4589d765f011b25c897c8ab1
Author: Dongxue Zhang <elta.era@gmail.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: Fix elen check
The elen check should be cpu->cfg.elen in range [8, 64].
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <167236721596.15277.2653405273227256289-0@git.sr.ht>
[ Changes by AF:
- Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: db2b9a59ca633602c4a18474a104182920858060
https://github.com/qemu/qemu/commit/db2b9a59ca633602c4a18474a104182920858060
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
A tests/avocado/riscv_opensbi.py
Log Message:
-----------
tests/avocado: add RISC-V OpenSBI boot test
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:
(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
SKIP: requires OpenSBI fix to work
[1]
https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3139929da4da015f372c11f9e9e1f2538f9767ed
https://github.com/qemu/qemu/commit/3139929da4da015f372c11f9e9e1f2538f9767ed
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/spike.c
M include/hw/riscv/spike.h
Log Message:
-----------
hw/riscv/spike: use 'fdt' from MachineState
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 60c7dfa2a3d7eb3919054367c2d03d4fc1bef3f1
https://github.com/qemu/qemu/commit/60c7dfa2a3d7eb3919054367c2d03d4fc1bef3f1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/sifive_u.c
M include/hw/riscv/sifive_u.h
Log Message:
-----------
hw/riscv/sifive_u: use 'fdt' from MachineState
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1db0c57adeb981c9581f7729e8e8dfb60bdb4e7c
https://github.com/qemu/qemu/commit/1db0c57adeb981c9581f7729e8e8dfb60bdb4e7c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
Log Message:
-----------
hw/riscv/boot.c: exit early if filename is NULL in load functions
riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works
under the assumption that a 'filename' parameter is always not NULL.
This is currently the case since all callers of these functions are
checking for NULL before calling them. Add an g_assert() to make sure
that a NULL value in these cases are to be considered a bug.
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c44df400d9fc23d1d135f6aa723cb58ada858ee3
https://github.com/qemu/qemu/commit/c44df400d9fc23d1d135f6aa723cb58ada858ee3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv/spike.c: load initrd right after riscv_load_kernel()
This will make the code more in line with what the other boards are
doing. We'll also avoid an extra check to machine->kernel_filename since
we already checked that before executing riscv_load_kernel().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b9a65476cbfc7a47a5c06ffdd58922fd295c5027
https://github.com/qemu/qemu/commit/b9a65476cbfc7a47a5c06ffdd58922fd295c5027
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
riscv_load_initrd() returns the initrd end addr while also writing a
'start' var to mark the addr start. These informations are being used
just to write the initrd FDT node. Every existing caller of
riscv_load_initrd() is writing the FDT in the same manner.
We can simplify things by writing the FDT inside riscv_load_initrd(),
sparing callers from having to manage start/end addrs to write the FDT
themselves.
An 'if (fdt)' check is already inserted at the end of the function
because we'll end up using it later on with other boards that doesn´t
have a FDT.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b1f19f238cae53b5c90085db45e0335af19f5387
https://github.com/qemu/qemu/commit/b1f19f238cae53b5c90085db45e0335af19f5387
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
The sifive_u, spike and virt machines are writing the 'bootargs' FDT
node during their respective create_fdt().
Given that bootargs is written only when '-append' is used, and this
option is only allowed with the '-kernel' option, which in turn is
already being check before executing riscv_load_kernel(), write
'bootargs' in the same code path as riscv_load_kernel().
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1f99146103dc49aabfa832f8527804087a4c2651
https://github.com/qemu/qemu/commit/1f99146103dc49aabfa832f8527804087a4c2651
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: use MachineState in riscv_load_initrd()
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 60c1f05e365e08cbdc6a9a64e29a109903a32ee6
https://github.com/qemu/qemu/commit/60c1f05e365e08cbdc6a9a64e29a109903a32ee6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/boot.h
Log Message:
-----------
hw/riscv/boot.c: use MachineState in riscv_load_kernel()
All callers are using kernel_filename as machine->kernel_filename.
This will also simplify the changes in riscv_load_kernel() that we're
going to do next.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c66ffcd5358ba88e93e1ffb15ae42ca52dab12a8
https://github.com/qemu/qemu/commit/c66ffcd5358ba88e93e1ffb15ae42ca52dab12a8
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu: set cpu->cfg in register_cpu_props()
There is an informal contract between the cpu_init() functions and
riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the
default settings were loaded via register_cpu_props() and do validations
to set env.misa_ext. If it's not zero, skip this whole process and
assume that the board somehow did everything.
At this moment, all SiFive CPUs are setting a non-zero misa_ext during
their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This
causes problems when the code being skipped in riscv_cpu_realize()
contains fixes or assumptions that affects all CPUs, meaning that SiFive
CPUs are missing out.
To allow this code to not be skipped anymore, all the cpu->cfg.ext_*
attributes needs to be set during cpu_init() time. At this moment this
is being done in register_cpu_props(). The SiFive boards are setting
their own extensions during cpu_init() though, meaning that they don't
want all the defaults from register_cpu_props().
Let's move the contract between *_cpu_init() and riscv_cpu_realize() to
register_cpu_props(). Inside this function we'll check if
cpu->env.misa_ext was set and, if that's the case, set all relevant
cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case
as is today, i.e. loading all the defaults from riscv_cpu_extensions[].
register_cpu_props() can then be called by all the cpu_init() functions,
including the SiFive ones. This will make all CPUs behave more in line
with what riscv_cpu_realize() expects.
This will also make the cpu_init() functions even more alike, but at this
moment we would need some design changes in how we're initializing
extensions/attributes (e.g. some CPUs are setting cfg options after
register_cpu_props(), so we can't simply add the function to a common
post_init() hook) to make a common cpu_init() code across all CPUs.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5ab1095213318effd9bb4667f7f52da21f81acc6
https://github.com/qemu/qemu/commit/5ab1095213318effd9bb4667f7f52da21f81acc6
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
All RISCV CPUs are setting cpu->cfg during their cpu_init() functions,
meaning that there's no reason to skip all the misa validation and setup
if misa_ext was set beforehand - especially since we're setting an
updated value in set_misa() in the end.
Put this code chunk into a new riscv_cpu_validate_set_extensions()
helper and always execute it regardless of what the board set in
env->misa_ext.
This will put more responsibility in how each board is going to init
their attributes and extensions if they're not using the defaults.
It'll also allow realize() to do its job looking only at the extensions
enabled per se, not corner cases that some CPUs might have, and we won't
have to change multiple code paths to fix or change how extensions work.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com>
[ Changes by AF:
- Rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 877a3a3732dcd45b09b96a6ff9655f6a2e19540f
https://github.com/qemu/qemu/commit/877a3a3732dcd45b09b96a6ff9655f6a2e19540f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Use TARGET_FMT_lx for env->mhartid
env->mhartid is currently casted to long before printed, which drops
the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230109152655.340114-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5dfe23774de34700337d66fc25b6313b65c34ad7
https://github.com/qemu/qemu/commit/5dfe23774de34700337d66fc25b6313b65c34ad7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv/spike.c: simplify create_fdt()
'mem_size' and 'cmdline' are unused.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: cdb785683ada2055f8f47ae154d0ce43f97d7a87
https://github.com/qemu/qemu/commit/cdb785683ada2055f8f47ae154d0ce43f97d7a87
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: simplify create_fdt()
'mem_size' and 'cmdline' aren't being used. Remove them.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f5be2ccb43d3d8466f15f53b82f5fdba1684fc56
https://github.com/qemu/qemu/commit/f5be2ccb43d3d8466f15f53b82f5fdba1684fc56
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/sifive_u.c
Log Message:
-----------
hw/riscv/sifive_u.c: simplify create_fdt()
'cmdline' isn't being used. Remove it.
A MachineState pointer is being retrieved via a MACHINE() macro calling
qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev().
'mem_size' is being set as machine->ram_size by the caller. Retrieve it
via ms->ram_size.
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 914c97f968cc70be5275fd230d38f99882896032
https://github.com/qemu/qemu/commit/914c97f968cc70be5275fd230d38f99882896032
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
create_fdt_socket_cpus() writes a different 'mmu-type' value if we're
running in 32 or 64 bits. However, the flag is being calculated during
virt_machine_init(), and is passed around in create_fdt(), then
create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of
the intermediate functions are using the flag, which is a bit
misleading.
Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it
using the already available RISCVVirtState pointer. This will also
change the signature of create_fdt_socket() and create_fdt(), making it
clear that these functions don't do anything special when we're running
in 32 bit mode.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fb60b488cf5027c8134f1ce0c1df9b6bdd3b9276
https://github.com/qemu/qemu/commit/fb60b488cf5027c8134f1ce0c1df9b6bdd3b9276
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/numa.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/numa.h
Log Message:
-----------
hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
There's no need to use a MachineState pointer and a fdt pointer now that
all RISC-V machines are using the FDT from the MachineState.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9c3ee7e84781909d5a114350c35554f0886491ba
https://github.com/qemu/qemu/commit/9c3ee7e84781909d5a114350c35554f0886491ba
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/numa.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/numa.h
Log Message:
-----------
hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
There's no need to use a MachineState pointer and a fdt pointer now that
all RISC-V machines are using the FDT from the MachineState.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 06d85c24c28f42a57680dc21955e343f58d93089
https://github.com/qemu/qemu/commit/06d85c24c28f42a57680dc21955e343f58d93089
Author: Andrew Bresticker <abrestic@rivosinc.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix up masking of vsip/vsie accesses
The current logic attempts to shift the VS-level bits into their correct
position in mip while leaving the remaining bits in-tact. This is both
pointless and likely incorrect since one would expect that any new, future
VS-level interrupts will get their own position in mip rather than sharing
with their (H)S-level equivalent. Fix this, and make the logic more
readable, by just making off the VS-level bits and shifting them into
position.
This also fixes reads of vsip, which would only ever report vsip.VSSIP
since the non-writable bits got masked off as well.
Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts
on RV32")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e471a8c9850f1af0c1bc5768ca28285348cdd6c5
https://github.com/qemu/qemu/commit/e471a8c9850f1af0c1bc5768ca28285348cdd6c5
Author: Andrew Bresticker <abrestic@rivosinc.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
Per the AIA specification, writes to stimecmp from VS level should
trap when hvictl.VTI is set since the write may cause vsip.STIP to
become unset.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9d9db41373a256c5ae011c1428d26d2597a77484
https://github.com/qemu/qemu/commit/9d9db41373a256c5ae011c1428d26d2597a77484
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
We failed to update this with the w^x split, so misses the fact
that true pc-relative offsets are usually small.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3ceeb19a53e51c0c6310d760d26dca08145797c5
https://github.com/qemu/qemu/commit/3ceeb19a53e51c0c6310d760d26dca08145797c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Introduce helper_set_rounding_mode_chkfrm
The new helper always validates the contents of FRM, even
if the new rounding mode is not DYN. This is required by
the vector unit.
Track whether we've validated FRM separately from whether
we've updated fp_status with a given rounding mode, so that
we can elide calls correctly.
This partially reverts d6c4d3f2a69 which attempted the to do
the same thing, but with two calls to gen_set_rm(), which is
both inefficient and tickles an assertion in decode_save_opc.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f251c01a623e0c998a2127f8648d4d02cd04e702
https://github.com/qemu/qemu/commit/f251c01a623e0c998a2127f8648d4d02cd04e702
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Remove helper_set_rod_rounding_mode
The only setting of RISCV_FRM_ROD is from the vector unit,
and now handled by helper_set_rounding_mode_chkfrm.
This helper is now unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b748352c555b42d497fe8ee00ee2e44eb8627660
https://github.com/qemu/qemu/commit/b748352c555b42d497fe8ee00ee2e44eb8627660
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()
Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier")
moved the initialization of fw_cfg to the virt_machine_done() callback.
Problem is that the validation of fw_cfg by devices such as ramfb is
done before the machine done notifier is called. Moving create_fw_cfg()
to machine_done() results in QEMU failing to boot when using a ramfb
device:
./qemu-system-riscv64 -machine virt -device ramfb -serial stdio
qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA
The fix is simple: move create_fw_cfg() config back to
virt_machine_init(). This happens to be the same way the ARM 'virt'
machine deals with fw_cfg (see machvirt_init() and virt_machine_done()
in hw/arm/virt.c), so we're keeping consistency with how other machines
handle this device.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 65cc5ccf06a74c98de73ec683d9a543baa302a12
https://github.com/qemu/qemu/commit/65cc5ccf06a74c98de73ec683d9a543baa302a12
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-01-20 (Fri, 20 Jan 2023)
Changed paths:
M hw/char/riscv_htif.c
M hw/riscv/boot.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/numa.c
M hw/riscv/opentitan.c
M hw/riscv/sifive_e.c
M hw/riscv/sifive_u.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/char/riscv_htif.h
M include/hw/riscv/boot.h
M include/hw/riscv/numa.h
M include/hw/riscv/sifive_u.h
M include/hw/riscv/spike.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/machine.c
M target/riscv/translate.c
M tcg/riscv/tcg-target.c.inc
A tests/avocado/riscv_opensbi.py
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230120' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for QEMU 8.0
* riscv_htif: Support console output via proxy syscall
* Cleanup firmware and device tree loading
* Fix elen check when using vector extensions
* add RISC-V OpenSBI boot test
* Ensure we always follow MISA parsing
* Fix up masking of vsip/vsie accesses
* Trap on writes to stimecmp from VS when hvictl.VTI=1
* Introduce helper_set_rounding_mode_chkfrm
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# gpg: Signature made Fri 20 Jan 2023 07:38:37 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu: (37
commits)
hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()
target/riscv: Remove helper_set_rod_rounding_mode
target/riscv: Introduce helper_set_rounding_mode_chkfrm
tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
target/riscv: Fix up masking of vsip/vsie accesses
hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
hw/riscv/sifive_u.c: simplify create_fdt()
hw/riscv/virt.c: simplify create_fdt()
hw/riscv/spike.c: simplify create_fdt()
target/riscv: Use TARGET_FMT_lx for env->mhartid
target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
target/riscv/cpu: set cpu->cfg in register_cpu_props()
hw/riscv/boot.c: use MachineState in riscv_load_kernel()
hw/riscv/boot.c: use MachineState in riscv_load_initrd()
hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
hw/riscv/spike.c: load initrd right after riscv_load_kernel()
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/fcb7e040f5c6...65cc5ccf06a7