[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] d4ea71: target/riscv: introduce riscv_cpu_cfg
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] d4ea71: target/riscv: introduce riscv_cpu_cfg() |
|
Date: |
Fri, 03 Mar 2023 05:35:40 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: d4ea71170432fef9e8394ab33eac3cdc3a9540d3
https://github.com/qemu/qemu/commit/d4ea71170432fef9e8394ab33eac3cdc3a9540d3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: introduce riscv_cpu_cfg()
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 5b17fefb90adcd79854858b2671106ad1035b391
https://github.com/qemu/qemu/commit/5b17fefb90adcd79854858b2671106ad1035b391
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: do not mask unsupported QEMU extensions in write_misa()
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230222185205.355361-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 54bd9b6ec3d67d3825258ef1fc3cec8f9679bdd5
https://github.com/qemu/qemu/commit/54bd9b6ec3d67d3825258ef1fc3cec8f9679bdd5
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: allow MISA writes as experimental
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well because write_misa() will always exit
earlier.
This seems to be benign in the majority of cases. Booting an Ubuntu
'virt' guest and logging all the calls to 'write_misa' shows that no
writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
RISC-V extensions after the machine is powered on, seems to be a niche
use.
After discussions in the mailing list, most notably in [1], we reached
the consensus that this code is not suited to be exposed to users
because it's not well tested, but at the same time removing it is a bit
extreme because we would like to fix it, and it's easier to do so with
the code available to use instead of fetching it from git log.
The approach taken here is to get rid of RISCV_FEATURE_MISA altogether
and use a new experimental flag called x-misa-w. The default value is
false, meaning that we're keeping the existing behavior of doing nothing
if a write_misa() is attempted. As with any existing experimental flag,
x-misa-w is also a temporary flag that we need to remove once we fix
write_misa().
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: cdfb290569fc80e9fb07c86c6de8ae8068fba000
https://github.com/qemu/qemu/commit/cdfb290569fc80e9fb07c86c6de8ae8068fba000
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
Log Message:
-----------
target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by
cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 09631441e5bdd164f737d4e10a4a0e3dcc1c90a7
https://github.com/qemu/qemu/commit/09631441e5bdd164f737d4e10a4a0e3dcc1c90a7
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: error out if EPMP is enabled without PMP
Instead of silently ignoring the EPMP setting if there is no PMP
available, error out informing the user that EPMP depends on PMP
support:
$ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true
qemu-system-riscv64: Invalid configuration: EPMP requires PMP support
This will force users to pick saner options in the QEMU command line.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-6-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 6a3ffda2ba4f3d4895c8d45d35feb61ddbd3a4f5
https://github.com/qemu/qemu/commit/6a3ffda2ba4f3d4895c8d45d35feb61ddbd3a4f5
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: remove RISCV_FEATURE_EPMP
RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 3fe40ef5a90d62e5695c18ec8aa517a0694ce7ed
https://github.com/qemu/qemu/commit/3fe40ef5a90d62e5695c18ec8aa517a0694ce7ed
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: c95c9d200e22b17858ec9287b6a9716d053e48aa
https://github.com/qemu/qemu/commit/c95c9d200e22b17858ec9287b6a9716d053e48aa
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-9-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: dcf654a3e899ac2569393ca3a4747c3776d9c9a3
https://github.com/qemu/qemu/commit/dcf654a3e899ac2569393ca3a4747c3776d9c9a3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/monitor.c
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: remove RISCV_FEATURE_MMU
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
the flag directly instead.
With this change the enum is also removed. It is worth noticing that
this enum, and all the RISCV_FEATURES_* that were contained in it,
predates the existence of the cpu->cfg object. Today, using cpu->cfg is
an easier way to retrieve all the features and extensions enabled in the
hart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-10-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 1e2de2b8280a518a6178e7d4dda6c9906d8a86f2
https://github.com/qemu/qemu/commit/1e2de2b8280a518a6178e7d4dda6c9906d8a86f2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/machine.c
Log Message:
-----------
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled
features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also
need to bump vmstate_riscv_cpu version_id and minimal_version_id since
'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 1d2cb5a8689f6c087b297723179676132d1cab32
https://github.com/qemu/qemu/commit/1d2cb5a8689f6c087b297723179676132d1cab32
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix the relationship between Zfhmin and Zfh
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-2-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a0d805f035ff7132949a4a7e82d7742c243927ed
https://github.com/qemu/qemu/commit/a0d805f035ff7132949a4a7e82d7742c243927ed
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix the relationship between Zhinxmin and Zhinx
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-3-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 94bdf6ee107718ad724b7d2f06633836a06b8143
https://github.com/qemu/qemu/commit/94bdf6ee107718ad724b7d2f06633836a06b8143
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvzfh.c.inc
Log Message:
-----------
target/riscv: Simplify the check for Zfhmin and Zhinxmin
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-4-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a7336161f025c114fc57595801a492d8222540ec
https://github.com/qemu/qemu/commit/a7336161f025c114fc57595801a492d8222540ec
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add cfg properties for Zv* extensions
Add properties for Zve64d,Zvfh,Zvfhmin extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-5-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: e7f0a803a7b98a784ec6bce7992b7ad643881150
https://github.com/qemu/qemu/commit/e7f0a803a7b98a784ec6bce7992b7ad643881150
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Fix relationship between V, Zve*, F and D
Add dependence chain:
* V => Zve64d => Zve64f => Zve32f => F
* V => Zve64d => D
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 2e60f9ec2ccb3906323deda7797f91c74b967b3f
https://github.com/qemu/qemu/commit/2e60f9ec2ccb3906323deda7797f91c74b967b3f
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add property check for Zvfh{min} extensions
Add check for Zvfh and Zvfhmin.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-7-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 51f33081efd4cf3182bf905096888861814522a7
https://github.com/qemu/qemu/commit/51f33081efd4cf3182bf905096888861814522a7
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Indent fixes in cpu.c
Fix indent problems in vector related check.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-8-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 3f4a5a5314b1d2d1fe910b87a3784743993003da
https://github.com/qemu/qemu/commit/3f4a5a5314b1d2d1fe910b87a3784743993003da
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Simplify check for Zve32f and Zve64f
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 732b902dd5803e3cb228424050300beffe097acf
https://github.com/qemu/qemu/commit/732b902dd5803e3cb228424050300beffe097acf
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 2bc2853f157db43c98bf1458f9af0ed11205b3f2
https://github.com/qemu/qemu/commit/2bc2853f157db43c98bf1458f9af0ed11205b3f2
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Remove redundunt check for zve32f and zve64f
Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-11-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: e80865e5f36e6bb38eae551ecb09f069b9e21e93
https://github.com/qemu/qemu/commit/e80865e5f36e6bb38eae551ecb09f069b9e21e93
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Add support for Zvfh/zvfhmin extensions
Zvfh supports vector float point instructions with SEW = 16
and supports conversions between 8-bit integers and binary16 values.
Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-12-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 6ad831ebf142ba971c5e4cb29c52b1c0c92c259b
https://github.com/qemu/qemu/commit/6ad831ebf142ba971c5e4cb29c52b1c0c92c259b
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Fix check for vector load/store instructions when EEW=64
The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32.
(Section 18.3)
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-13-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f
https://github.com/qemu/qemu/commit/c1027460dcbb782ea69a2c2d2dd8c53b4b3a625f
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Only V extension supports EEW = 64 in these cases: Zve64* extensions don't
support EEW = 64 in these cases as commented before the check.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 058d9d302e0d7b6de101310af62317c8550945ce
https://github.com/qemu/qemu/commit/058d9d302e0d7b6de101310af62317c8550945ce
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose properties for Zv* extensions
Expose Zve64d,Zvfh,Zvfhmin properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-15-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: d3e6d5762bb7b9a06c4d8dc281768deddce9b516
https://github.com/qemu/qemu/commit/d3e6d5762bb7b9a06c4d8dc281768deddce9b516
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M hw/riscv/virt.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/monitor.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
Log Message:
-----------
Merge patch series "make write_misa a no-op and FEATURE_* cleanups"
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says:
The RISCV_FEATURES_* enum and the CPUArchState::features attribute were
introduced 4+ years ago, as a way to retrieve the enabled hart features
that aren't represented via MISA CSR bits. Time passed on, and
RISCVCPUConfig was introduced. With it, we now have a centralized way of
reading all hart features that are enabled/disabled by the user and the
board. All recent features are reading their correspondent cpu->cfg.X
flag.
All but the 5 features in the RISCV_FEATURE_* enum. These features are
still operating in the same way: set it during riscv_cpu_realize() using
their cpu->cfg value, read it using riscv_feature() when needed. There
is nothing special about them in comparison with all the other features
and extensions to justify this special handling.
This series then is doing two things: first we're actually allowing
users to write the MISA CSR if they so choose. Then we're deprecate each
RISC_FEATURE_* usage until, in patch 11, we remove everything related to
it. All 5 existing RISCV_FEATURE_* features will be handled as everyone
else.
* b4-shazam-merge:
target/riscv/cpu: remove CPUArchState::features and friends
target/riscv: remove RISCV_FEATURE_MMU
hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()
target/riscv: remove RISCV_FEATURE_PMP
target/riscv: remove RISCV_FEATURE_EPMP
target/riscv/cpu.c: error out if EPMP is enabled without PMP
target/riscv: remove RISCV_FEATURE_DEBUG
target/riscv: allow MISA writes as experimental
target/riscv: do not mask unsupported QEMU extensions in write_misa()
target/riscv: introduce riscv_cpu_cfg()
Message-ID: <20230222185205.355361-1-dbarboza@ventanamicro.com>
[Palmer: use the text from the v1]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 312f632f4c3f984f820de7ac4b3a8030c5db87a0
https://github.com/qemu/qemu/commit/312f632f4c3f984f820de7ac4b3a8030c5db87a0
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
Log Message:
-----------
Merge patch series "target/riscv: Some updates to float point related
extensions"
RISC-V defines a handful of extensions related to floating point, along
with various relationships between these and other extensions. This
patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions;
along with a handful of fixes and cleanups related to the other
floating-point extension relationships.
* b4-shazam-merge
target/riscv: Expose properties for Zv* extensions
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
target/riscv: Fix check for vector load/store instructions when EEW=64
target/riscv: Add support for Zvfh/zvfhmin extensions
target/riscv: Remove rebundunt check for zve32f and zve64f
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
target/riscv: Simplify check for Zve32f and Zve64f
target/riscv: Indent fixes in cpu.c
target/riscv: Add propertie check for Zvfh{min} extensions
target/riscv: Fix relationship between V, Zve*, F and D
target/riscv: Add cfg properties for Zv* extensions
target/riscv: Simplify the check for Zfhmin and Zhinxmin
target/riscv: Fix the relationship between Zhinxmin and Zhinx
target/riscv: Fix the relationship between Zfhmin and Zfh
Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0bc71ee0b70ba8842cbf919ba4fcfd6a37f8f716
https://github.com/qemu/qemu/commit/0bc71ee0b70ba8842cbf919ba4fcfd6a37f8f716
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: gdbstub: Check priv spec version before reporting CSR
The gdbstub CSR XML is dynamically generated according to the result
of the CSR predicate() result. This has been working fine until
commit 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
introduced the privilege spec version check in riscv_csrrw_check().
When debugging the 'sifive_u' machine whose priv spec is at 1.10,
gdbstub reports priv spec 1.12 CSRs like menvcfg in the XML, hence
we see "remote failure reply 'E14'" message when examining all CSRs
via "info register system" from gdb.
Add the priv spec version check in the CSR XML generation logic to
fix this issue.
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-2-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a5e0f68652fe1ed0231311d6c8aaeaf55c631821
https://github.com/qemu/qemu/commit/a5e0f68652fe1ed0231311d6c8aaeaf55c631821
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add some comments to clarify the priority policy of
riscv_csrrw_check()
The priority policy of riscv_csrrw_check() was once adjusted in
commit eacaf4401956 ("target/riscv: Fix priority of csr related check in
riscv_csrrw_check")
whose commit message says the CSR existence check should come before
the access control check, but the code changes did not agree with
the commit message, that the predicate() check actually came after
the read / write check.
In fact this was intentional. Add some comments there so that people
won't bother trying to change it without a solid reason.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-3-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0ee342256af9205e7388efdf193a6d8f1ba1a617
https://github.com/qemu/qemu/commit/0ee342256af9205e7388efdf193a6d8f1ba1a617
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Use g_assert() for the predicate() NULL check
At present riscv_csrrw_check() checks the CSR predicate() against
NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is
a pure software check, and has nothing to do with the emulation of
the hardware behavior, thus it is inappropriate to return illegal
instruction exception when software forgets to install the hook.
Change to use g_assert() instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-4-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 28eb8bee83c6223f5921f95844e381fe01ec9e0f
https://github.com/qemu/qemu/commit/28eb8bee83c6223f5921f95844e381fe01ec9e0f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: gdbstub: Minor change for better readability
Use a variable 'base_reg' to represent cs->gdb_num_regs so that
the call to ricsv_gen_dynamic_vector_xml() can be placed in one
single line for better readability.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: e17e2c7cb968e519eb1f6c676e5c98e21f016310
https://github.com/qemu/qemu/commit/e17e2c7cb968e519eb1f6c676e5c98e21f016310
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
There is no need to generate the CSR XML if the Zicsr extension
is not enabled.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-6-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 8c7feddddd9218b407792120bcfda0347ed16205
https://github.com/qemu/qemu/commit/8c7feddddd9218b407792120bcfda0347ed16205
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Coding style fixes in csr.c
Fix various places that violate QEMU coding style:
- correct multi-line comment format
- indent to opening parenthesis
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-7-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a7e407b3f87329be533570351fc1658a7ba7b06f
https://github.com/qemu/qemu/commit/a7e407b3f87329be533570351fc1658a7ba7b06f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Use 'bool' type for read_only
The read_only variable is currently declared as an 'int', but it
should really be a 'bool'.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-8-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 77ad639cb1269ed19fe726edee7c20487b95f7d3
https://github.com/qemu/qemu/commit/77ad639cb1269ed19fe726edee7c20487b95f7d3
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Simplify {read, write}_pmpcfg() a little bit
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 94e297071bc0a5965cc32c497a886f2cf9d32710
https://github.com/qemu/qemu/commit/94e297071bc0a5965cc32c497a886f2cf9d32710
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Simplify getting RISCVCPU pointer from env
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-10-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 04733fb0916f4b2b240da42342374b05d5dfc389
https://github.com/qemu/qemu/commit/04733fb0916f4b2b240da42342374b05d5dfc389
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
At present the odd-numbered PMP configuration registers for RV64 are
reported in the CSR XML by QEMU gdbstub. However these registers do
not exist on RV64 so trying to access them from gdb results in 'E14'.
Move the pmpcfgX index check from the actual read/write routine to
the PMP CSR predicate() routine, so that non-existent pmpcfgX won't
be reported in the CSR XML for RV64.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-11-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a1f0083c6e3eee2d80e712e8a03abd70b25df097
https://github.com/qemu/qemu/commit/a1f0083c6e3eee2d80e712e8a03abd70b25df097
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from
riscv-*-fpu.xml")
the 3 FPU CSRs are removed from the XML target decription. The
original intent of that commit was based on the assumption that
the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in
riscv-*-fpu.xml are redundant. But unforuantely that is not true.
As the FPU CSR predicate() has a run-time check on MSTATUS.FS,
at the time when CSR XML is generated MSTATUS.FS is unset, hence
no FPU CSRs will be reported.
The FPU CSR predicate() already considered such a case of being
accessed by a debugger. All we need to do is to turn on debugger
mode before calling predicate().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-12-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 7eac8f4191561492fa9fa1e12c80fe27d9842fc6
https://github.com/qemu/qemu/commit/7eac8f4191561492fa9fa1e12c80fe27d9842fc6
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.
Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 &
rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: fb517fdb150b71d6fad8e2332c9aace82143e45f
https://github.com/qemu/qemu/commit/fb517fdb150b71d6fad8e2332c9aace82143e45f
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Allow debugger to access user timer and counter CSRs
At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.
Fix it by adding a debugger check in their predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-14-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: ddb10742f1acce17dbb8f3551af01bf5bfc4fa14
https://github.com/qemu/qemu/commit/ddb10742f1acce17dbb8f3551af01bf5bfc4fa14
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Allow debugger to access seed CSR
At present seed CSR is not reported in the CSR XML hence gdb cannot
access it.
Fix it by adding a debugger check in its predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-15-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0308fc621914ba424705d188dc4a58006edb3472
https://github.com/qemu/qemu/commit/0308fc621914ba424705d188dc4a58006edb3472
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Allow debugger to access {h, s}stateen CSRs
At present {h,s}stateen CSRs are not reported in the CSR XML
hence gdb cannot access them.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-16-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: e4e1f216a1ece6a69d10b22bc6f1cf855e054c95
https://github.com/qemu/qemu/commit/e4e1f216a1ece6a69d10b22bc6f1cf855e054c95
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Allow debugger to access sstc CSRs
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-17-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 9e83a35661e76652dcbdd761b8a63649f93a3d38
https://github.com/qemu/qemu/commit/9e83a35661e76652dcbdd761b8a63649f93a3d38
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Drop priv level check in mseccfg predicate()
riscv_csrrw_check() already does the generic privilege level check
hence there is no need to do the specific M-mode access check in
the mseccfg predicate().
With this change debugger can access the mseccfg CSR anytime.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-18-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: fb5bd4dcaec42b8373f445be9ab2a05aed29c4db
https://github.com/qemu/qemu/commit/fb5bd4dcaec42b8373f445be9ab2a05aed29c4db
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Group all predicate() routines together
Move sstc()/sstc32() to where all predicate() routines live, and
smstateen_acc_ok() to near {read,write}_xenvcfg().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-19-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 73b9da4aa39cd2f8b485771763bc207faf9c6893
https://github.com/qemu/qemu/commit/73b9da4aa39cd2f8b485771763bc207faf9c6893
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
M target/riscv/gdbstub.c
Log Message:
-----------
Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"
Bin Meng <bmeng@tinylab.org> says:
At present gdbstub reports an incorrect / incomplete CSR list in the
target description XML, for example:
- menvcfg is reported in 'sifive_u' machine
- fcsr is missing in a F/D enabled processor
The issue is caused by:
- priv spec version check is missing when reporting CSRs
- CSR predicate() routine is called without turning on the debugger flag
* b4-shazam-merge:
target/riscv: Group all predicate() routines together
target/riscv: Drop priv level check in mseccfg predicate()
target/riscv: Allow debugger to access sstc CSRs
target/riscv: Allow debugger to access {h, s}stateen CSRs
target/riscv: Allow debugger to access seed CSR
target/riscv: Allow debugger to access user timer and counter CSRs
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
target/riscv: Simplify getting RISCVCPU pointer from env
target/riscv: Simplify {read, write}_pmpcfg() a little bit
target/riscv: Use 'bool' type for read_only
target/riscv: Coding style fixes in csr.c
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
target/riscv: gdbstub: Minor change for better readability
target/riscv: Use g_assert() for the predicate() NULL check
target/riscv: Add some comments to clarify the priority policy of
riscv_csrrw_check()
target/riscv: gdbstub: Check priv spec version before reporting CSR
Message-ID: <20230228104035.1879882-1-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: ae9c326fb6f9b580b18de9bce1438229bfaa5215
https://github.com/qemu/qemu/commit/ae9c326fb6f9b580b18de9bce1438229bfaa5215
Author: Shaobo Song <songshaobo@eswincomputing.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
This bug has a noticeable behavior of falling back to the main loop and
respawning a redundant translation block including a single instruction
when the end address of the compressive instruction is exactly on a page
boundary, and slows down running system performance.
Signed-off-by: Shaobo Song <songshaobo@eswincomputing.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230220072732.568-1-songshaobo@eswincomputing.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: b7fa70e2afa6c784f21f749572ce78f6467666fd
https://github.com/qemu/qemu/commit/b7fa70e2afa6c784f21f749572ce78f6467666fd
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/insn_trans/trans_xthead.c.inc
Log Message:
-----------
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair instructions.
Let's fix this by removing this code.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230220095612.1529031-1-christoph.muellner@vrull.eu>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: b8e1f32cda7805236c2bd497106a9356431c2d60
https://github.com/qemu/qemu/commit/b8e1f32cda7805236c2bd497106a9356431c2d60
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzicond.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add support for Zicond extension
The spec can be found in https://github.com/riscv/riscv-zicond.
Two instructions are added:
- czero.eqz: Moves zero to a register rd, if the condition rs2 is
equal to zero, otherwise moves rs1 to rd.
- czero.nez: Moves zero to a register rd, if the condition rs2 is
nonzero, otherwise moves rs1 to rd.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: d43d54ca2b27077974928ee7783a0ae1f9838a8d
https://github.com/qemu/qemu/commit/d43d54ca2b27077974928ee7783a0ae1f9838a8d
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: Skip re-generating DT nodes for a given DTB
Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt'
machines, QEMU complains:
qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS
The whole DT generation logic should be skipped when a given DTB is
present.
Fixes: b1f19f238cae ("hw/riscv: write bootargs 'chosen' FDT after
riscv_load_kernel()")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230228074522.1845007-1-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: fc9ec3625f6dee52811c8150af994abe3c1668a3
https://github.com/qemu/qemu/commit/fc9ec3625f6dee52811c8150af994abe3c1668a3
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/virt.c
M include/hw/riscv/sifive_u.h
Log Message:
-----------
hw/riscv: Move the dtb load bits outside of create_fdt()
Move the dtb load bits outside of create_fdt(), and put it explicitly
in sifive_u_machine_init() and virt_machine_init(). With such change
create_fdt() does exactly what its function name tells us.
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230228074522.1845007-2-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 73ec0ead67ca8b4b10132b033b7388d0718b2353
https://github.com/qemu/qemu/commit/73ec0ead67ca8b4b10132b033b7388d0718b2353
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc
extensions
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203
https://github.com/qemu/qemu/commit/6f3eb1a3c82d18e5d03d25ec582f3b19ab7df203
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and
henvcfg
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-3-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0d190bd3948402257b8ca218cd63ee8bbb78b76c
https://github.com/qemu/qemu/commit/0d190bd3948402257b8ca218cd63ee8bbb78b76c
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add csr support for svadu
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-4-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 7a6613da99ccb0a80adda550722df387736d77da
https://github.com/qemu/qemu/commit/7a6613da99ccb0a80adda550722df387736d77da
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Add *envcfg.PBMTE related check in address translation
menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.
henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.
Set *envcfg.PBMTE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-5-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0af3f115e68ea9b46fe56fa7af554c61a966a23c
https://github.com/qemu/qemu/commit/0af3f115e68ea9b46fe56fa7af554c61a966a23c
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Add *envcfg.HADE related check in address translation
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 62108f05e74ce6d2a07d79e9de8801f685d60453
https://github.com/qemu/qemu/commit/62108f05e74ce6d2a07d79e9de8801f685d60453
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Export Svadu property
Set it default true for backward compatibility
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-7-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 8e5aded3de88e9403bd95b152e2a5597b5d92895
https://github.com/qemu/qemu/commit/8e5aded3de88e9403bd95b152e2a5597b5d92895
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
Merge patch series "target/riscv: Add support for Svadu extension"
Weiwei Li <liweiwei@iscas.ac.cn> says:
This patchset adds support svadu extension. It also fixes some
relationship between *envcfg fields and Svpbmt/Sstc extensions.
Specification for Svadu extension can be found in:
https://github.com/riscv/riscv-svadu
* b4-shazam-merge:
target/riscv: Export Svadu property
target/riscv: Add *envcfg.HADE related check in address translation
target/riscv: Add *envcfg.PBMTE related check in address translation
target/riscv: Add csr support for svadu
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and
henvcfg
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc
extensions
Message-ID: <20230224040852.37109-1-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 3c7d54f945f1b5b474ea35c0815a1618927c9384
https://github.com/qemu/qemu/commit/3c7d54f945f1b5b474ea35c0815a1618927c9384
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: use env_archcpu() in ctr()
We don't need to use env_cpu() and CPUState().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 96b1b00058fc95de6c76c441a8b941003de3a54d
https://github.com/qemu/qemu/commit/96b1b00058fc95de6c76c441a8b941003de3a54d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: simplify mctr()
Use riscv_cpu_cfg() to retrieve pmu_num.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: a9a4e39fd2bbf09bf10cb30700f4792a10cd2392
https://github.com/qemu/qemu/commit/a9a4e39fd2bbf09bf10cb30700f4792a10cd2392
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
A common trend in this file is to retrieve a RISCVCPU pointer by first
retrieving a CPUState pointer via env_cpu(). The CPU pointer is used
only to access the RISCVCPUConfig object and nothing else.
Let's use riscv_cpu_cfg() to access what we need directly without these
2 pointers.
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-4-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 01af27e39876d6ccbf98a0ed7d45fe9c795f1c6a
https://github.com/qemu/qemu/commit/01af27e39876d6ccbf98a0ed7d45fe9c795f1c6a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg
can be avoided by using riscv_cpu_cfg().
Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230224174520.92490-5-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 0b28c7ea0edbb6858adcce7f0ddf761441e730e8
https://github.com/qemu/qemu/commit/0b28c7ea0edbb6858adcce7f0ddf761441e730e8
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
Merge patch series "RISCVCPUConfig related cleanups"
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says:
These cleanups were suggested by LIU Zhiwei during the review of
d3e6d5762b ("Merge patch series "make write_misa a no-op and FEATURE_*
cleanups"").
* b4-shazam-merge:
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
target/riscv/csr.c: simplify mctr()
target/riscv/csr.c: use env_archcpu() in ctr()
Message-ID: <20230224174520.92490-1-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: e130683ffbac5006e57b9f730bbc556044117222
https://github.com/qemu/qemu/commit/e130683ffbac5006e57b9f730bbc556044117222
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a env->vl versus an evl value being used in the
first loop, the code is being repeated 4 times.
Create a helper to avoid code repetition in all those functions.
Arguments that are used in the callers (nf, esz and max_elems) are
passed as arguments. All other values are being derived inside the
helper.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230226170514.588071-2-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 86247c51fff458fb238a1690232c16e8425b15d3
https://github.com/qemu/qemu/commit/86247c51fff458fb238a1690232c16e8425b15d3
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
This file has several uses of env_archcpu() that are used solely to read
cfg->vlen. Use the new riscv_cpu_cfg() inline instead.
Suggested-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Message-ID: <20230226170514.588071-3-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 37151032989ecf6e7ce8b65bc7bcb400d0318b2c
https://github.com/qemu/qemu/commit/37151032989ecf6e7ce8b65bc7bcb400d0318b2c
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date: 2023-03-01 (Wed, 01 Mar 2023)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
Merge patch series "target/riscv: some vector_helper.c cleanups"
Daniel Henrique Barboza <dbarboza@ventanamicro.com> says:
This is a re-send of patch 1, which is already reviewed, with a
follow-up that uses riscv_cpu_cfg() in the remaining of the file. This
was suggested by Weiwei Li in the "[PATCH 0/4] RISCVCPUConfig related
cleanups" review. Patch 1 makes the work of patch 2 easier since it
eliminated some uses of env_archcpu() we want to avoid.
* b4-shazam-merge:
target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
Message-ID: <20230226170514.588071-1-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Commit: 76116e28e1491a06966fd594fefdaacb084ada10
https://github.com/qemu/qemu/commit/76116e28e1491a06966fd594fefdaacb084ada10
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-03-03 (Fri, 03 Mar 2023)
Changed paths:
M hw/riscv/sifive_u.c
M hw/riscv/virt.c
M include/hw/riscv/sifive_u.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
A target/riscv/insn_trans/trans_rvzicond.c.inc
M target/riscv/insn_trans/trans_xthead.c.inc
M target/riscv/machine.c
M target/riscv/monitor.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230303' of
https://gitlab.com/palmer-dabbelt/qemu into staging
Fifth RISC-V PR for QEMU 8.0
* Experimantal support for writable misa.
* Support for Svadu extension.
* Support for the Zicond extension.
* Fixes to gdbstub, CSR accesses, dependencies between the various
floating-point exceptions, and XTheadMemPair.
* Many cleanups.
# -----BEGIN PGP SIGNATURE-----
#
# iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBrrUTHHBhbG1lckBk
# YWJiZWx0LmNvbQAKCRAuExnzX7sYicHrD/9dHBDOYNwyT/C2Q31NHMcEsVN6J0kW
# 0sVyDb2/TUFoXmClMwS6jZYQQwWD7tjjB7BDcvPJ0QKLblDoZFX5JyxpQypIKWcs
# It/E6mk7aG0epH1GoB/mbHFDbeCm4tbo7Vf6cQGpV/vGWBUaOS67c5nenUK7Tlqw
# NTr9qak+9NYVswvMHZ0lUKtO12W1g/1EVkict2/90P2snWbPZ+foWomifGNljmhy
# 5WtCNp27uBKF/uuD9xubLOxSEcqtZFTuKJy7U3azV4I0IKfd6Is83Kd0IwBOrTgT
# MYkFdtQE1jgbkXYVZjft6ymLuqJrcLFYwD8C2zdNAXJLk1Y+MCtGafgW6f6SkT6B
# FrNaSOqQ9xXiaNStF2FwYdmZ476zcY+eEg2rH1grTwCMewZ9r7m3+H8iat/tR0pt
# 9scYAre1oaL33LB6DGZi3JkssNYyj42sutcNao2hQXRHcsh+vv1dLR+Di2mO6Ji5
# MNfvEgCrWWZjNVSwvhwCXdJPqqpyTbkRf8HJEp0gWvjk6VoF8sWidDw/8oMLj+wW
# qZur7GNe+piJNvly85aFSL9J3SX7RyNeDzX/yK3b4k+g6I/ZziQaNgQtB9gYcm6w
# mj3snCwRbEMEhdhPH0+Chm0Wb97knHJS14Vq9wCe2xh16o3HM5FspboLFkGZMjDV
# tRDPFb7pitwdlA==
# =FMkl
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 03 Mar 2023 08:24:21 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889
* tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu:
(59 commits)
target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig
target/riscv/vector_helper.c: create vext_set_tail_elems_1s()
target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig
target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers
target/riscv/csr.c: simplify mctr()
target/riscv/csr.c: use env_archcpu() in ctr()
target/riscv: Export Svadu property
target/riscv: Add *envcfg.HADE related check in address translation
target/riscv: Add *envcfg.PBMTE related check in address translation
target/riscv: Add csr support for svadu
target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and
henvcfg
target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc
extensions
hw/riscv: Move the dtb load bits outside of create_fdt()
hw/riscv: Skip re-generating DT nodes for a given DTB
target/riscv: Add support for Zicond extension
RISC-V: XTheadMemPair: Remove register restrictions for store-pair
target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages
target/riscv: Group all predicate() routines together
target/riscv: Drop priv level check in mseccfg predicate()
target/riscv: Allow debugger to access sstc CSRs
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/c61d1a066cb6...76116e28e149