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[Qemu-commits] [qemu/qemu] 11aeb4: m25p80: Improve error when the backen
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 11aeb4: m25p80: Improve error when the backend file size d... |
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Date: |
Thu, 09 Mar 2023 05:13:10 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 11aeb4b8c125d20181421fe2996d36285c5d62f7
https://github.com/qemu/qemu/commit/11aeb4b8c125d20181421fe2996d36285c5d62f7
Author: Cédric Le Goater <clg@kaod.org>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
m25p80: Improve error when the backend file size does not match the device
Currently, when a block backend is attached to a m25p80 device and the
associated file size does not match the flash model, QEMU complains
with the error message "failed to read the initial flash content".
This is confusing for the user.
Instead, use helper blk_check_size_and_read_all() introduced by commit
06f1521795 ("pflash: Require backend size to match device, improve
errors").
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221115151000.2080833-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3c6f3f65eab277d57f351823d0168e7268492ef5
https://github.com/qemu/qemu/commit/3c6f3f65eab277d57f351823d0168e7268492ef5
Author: Kevin Wolf <kwolf@redhat.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M hw/block/block.c
Log Message:
-----------
pflash: Fix blk_pread_nonzeroes()
Commit a4b15a8b introduced a new function blk_pread_nonzeroes(). Instead
of reading directly from the root node of the BlockBackend, it reads
from its 'file' child node. This can happen to mostly work for raw
images (as long as the 'raw' format driver is in use, but not actually
doing anything), but it breaks everything else.
Fix it to read from the root node instead.
Fixes: a4b15a8b9ef25b44fa92a4825312622600c1f37c
Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Message-Id: <20230307140230.59158-1-kwolf@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0a1f86bac9672fe34654ed001b0edfb660f7a1ba
https://github.com/qemu/qemu/commit/0a1f86bac9672fe34654ed001b0edfb660f7a1ba
Author: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Added TMP421 type sensor's support in yosemitev2
Added TMP421 type support in yosemite v2 platform.
Tested: Tested and verified in yosemite V2 platform.
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230307095239.3583613-1-pkarthikeyan1509@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a09d357dd33e93eff4f7aca503dd1e5d4f279b21
https://github.com/qemu/qemu/commit/a09d357dd33e93eff4f7aca503dd1e5d4f279b21
Author: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Added TMP421 type sensor's support in tiogapass
Added TMP421 type sensor support in tiogapass platform.
Tested: Tested and verified in tiogapass platform.
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230307103334.3586755-1-pkarthikeyan1509@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7840ba985a7c0fcf90a7318ff1f827f89571cb3c
https://github.com/qemu/qemu/commit/7840ba985a7c0fcf90a7318ff1f827f89571cb3c
Author: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M hw/arm/aspeed_eeprom.c
Log Message:
-----------
hw/arm/aspeed: Modified BMC FRU byte data in yosemitev2
Modified BMC FRU data in yosemite v2 platform.
Tested: Tested and Verified in yosemitev2 platform.
Fixes: 34f73a81e6 ("hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU")
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230307104833.3587947-1-pkarthikeyan1509@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: abe45a859b897736d7f428f58d1e5cab4fec4ddf
https://github.com/qemu/qemu/commit/abe45a859b897736d7f428f58d1e5cab4fec4ddf
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M docs/system/target-mips.rst
Log Message:
-----------
docs/system: Remove "mips" board from target-mips.rst
This board had been removed long ago in commit f169413c27
("hw/mips: Remove the 'r4k' machine")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230202132138.30945-2-jiaxun.yang@flygoat.com>
[PMD: Mention commit f169413c27]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: a43972e1769b6b35c2c5826e707ea784242b6287
https://github.com/qemu/qemu/commit/a43972e1769b6b35c2c5826e707ea784242b6287
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M target/mips/sysemu/physaddr.c
M target/mips/tcg/msa_helper.c
Log Message:
-----------
target/mips: Replace [g_]assert(0) -> g_assert_not_reached()
In order to avoid warnings such commit c0a6665c3c ("target/i386:
Remove compilation errors when -Werror=maybe-uninitialized"),
replace all assert(0) and g_assert(0) by g_assert_not_reached().
Remove any code following g_assert_not_reached().
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230221232520.14480-4-philmd@linaro.org>
Commit: 9055ffd76edc80a6f0d134213522c8cbbafd0f36
https://github.com/qemu/qemu/commit/9055ffd76edc80a6f0d134213522c8cbbafd0f36
Author: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Date: 2023-03-07 (Tue, 07 Mar 2023)
Changed paths:
M target/mips/tcg/translate.c
Log Message:
-----------
target/mips: Fix JALS32/J32 instruction handling for microMIPS
microMIPS J & JAL instructions perform a jump in a 128MB region and 5
top bits of the address need to be preserved. This is different behavior
compared to standard mips systems, where the jump is executed within a
256MB region.
Note that microMIPS32 instruction set documentation appears to have
inconsistent information regarding JALX32 instruction - it is written in
the doc that:
"To execute a procedure call within the current 256 MB-aligned region
(...)
The low 26 bits of the target address is the target field shifted left
2 bits."
But the target address is already 26 bits. Moreover, the operation
description indicates that 28 bits are copied, so the statement about
use of 26 bits is _most likely_ incorrect and the corresponding code
remains the same as for standard mips instruction set.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 7c00edb9a2e2cb975a60e80dbe1e66287a9d5777
https://github.com/qemu/qemu/commit/7c00edb9a2e2cb975a60e80dbe1e66287a9d5777
Author: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M target/mips/tcg/ldst_helper.c
Log Message:
-----------
target/mips: Fix SWM32 handling for microMIPS
SWM32 should store a sequence of 32-bit words from the GPRs, but it was
incorrectly coded to store 16-bit words only. As a result, an LWM32 that
usually follows would restore invalid register values.
Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of
MMU_MODE*_SUFFIX")
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230216051717.3911212-3-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 36b84f856ed67f5b2ee2e26368f7009f3222ba46
https://github.com/qemu/qemu/commit/36b84f856ed67f5b2ee2e26368f7009f3222ba46
Author: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
Log Message:
-----------
target/mips: Implement CP0.Config7.WII bit support
Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a
disabled interrupt should wake up a sleeping CPU.
Enable this bit by default for M14K(c) and P5600. There are potentially
other cores that support this feature, but I do not have a complete
list.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230216051717.3911212-4-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: dcebb36eb0a8dea4e134b6fed0919aff55397930
https://github.com/qemu/qemu/commit/dcebb36eb0a8dea4e134b6fed0919aff55397930
Author: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M target/mips/cpu-defs.c.inc
Log Message:
-----------
target/mips: Set correct CP0.Config[4, 5] values for M14K(c)
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230216051717.3911212-5-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 10997f2d1ded7616d33276cdc2a3e37b9ce2154d
https://github.com/qemu/qemu/commit/10997f2d1ded7616d33276cdc2a3e37b9ce2154d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/intc/mips_gic.c
M hw/mips/boston.c
M hw/mips/cps.c
M hw/mips/malta.c
M hw/misc/mips_cmgcr.c
M hw/misc/mips_itu.c
M include/hw/intc/mips_gic.h
M include/hw/misc/mips_cmgcr.h
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/mips: Declare all length properties as unsigned
Some length properties are signed, other unsigned:
hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq,
256),
hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState,
num_vps, 1),
hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp,
0x1),
hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState,
num_fifo,
hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUState,
Since negative values are not used (the minimum is '0'),
unify by declaring all properties as unsigned.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230203113650.78146-9-philmd@linaro.org>
Commit: 4c921e3fb2a9f53cbc97318487844b48ad3781f8
https://github.com/qemu/qemu/commit/4c921e3fb2a9f53cbc97318487844b48ad3781f8
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/mips/cps.c
M hw/misc/mips_itu.c
M include/hw/misc/mips_itu.h
Log Message:
-----------
hw/mips/itu: Pass SAAR using QOM link property
QOM objects shouldn't access each other internals fields
except using the QOM API.
mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and
directly sets the 'saar' pointer:
if (saar_present) {
s->itu.saar = &env->CP0_SAAR;
}
In order to avoid that, pass the MIPS_CPU object via a QOM
link property, and set the 'saar' pointer in mips_itu_realize().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230203113650.78146-10-philmd@linaro.org>
Commit: d1396cc74935bec473282fdcaeae3cb52910187b
https://github.com/qemu/qemu/commit/d1396cc74935bec473282fdcaeae3cb52910187b
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/isa/i82378.c
Log Message:
-----------
Revert "hw/isa/i82378: Remove intermediate IRQ forwarder"
To be 'usable', QDev objects (which are QOM objects) must be
1/ initialized (at this point their properties can be modified), then
2/ realized (properties are consumed).
Some devices (objects) might depend on other devices. When creating
the 'QOM composition tree', parent objects can't be 'realized' until
all their children are. We might also have circular dependencies.
A common circular dependency occurs with IRQs. Device (A) has an
output IRQ wired to device (B), and device (B) has one to device (A).
When (A) is realized and connects its IRQ to an unrealized (B), the
IRQ handler on (B) is not yet created. QEMU pass IRQ between objects
as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized
and its IRQ pointers are populated, but (A) keeps a reference to a
NULL pointer.
A common pattern to bypass this circular limitation is to use 'proxy'
objects. Proxy (P) is created (and realized) before (A) and (B). Then
(A) and (B) can be created in different order, it doesn't matter: (P)
pointers are already populated.
Commit cef2e7148e ("hw/isa/i82378: Remove intermediate IRQ forwarder")
neglected the QOM/QDev circular dependency issue, and removed the
'proxy' between the southbridge, its PCI functions and the interrupt
controller, resulting in PCI functions wiring output IRQs to
'NULL', leading to guest failures (IRQ never delivered) [1] [2].
Since we are entering feature freeze, it is safer to revert the
offending patch until we figure a way to strengthen our APIs.
[1]
https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d@redhat.com/
[2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme.hu/
This reverts commit cef2e7148e32d61338de0220619d308bf42af770.
Reported-by: Thomas Huth <thuth@redhat.com>
Inspired-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 38200011319b5819ff268dadb1b175faa6b0764a
https://github.com/qemu/qemu/commit/38200011319b5819ff268dadb1b175faa6b0764a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder"
To be 'usable', QDev objects (which are QOM objects) must be
1/ initialized (at this point their properties can be modified), then
2/ realized (properties are consumed).
Some devices (objects) might depend on other devices. When creating
the 'QOM composition tree', parent objects can't be 'realized' until
all their children are. We might also have circular dependencies.
A common circular dependency occurs with IRQs. Device (A) has an
output IRQ wired to device (B), and device (B) has one to device (A).
When (A) is realized and connects its IRQ to an unrealized (B), the
IRQ handler on (B) is not yet created. QEMU pass IRQ between objects
as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized
and its IRQ pointers are populated, but (A) keeps a reference to a
NULL pointer.
A common pattern to bypass this circular limitation is to use 'proxy'
objects. Proxy (P) is created (and realized) before (A) and (B). Then
(A) and (B) can be created in different order, it doesn't matter: (P)
pointers are already populated.
Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ
forwarder") neglected the QOM/QDev circular dependency issue, and
removed the 'proxy' between the southbridge, its PCI functions and the
interrupt controller, resulting in PCI functions wiring output IRQs to
'NULL', leading to guest failures (IRQ never delivered) [1] [2].
Since we are entering feature freeze, it is safer to revert the
offending patch until we figure a way to strengthen our APIs.
[1]
https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d@redhat.com/
[2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme.hu/
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<cdfb3c5a42e505450f6803124f27856434c5b298.1677628524.git.balaton@eik.bme.hu>
[PMD: Reworded description]
Inspired-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 4e0210525752511646c737f89ea2f2e7c7ca85de
https://github.com/qemu/qemu/commit/4e0210525752511646c737f89ea2f2e7c7ca85de
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/display/sm501.c
Log Message:
-----------
hw/display/sm501: Add debug property to control pixman usage
Add a property to allow disabling pixman and always use the fallbacks
for different operations which is useful for testing different drawing
methods or debugging pixman related issues.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id:
<61768ffaefa71b65a657d1365823bd43c7ee9354.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: ecb0e98b4f24495dd4febab7d69579d62773bdc4
https://github.com/qemu/qemu/commit/ecb0e98b4f24495dd4febab7d69579d62773bdc4
Author: David Woodhouse <dwmw2@infradead.org>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/intc/i8259.c
M hw/intc/i8259_common.c
M include/hw/isa/i8259_internal.h
Log Message:
-----------
hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select
Back in the mists of time, before EISA came along and required per-pin
level control in the ELCR register, the i8259 had a single chip-wide
level-mode control in bit 3 of ICW1.
Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is
disabled', but apparently MorphOS is using it in the version of the
i8259 which is in the Pegasos2 board as part of the VT8231 chipset.
It's easy enough to implement, and I think it's harmless enough to do so
unconditionally.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
[balaton: updated commit message as asked by author]
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<3f09b2dd109d19851d786047ad5c2ff459c90cd7.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 2fdadd02e675caca4aba4ae26317701fe2c4c901
https://github.com/qemu/qemu/commit/2fdadd02e675caca4aba4ae26317701fe2c4c901
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
hw/isa/vt82c686: Implement PCI IRQ routing
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well. The real chip may allow routing IRQs from
internal functions independently of PCI interrupts but since guests
usually configute it to a single shared interrupt we don't model that
here for simplicity.
Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4.
Suggested-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id:
<fbb016c7d0e19093335c237e15f5f6c62c4393b4.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: fb27a3e9e7c348eb77a3b8d967e3d432d2ef8070
https://github.com/qemu/qemu/commit/fb27a3e9e7c348eb77a3b8d967e3d432d2ef8070
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/pci-host/mv64361.c
M hw/ppc/pegasos2.c
Log Message:
-----------
hw/ppc/pegasos2: Fix PCI interrupt routing
According to the PegasosII schematics the PCI interrupt lines are
connected to both the gpp pins of the Mv64361 north bridge and the
PINT pins of the VT8231 south bridge so guests can get interrupts from
either of these. So far we only had the MV64361 connections which
worked for on board devices but for additional PCI devices (such as
network or sound card added with -device) guest OSes expect interrupt
from the ISA IRQ 9 where the firmware routes these PCI interrupts in
VT8231 ISA bridge. After the previous patches we can now model this
and also remove the board specific connection from mv64361. Also
configure routing of these lines when using Virtual Open Firmware to
match board firmware for guests that expect this.
This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id:
<520ff9e6eeef600ee14a4116c0c7b11940cc499c.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 422a6e8075752bc5342afd3eace23a4990dd7d98
https://github.com/qemu/qemu/commit/422a6e8075752bc5342afd3eace23a4990dd7d98
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/usb/vt82c686-uhci-pci.c
Log Message:
-----------
hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing
According to the PCI specification, PCI_INTERRUPT_LINE shall have no
effect on hardware operations. Now that the VIA south bridges implement
the internal PCI interrupt router let's be more conformant to the PCI
specification.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<9fb86a74d16db65e3aafbb154238d55e123053eb.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: eb604411a78b82c468e2b8d81a9401eb8b9c7658
https://github.com/qemu/qemu/commit/eb604411a78b82c468e2b8d81a9401eb8b9c7658
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/audio/trace-events
M hw/audio/via-ac97.c
M hw/isa/trace-events
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
Log Message:
-----------
hw/audio/via-ac97: Basic implementation of audio playback
Add basic implementation of the AC'97 sound part used in VIA south
bridge chips. Not all features of the device is emulated, only one
playback channel is supported for now but this is enough to get sound
output from some guests using this device on pegasos2.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
Message-Id:
<63b99410895312f40e7be479f581da0805e605a1.1678188711.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 0c38e9ddd7ba0fcbada0b1f1d4d11e7b5b0dcbe3
https://github.com/qemu/qemu/commit/0c38e9ddd7ba0fcbada0b1f1d4d11e7b5b0dcbe3
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M hw/usb/hcd-ohci.c
Log Message:
-----------
hw/usb/ohci: Implement resume on connection status change
If certain bit is set remote wake up should change state from
suspended to resume and generate interrupt. There was a todo comment
for this, implement that by moving existing resume logic to a function
and call that.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id:
<35c4d4ccf2f73e6a87cdbd28fb6a1b33de72ed74.1676916640.git.balaton@eik.bme.hu>
[PMD: Have ohci_resume() return a boolean]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 9d9bc7db50e7d4fc29da10be4bc7a4157b13a566
https://github.com/qemu/qemu/commit/9d9bc7db50e7d4fc29da10be4bc7a4157b13a566
Author: Akihiko Odaki <akihiko.odaki@daynix.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M ui/cocoa.m
Log Message:
-----------
ui/cocoa: Override windowDidResignKey
This fixes pressed keys being stuck when the deck is clicked and the
window loses focus.
In the past, Gustavo Noronha Silva also had a patch to fix this issue
though it only ungrabs mouse and does not release keys, and depends on
another out-of-tree patch:
https://github.com/akihikodaki/qemu/pull/3/commits/e906a80147b1dc6d4f31b6a08064ef9871a2b76c
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-Id: <20230228070946.12370-1-akihiko.odaki@daynix.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: dbc6ae9c3b595e82e746178ce428e2f9a72db572
https://github.com/qemu/qemu/commit/dbc6ae9c3b595e82e746178ce428e2f9a72db572
Author: Ted Chen <znscnchen@gmail.com>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M softmmu/physmem.c
Log Message:
-----------
memory: Dump HPA and access type of ramblocks
It's convenient to dump HVA and RW/RO status of a ramblock in "info ramblock"
for debug purpose.
Before:
Offset Used Total
0x0000000000000000 0x0000000400000000 0x0000000400000000
After:
Offset Used Total HVA RO
0x0000000000000000 0x0000000400000000 0x0000000400000000 0x00007f12ebe00000 rw
Signed-off-by: Ted Chen <znscnchen@gmail.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221205120712.269013-1-znscnchen@gmail.com>
[PMD: Add uintptr_t cast for 32-bit hosts]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: cb9291e550c58825d6d7a6c9dc877705bd635376
https://github.com/qemu/qemu/commit/cb9291e550c58825d6d7a6c9dc877705bd635376
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2023-03-08 (Wed, 08 Mar 2023)
Changed paths:
M util/log.c
Log Message:
-----------
log: Remove unneeded new line
The help text of the -d plugin option has a new line at the end which
is not needed as one is added automatically. Fixing it removes the
unexpected empty line in -d help output.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230119214033.600FB74645F@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: 555ce1d8559ec00037f994c3a5df07815d20e1ef
https://github.com/qemu/qemu/commit/555ce1d8559ec00037f994c3a5df07815d20e1ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-03-09 (Thu, 09 Mar 2023)
Changed paths:
M docs/system/target-mips.rst
M hw/audio/trace-events
M hw/audio/via-ac97.c
M hw/display/sm501.c
M hw/intc/i8259.c
M hw/intc/i8259_common.c
M hw/intc/mips_gic.c
M hw/isa/i82378.c
M hw/isa/trace-events
M hw/isa/vt82c686.c
M hw/mips/boston.c
M hw/mips/cps.c
M hw/mips/malta.c
M hw/misc/mips_cmgcr.c
M hw/misc/mips_itu.c
M hw/pci-host/mv64361.c
M hw/ppc/pegasos2.c
M hw/usb/hcd-ohci.c
M hw/usb/vt82c686-uhci-pci.c
M include/hw/intc/mips_gic.h
M include/hw/isa/i8259_internal.h
M include/hw/isa/vt82c686.h
M include/hw/misc/mips_cmgcr.h
M include/hw/misc/mips_itu.h
M softmmu/physmem.c
M target/mips/cpu-defs.c.inc
M target/mips/cpu.c
M target/mips/cpu.h
M target/mips/sysemu/physaddr.c
M target/mips/tcg/ldst_helper.c
M target/mips/tcg/msa_helper.c
M target/mips/tcg/translate.c
M ui/cocoa.m
M util/log.c
Log Message:
-----------
Merge tag 'mips-misc-20230308' of https://github.com/philmd/qemu into staging
MIPS (and few misc) patches
- MIPS
- Remove obsolete "mips" board from target-mips.rst
- Fix JALS32/J32/SWM32 instructions for microMIPS
- Fix CP0.Config7.WII handling on pre-R6 cores
- HW
- Revert "Remove intermediate IRQ forwarder" commits
- Implement legacy LTIM Edge/Level Bank Select in Intel 8259 INTC
- Improve PCI IRQ routing in VT82C686 / Pegasos II
- Basic implementation of VIA AC97 audio playback
- Implement 'resume on connection status change' in USB OHCI
- UI
- Override windowDidResignKey
- memory
- Dump HPA and access type in HMP 'info ramblock'
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmQHzH8ACgkQ4+MsLN6t
# wN4RbxAAtbsbJKHikHevCiE9Fi0E4HHI4su00m3anImogfU3CKIHA7WHgeUVCdVH
# aLoFKjvE3d45FA4YwMs13wIo89tv6btn1y8C9iy+yjktdABPUr8OJphuaDxU+yNf
# XhPm4WsS0tEg5KzzTHF7qotJGw7Zd0Aca8oezFVBSL8b73lqiJiWBEouFTK9j5Oi
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# xcVhw+GOZ67x8qAWIBKDG7nfChbcXgJ2sHxQmvb2XlxnOYw1oO5aRlrnn7ZPEWYA
# NbqUHB8G88wDcrms+Y+xCfO8idnr7Kzf4/1R1J1+5yEjg8Y1wu4t0asqZvhXA2HL
# F1yhHDCRY8w9pLYmPFGBrINBCoosiDn61g+JTngPffq1zJttmWjSLe9BYOF8Kiw+
# 4YjkCx43wK6RLTZNhU8g7iuqoYbHCQcXx5ZnGEadk+UJcfGrLnOrQbtAhvysS2wo
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# UnAihAEsyUjyg5YNb4r8ZNkdeCPN6p3s2xY8OHphqu717K6uJXw=
# =D/0W
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Mar 2023 23:45:03 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-misc-20230308' of https://github.com/philmd/qemu:
log: Remove unneeded new line
memory: Dump HPA and access type of ramblocks
ui/cocoa: Override windowDidResignKey
hw/usb/ohci: Implement resume on connection status change
hw/audio/via-ac97: Basic implementation of audio playback
hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing
hw/ppc/pegasos2: Fix PCI interrupt routing
hw/isa/vt82c686: Implement PCI IRQ routing
hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select
hw/display/sm501: Add debug property to control pixman usage
Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder"
Revert "hw/isa/i82378: Remove intermediate IRQ forwarder"
hw/mips/itu: Pass SAAR using QOM link property
hw/mips: Declare all length properties as unsigned
target/mips: Set correct CP0.Config[4, 5] values for M14K(c)
target/mips: Implement CP0.Config7.WII bit support
target/mips: Fix SWM32 handling for microMIPS
target/mips: Fix JALS32/J32 instruction handling for microMIPS
target/mips: Replace [g_]assert(0) -> g_assert_not_reached()
docs/system: Remove "mips" board from target-mips.rst
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ba44caac0741482d2c1921f7f974c205d2d4222b
https://github.com/qemu/qemu/commit/ba44caac0741482d2c1921f7f974c205d2d4222b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2023-03-09 (Thu, 09 Mar 2023)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_eeprom.c
M hw/block/block.c
M hw/block/m25p80.c
Log Message:
-----------
Merge tag 'pull-aspeed-20230307' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Small adjustments for the newest Meta machines
* blk_pread_nonzeroes() fix required for pflash and m25p80 devices
* Improve error reporting on file size for m25p80 devices
# -----BEGIN PGP SIGNATURE-----
#
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# 7KHB7w//SQzcTNAUgMc6zbe3bULS9YU7csg0zX896DwQ9Ub4wtbnIps0/JwOsx6E
# ss52YbbRVlHKcbahX6WW8JHtc6Wepcmnp4vC5dXdqgRryLTK5GgBu/GKcBb6qnHZ
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# xis0Z8gIpyLrtFT2TFc5BN9+z+PLgyaYyh7wZ2pFy1i6SOgh4FIFBOzQJDb05mmf
# aFMD+6FOGx0wo8OXfy5EQyElWhVSYio+Hx9DaDP3d3cd/twHJx8nZ8QlXh2ThRd8
# jNLdFReJBImCJHSmYzbc/tGDOjg6+TWkZOzdjqTra08UwisK4XyOKj8E+sodWr0y
# e/hI9nmIoarLCytMN1zElQFvj8xjpZ2lZOxr2EiX5ugYg0iuJhU=
# =Xs26
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Mar 2023 15:54:23 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20230307' of https://github.com/legoater/qemu:
hw/arm/aspeed: Modified BMC FRU byte data in yosemitev2
hw/arm/aspeed: Added TMP421 type sensor's support in tiogapass
hw/arm/aspeed: Added TMP421 type sensor's support in yosemitev2
pflash: Fix blk_pread_nonzeroes()
m25p80: Improve error when the backend file size does not match the device
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/7b0f0aa55fd2...ba44caac0741