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[Qemu-commits] [qemu/qemu] c46013: target/arm: Move translate-a32.h, arm


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] c46013: target/arm: Move translate-a32.h, arm_ldst.h, sve_...
Date: Sat, 13 May 2023 01:36:03 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c460132251e85eed22f7be4c75f444ce2e246912
      
https://github.com/qemu/qemu/commit/c460132251e85eed22f7be4c75f444ce2e246912
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    R target/arm/arm_ldst.h
    R target/arm/sve_ldst_internal.h
    A target/arm/tcg/arm_ldst.h
    A target/arm/tcg/sve_ldst_internal.h
    A target/arm/tcg/translate-a32.h
    R target/arm/translate-a32.h

  Log Message:
  -----------
  target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/

These files got missed when populating tcg/.
Because they are included with "", no change to the users required.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230504110412.1892411-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 67ce09b5443caf310649b5b003efe5b0d69e81a1
      
https://github.com/qemu/qemu/commit/67ce09b5443caf310649b5b003efe5b0d69e81a1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    R target/arm/helper-a64.h
    R target/arm/helper-mve.h
    R target/arm/helper-sme.h
    R target/arm/helper-sve.h
    M target/arm/helper.h
    A target/arm/tcg/helper-a64.h
    A target/arm/tcg/helper-mve.h
    A target/arm/tcg/helper-sme.h
    A target/arm/tcg/helper-sve.h

  Log Message:
  -----------
  target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/

While we cannot move the main "helper.h" out of target/arm/,
due to usage by generic code, we can move the sub-includes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20230504110412.1892411-3-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 21a4ab8318ba6f049aac244e237cd1557586e216
      
https://github.com/qemu/qemu/commit/21a4ab8318ba6f049aac244e237cd1557586e216
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Don't allow stage 2 page table walks to downgrade to NS

Bit 63 in a Table descriptor is only the NSTable bit for stage 1
translations; in stage 2 it is RES0.  We were incorrectly looking at
it all the time.

This causes problems if:
 * the stage 2 table descriptor was incorrectly setting the RES0 bit
 * we are doing a stage 2 translation in Secure address space for
   a NonSecure stage 1 regime -- in this case we would incorrectly
   do an immediate downgrade to NonSecure

A bug elsewhere in the code currently prevents us from getting
to the second situation, but when we fix that it will be possible.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230504135425.2748672-2-peter.maydell@linaro.org


  Commit: fcc0b0418fff655f20fd0cf86a1bbdc41fd2e7c6
      
https://github.com/qemu/qemu/commit/fcc0b0418fff655f20fd0cf86a1bbdc41fd2e7c6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Fix handling of SW and NSW bits for stage 2 walks

We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW
configuration bits.  These allow configuration of whether the stage 2
page table walks for Secure IPA and NonSecure IPA should do their
descriptor reads from Secure or NonSecure physical addresses. (This
is separate from how the translation table base address and other
parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2
for its base address and walk parameters, regardless of the NSW bit,
and similarly for Secure.)

Provide a new function ptw_idx_for_stage_2() which returns the
MMU index to use for descriptor reads, and use it to set up
the .in_ptw_idx wherever we call get_phys_addr_lpae().

For a stage 2 walk, wherever we call get_phys_addr_lpae():
 * .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx
 * .in_secure should be true if .in_mmu_idx is Stage2_S

This allows us to correct S1_ptw_translate() so that it consistently
always sets its (out_secure, out_phys) to the result it gets from the
S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup).
This makes better conceptual sense because the S2 walk should return
us an (address space, address) tuple, not an address that we then
randomly assign to S or NS.

Our previous handling of SW and NSW was broken, so guest code
trying to use these bits to put the s2 page tables in the "other"
address space wouldn't work correctly.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org


  Commit: 4f9786327458c0e50d8e99066d1603ebe0e345c0
      
https://github.com/qemu/qemu/commit/4f9786327458c0e50d8e99066d1603ebe0e345c0
  Author: Akihiko Odaki <akihiko.odaki@gmail.com>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update Akihiko Odaki's email address

I am now employed by Daynix. Although my role as a reviewer of
macOS-related change is not very relevant to the employment, I decided
to use the company email address to avoid confusions from different
addresses.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20230506072333.32510-1-akihiko.odaki@daynix.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cd22a0f520f471e3bd33bc19cf3b2fa772cdb2a8
      
https://github.com/qemu/qemu/commit/cd22a0f520f471e3bd33bc19cf3b2fa772cdb2a8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M ui/console.c

  Log Message:
  -----------
  ui: Fix pixel colour channel order for PNG screenshots

When we take a PNG screenshot the ordering of the colour channels in
the data is not correct, resulting in the image having weird
colouring compared to the actual display.  (Specifically, on a
little-endian host the blue and red channels are swapped; on
big-endian everything is wrong.)

This happens because the pixman idea of the pixel data and the libpng
idea differ.  PIXMAN_a8r8g8b8 defines that pixels are 32-bit values,
with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits
0-7.  This means that on little-endian systems the bytes in memory
are
   B G R A
and on big-endian systems they are
   A R G B

libpng, on the other hand, thinks of pixels as being a series of
values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA
always wants bytes in the order
   R G B A

This isn't the same as the pixman order for either big or little
endian hosts.

The alpha channel is also unnecessary bulk in the output PNG file,
because there is no alpha information in a screenshot.

To handle the endianness issue, we already define in ui/qemu-pixman.h
various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent
byte-order pixel channel formats.  So we can use PIXMAN_BE_r8g8b8 and
PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of
    R G B
and 3 bytes per pixel.

(PPM format screenshots get this right; they already use the
PIXMAN_BE_r8g8b8 format.)

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622
Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as 
PNG")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org


  Commit: d6359e150dbdf84f67add786473fd277a9a442bb
      
https://github.com/qemu/qemu/commit/d6359e150dbdf84f67add786473fd277a9a442bb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M docs/system/devices/igb.rst
    M docs/system/devices/ivshmem.rst
    M docs/system/devices/net.rst
    M docs/system/devices/usb.rst
    M docs/system/keys.rst
    M docs/system/linuxboot.rst
    M docs/system/target-i386.rst

  Log Message:
  -----------
  docs: Remove unused weirdly-named cross-reference targets

In the doc sources, we have a few cross-reference targets with odd
names "pcsys_005fxyz".  These are the legacy of the semi-automated
conversion of the old info docs to rST (the '005f' is because ASCII
0x5f is '_' and the old info link names had underscores in them).

Remove the targets which nothing links to, and rename the two targets
which are used to something a bit more descriptive.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230421163642.1151904-1-peter.maydell@linaro.org
Reviewed-by: Markus Armbruster <armbru@redhat.com>


  Commit: 9d8299bf93eb7c2ea5fd64716352b9454fa7fe8c
      
https://github.com/qemu/qemu/commit/9d8299bf93eb7c2ea5fd64716352b9454fa7fe8c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M hw/mips/malta.c

  Log Message:
  -----------
  hw/mips/malta: Fix minor dead code issue

Coverity points out (in CID 1508390) that write_bootloader has
some dead code, where we assign to 'p' and then in the following
line assign to it again. This happened as a result of the
refactoring in commit cd5066f8618b.

Fix the dead code by removing the 'void *v' variable entirely and
instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as
we do at its other callsite in write_bootloader_nanomips().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: f773a31ece66744705eda794752767df29f8c8d8
      
https://github.com/qemu/qemu/commit/f773a31ece66744705eda794752767df29f8c8d8
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M target/arm/Kconfig

  Log Message:
  -----------
  target/arm: Select SEMIHOSTING when using TCG

Semihosting has been made a 'default y' entry in Kconfig, which does
not work because when building --without-default-devices, the
semihosting code would not be available.

Make semihosting unconditional when TCG is present.

Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only 
build")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230508181611.2621-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a117e87212ca1da8221e4ccbdeed3bedba5dc8f3
      
https://github.com/qemu/qemu/commit/a117e87212ca1da8221e4ccbdeed3bedba5dc8f3
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M target/arm/Kconfig

  Log Message:
  -----------
  target/arm: Select CONFIG_ARM_V7M when TCG is enabled

We cannot allow this config to be disabled at the moment as not all of
the relevant code is protected by it.

Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a
KVM-only build") moved the CONFIGs of several boards to Kconfig, so it
is now possible that nothing selects ARM_V7M (e.g. when doing a
--without-default-devices build).

Return the CONFIG_ARM_V7M entry to a state where it is always selected
whenever TCG is available.

Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only 
build")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230508181611.2621-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c726fa701c14f088241e2f3f89b0c25ffabeac3c
      
https://github.com/qemu/qemu/commit/c726fa701c14f088241e2f3f89b0c25ffabeac3c
  Author: Fabiano Rosas <farosas@suse.de>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M tests/qtest/cdrom-test.c

  Log Message:
  -----------
  tests/qtest: Don't run cdrom boot tests if no accelerator is present

On a build configured with: --disable-tcg --enable-xen it is possible
to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom
boot tests if that's the case.

Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present")
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20230508181611.2621-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 478dccbb99db0bf8f00537dd0b4d0de88d5cb537
      
https://github.com/qemu/qemu/commit/478dccbb99db0bf8f00537dd0b4d0de88d5cb537
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M target/arm/gdbstub64.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/ptw.c
    M target/arm/tcg/pauth_helper.c

  Log Message:
  -----------
  target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check

In check_s2_mmu_setup() we have a check that is attempting to
implement the part of AArch64.S2MinTxSZ that is specific to when EL1
is AArch32:

    if !s1aarch64 then
        // EL1 is AArch32
        min_txsz = Min(min_txsz, 24);

Unfortunately we got this wrong in two ways:

(1) The minimum txsz corresponds to a maximum inputsize, but we got
the sense of the comparison wrong and were faulting for all
inputsizes less than 40 bits

(2) We try to implement this as an extra check that happens after
we've done the same txsz checks we would do for an AArch64 EL1, but
in fact the pseudocode is *loosening* the requirements, so that txsz
values that would fault for an AArch64 EL1 do not fault for AArch32
EL1, because it does Min(old_min, 24), not Max(old_min, 24).

You can see this also in the text of the Arm ARM in table D8-8, which
shows that where the implemented PA size is less than 40 bits an
AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit
IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to
constrain the IPA to the implemented PA size.

Because of part (2), we can't do this as a separate check, but
have to integrate it into aa64_va_parameters(). Add a new argument
to that function to indicate that EL1 is 32-bit. All the existing
callsites except the one in get_phys_addr_lpae() can pass 'false',
because they are either doing a lookup for a stage 1 regime or
else they don't care about the tsz/tsz_oob fields.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org


  Commit: debca86cad28192f82f741700bc38845f17d5c10
      
https://github.com/qemu/qemu/commit/debca86cad28192f82f741700bc38845f17d5c10
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-13 (Sat, 13 May 2023)

  Changed paths:
    M MAINTAINERS
    M docs/system/devices/igb.rst
    M docs/system/devices/ivshmem.rst
    M docs/system/devices/net.rst
    M docs/system/devices/usb.rst
    M docs/system/keys.rst
    M docs/system/linuxboot.rst
    M docs/system/target-i386.rst
    M hw/mips/malta.c
    M target/arm/Kconfig
    R target/arm/arm_ldst.h
    M target/arm/gdbstub64.c
    R target/arm/helper-a64.h
    R target/arm/helper-mve.h
    R target/arm/helper-sme.h
    R target/arm/helper-sve.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/ptw.c
    R target/arm/sve_ldst_internal.h
    A target/arm/tcg/arm_ldst.h
    A target/arm/tcg/helper-a64.h
    A target/arm/tcg/helper-mve.h
    A target/arm/tcg/helper-sme.h
    A target/arm/tcg/helper-sve.h
    M target/arm/tcg/pauth_helper.c
    A target/arm/tcg/sve_ldst_internal.h
    A target/arm/tcg/translate-a32.h
    R target/arm/translate-a32.h
    M tests/qtest/cdrom-test.c
    M ui/console.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230512' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * More refactoring of files into tcg/
 * Don't allow stage 2 page table walks to downgrade to NS
 * Fix handling of SW and NSW bits for stage 2 walks
 * MAINTAINERS: Update Akihiko Odaki's email address
 * ui: Fix pixel colour channel order for PNG screenshots
 * docs: Remove unused weirdly-named cross-reference targets
 * hw/mips/malta: Fix minor dead code issue
 * Fixes for the "allow CONFIG_TCG=n" changes
 * tests/qtest: Don't run cdrom boot tests if no accelerator is present
 * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check

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# gpg: Signature made Fri 12 May 2023 04:32:51 PM BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]

* tag 'pull-target-arm-20230512' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check
  tests/qtest: Don't run cdrom boot tests if no accelerator is present
  target/arm: Select CONFIG_ARM_V7M when TCG is enabled
  target/arm: Select SEMIHOSTING when using TCG
  hw/mips/malta: Fix minor dead code issue
  docs: Remove unused weirdly-named cross-reference targets
  ui: Fix pixel colour channel order for PNG screenshots
  MAINTAINERS: Update Akihiko Odaki's email address
  target/arm: Fix handling of SW and NSW bits for stage 2 walks
  target/arm: Don't allow stage 2 page table walks to downgrade to NS
  target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/
  target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/278238505d28...debca86cad28



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