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[Qemu-commits] [qemu/qemu] 988998: tcg/i386: Set P_REXW in tcg_out_addi_


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 988998: tcg/i386: Set P_REXW in tcg_out_addi_ptr
Date: Tue, 16 May 2023 17:59:12 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 988998503bc6d8c03fbea001a0513e8372fddf28
      
https://github.com/qemu/qemu/commit/988998503bc6d8c03fbea001a0513e8372fddf28
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Set P_REXW in tcg_out_addi_ptr

The REXW bit must be set to produce a 64-bit pointer result; the
bit is disabled in 32-bit mode, so we can do this unconditionally.

Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1642
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 37031fefc777a715320f86fc35ee3dd82d9d945e
      
https://github.com/qemu/qemu/commit/37031fefc777a715320f86fc35ee3dd82d9d945e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/exec/memop.h
    M tcg/tcg.c

  Log Message:
  -----------
  include/exec/memop: Add MO_ATOM_*

This field may be used to describe the precise atomicity requirements
of the guest, which may then be used to constrain the methods by which
it may be emulated by the host.

For instance, the AArch64 LDP (32-bit) instruction changes semantics
with ARMv8.4 LSE2, from

  MO_64 | MO_ATOM_IFALIGN_PAIR
  (64-bits, single-copy atomic only on 4 byte units,
   nonatomic if not aligned by 4),

to

  MO_64 | MO_ATOM_WITHIN16
  (64-bits, single-copy atomic within a 16 byte block)

The former may be implemented with two 4 byte loads, or a single 8 byte
load if that happens to be efficient on the host.  The latter may not
be implemented with two 4 byte loads and may also require a helper when
misaligned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cdfac37be0d1876832d2bb813d29df3ab885329c
      
https://github.com/qemu/qemu/commit/cdfac37be0d1876832d2bb813d29df3ab885329c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    A accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Honor atomicity of loads

Create ldst_atomicity.c.inc.

Not required for user-only code loads, because we've ensured that
the page is read-only before beginning to translate code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5b36f2684cbb07fcd75cc29b618651c43e7a80ed
      
https://github.com/qemu/qemu/commit/5b36f2684cbb07fcd75cc29b618651c43e7a80ed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg: Honor atomicity of stores

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0cadc1eda1a3120c37c713ab6d6b7a02da0d2e6f
      
https://github.com/qemu/qemu/commit/0cadc1eda1a3120c37c713ab6d6b7a02da0d2e6f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M docs/devel/loads-stores.rst
    M include/tcg/tcg-ldst.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc
    M tcg/tcg.c
    M tcg/tci.c

  Log Message:
  -----------
  tcg: Unify helper_{be,le}_{ld,st}*

With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert.  Unify the pairs of functions.

Hoist the qemu_{ld,st}_helpers arrays to tcg.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: de95016dfbf774b34ef510ad43bfce29d627cb62
      
https://github.com/qemu/qemu/commit/de95016dfbf774b34ef510ad43bfce29d627cb62
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg.c

  Log Message:
  -----------
  accel/tcg: Implement helper_{ld,st}*_mmu for user-only

TCG backends may need to defer to a helper to implement
the atomicity required by a given operation.  Mirror the
interface used in system mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0bbf501570801a101a741a7f79e1865c4ec411e2
      
https://github.com/qemu/qemu/commit/0bbf501570801a101a741a7f79e1865c4ec411e2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tci.c

  Log Message:
  -----------
  tcg/tci: Use helper_{ld,st}*_mmu for user-only

We can now fold these two pieces of code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 35c653c4029794f67a523191941104fe12f2b22d
      
https://github.com/qemu/qemu/commit/35c653c4029794f67a523191941104fe12f2b22d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg-op.c

  Log Message:
  -----------
  tcg: Add 128-bit guest memory primitives

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e61f1efeb730fd64441131ea721086065904ff67
      
https://github.com/qemu/qemu/commit/e61f1efeb730fd64441131ea721086065904ff67
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/ldst_atomicity.c.inc
    M meson.build

  Log Message:
  -----------
  meson: Detect atomic128 support with optimization

There is an edge condition prior to gcc13 for which optimization
is required to generate 16-byte atomic sequences.  Detect this.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6d3f2e3c64ac93ff6f7e286068091d5559df255c
      
https://github.com/qemu/qemu/commit/6d3f2e3c64ac93ff6f7e286068091d5559df255c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/qemu/cpuid.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Add have_atomic16

Notice when Intel or AMD have guaranteed that vmovdqa is atomic.
The new variable will also be used in generated code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b764941955d5ff13dd2760b59ce37d98941fc46b
      
https://github.com/qemu/qemu/commit/b764941955d5ff13dd2760b59ce37d98941fc46b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h

  Log Message:
  -----------
  tcg/aarch64: Detect have_lse, have_lse2 for linux

Notice when the host has additional atomic instructions.
The new variables will also be used in generated code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1ce12a8c83f2dcd10aa324916dcf6f67cc58a882
      
https://github.com/qemu/qemu/commit/1ce12a8c83f2dcd10aa324916dcf6f67cc58a882
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Detect have_lse, have_lse2 for darwin

These features are present for Apple M1.

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 30cc7a7e912481b5ba03df370d638f7ff4d7d6e1
      
https://github.com/qemu/qemu/commit/30cc7a7e912481b5ba03df370d638f7ff4d7d6e1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e9266ecd8f4aeef164e53da8f1731f4e01ba3dca
      
https://github.com/qemu/qemu/commit/e9266ecd8f4aeef164e53da8f1731f4e01ba3dca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 64d51dc31a5bdf5a0571ce48717a7daf1f7dc4aa
      
https://github.com/qemu/qemu/commit/64d51dc31a5bdf5a0571ce48717a7daf1f7dc4aa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3fb4934d3446940866fdbbba370d84a22fd3a7e1
      
https://github.com/qemu/qemu/commit/3fb4934d3446940866fdbbba370d84a22fd3a7e1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9161e9ae2eb62655ce1e9c4ec67cd1ff69639e7f
      
https://github.com/qemu/qemu/commit/9161e9ae2eb62655ce1e9c4ec67cd1ff69639e7f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7212812263402605abb147e5b2468f523a1471ab
      
https://github.com/qemu/qemu/commit/7212812263402605abb147e5b2468f523a1471ab
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target-con-set.h
    M tcg/arm/tcg-target-con-str.h
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Adjust constraints on qemu_ld/st

Always reserve r3 for tlb softmmu lookup.  Fix a bug in user-only
ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads
to the misaligned trap.  Remove r0+r1 from user-only ALL_QLDST_REGS;
I believe these had been reserved for bswap, which we no longer
perform during qemu_st.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b6ee2453f63bf1b9fe5d3e20e00b128820b4902e
      
https://github.com/qemu/qemu/commit/b6ee2453f63bf1b9fe5d3e20e00b128820b4902e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 30feb7ee4387f40e73a1e938388b60d76c90fc4f
      
https://github.com/qemu/qemu/commit/30feb7ee4387f40e73a1e938388b60d76c90fc4f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3df73c7e393b8190372f2d276b7ebc523199cfa1
      
https://github.com/qemu/qemu/commit/3df73c7e393b8190372f2d276b7ebc523199cfa1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use full load/store helpers in user-only mode

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 33982b890b057319daf5a9a0678dbffc80ed8880
      
https://github.com/qemu/qemu/commit/33982b890b057319daf5a9a0678dbffc80ed8880
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Allocate %g2 as a third temporary

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8b14f8627cd0ea5cd038e80a8dccde0c3d57458f
      
https://github.com/qemu/qemu/commit/8b14f8627cd0ea5cd038e80a8dccde0c3d57458f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13

Emphasize that the constant is signed.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ca0681c9419cde2fa4e77950ce1025af8f280adb
      
https://github.com/qemu/qemu/commit/ca0681c9419cde2fa4e77950ce1025af8f280adb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32

Shuffle the order in tcg_out_movi_int to check s13 first, and
drop this check from tcg_out_movi_imm32.  This might make the
sequence for in_prologue larger, but not worth worrying about.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2cb3f794b6d903f18f84bc0c223ec5c40ffd7064
      
https://github.com/qemu/qemu/commit/2cb3f794b6d903f18f84bc0c223ec5c40ffd7064
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32

Emphasize that the constant is unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1a42d9d472b61e4db2fb16800495d402cb9b94af
      
https://github.com/qemu/qemu/commit/1a42d9d472b61e4db2fb16800495d402cb9b94af
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Split out tcg_out_movi_s32

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2908650333ec463031632baa6ab2c9609732056d
      
https://github.com/qemu/qemu/commit/2908650333ec463031632baa6ab2c9609732056d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target-con-set.h
    M tcg/sparc64/tcg-target-con-str.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h

  Log Message:
  -----------
  tcg/sparc64: Use standard slow path for softmmu

Drop the target-specific trampolines for the standard slow path.
This lets us use tcg_out_helper_{ld,st}_args, and handles the new
atomicity bits within MemOp.

At the same time, use the full load/store helpers for user-only mode.
Drop inline unaligned access support for user-only mode, as it does
not handle atomicity.

Use TCG_REG_T[1-3] in the tlb lookup, instead of TCG_REG_O[0-2].
This allows the constraints to be simplified.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a0d99b3f47a4fa0ccd07a9a8280b272167d18c15
      
https://github.com/qemu/qemu/commit/a0d99b3f47a4fa0ccd07a9a8280b272167d18c15
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h

  Log Message:
  -----------
  accel/tcg: Remove helper_unaligned_{ld,st}

These functions are now unused.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 81f004b22354857a9cad9619a466a9d7eaffa975
      
https://github.com/qemu/qemu/commit/81f004b22354857a9cad9619a466a9d7eaffa975
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Check the host supports unaligned accesses

This should be true of all loongarch64 running Linux.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 12d7fead7c6232b3ddae963b113dcaf7e1cb1f28
      
https://github.com/qemu/qemu/commit/12d7fead7c6232b3ddae963b113dcaf7e1cb1f28
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Support softmmu unaligned accesses

Test the final byte of an unaligned access.
Use BSTRINS.D to clear the range of bits, rather than AND.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 933b331b306cd530a441d25245577f30ee0b938e
      
https://github.com/qemu/qemu/commit/933b331b306cd530a441d25245577f30ee0b938e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Support softmmu unaligned accesses

The system is required to emulate unaligned accesses, even if the
hardware does not support it.  The resulting trap may or may not
be more efficient than the qemu slow path.  There are linux kernel
patches in flight to allow userspace to query hardware support;
we can re-evaluate whether to enable this by default after that.

In the meantime, softmmu now matches useronly, where we already
assumed that unaligned accesses are supported.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7b8801071951c55dc506c1fca8b40ba292a28d6e
      
https://github.com/qemu/qemu/commit/7b8801071951c55dc506c1fca8b40ba292a28d6e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-internal.h
    M tcg/tcg-op.c
    M tcg/tci/tcg-target.c.inc
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  tcg: Introduce tcg_target_has_memory_bswap

Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
with a function with a memop argument.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 12fde9bcdb52118495d10c32ed375679f23e323c
      
https://github.com/qemu/qemu/commit/12fde9bcdb52118495d10c32ed375679f23e323c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M docs/devel/tcg-ops.rst
    M include/tcg/tcg-opc.h
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.h
    M tcg/mips/tcg-target.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  tcg: Add INDEX_op_qemu_{ld,st}_i128

Add opcodes for backend support for 128-bit memory operations.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2462e30e99676c710624806febe5ce67a45f0521
      
https://github.com/qemu/qemu/commit/2462e30e99676c710624806febe5ce67a45f0521
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Introduce tcg_out_movext3

With x86_64 as host, we do not have any temporaries with which to
resolve cycles, but we do have xchg.   As a side bonus, the set of
graphs that can be made with 3 nodes and all nodes conflicting is
small: two.  We can solve the cycle with a single temp.

This is required for x86_64 to handle stores of i128: 1 address
register and 2 data registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8d314041008478ea29ca462123f2ab21c3b363f6
      
https://github.com/qemu/qemu/commit/8d314041008478ea29ca462123f2ab21c3b363f6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Merge tcg_out_helper_load_regs into caller

Now that tcg_out_helper_load_regs is not recursive, we can
merge it into its only caller, tcg_out_helper_load_slots.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ebebea53ef8b08deb1ff970eaae706504a857bf6
      
https://github.com/qemu/qemu/commit/ebebea53ef8b08deb1ff970eaae706504a857bf6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e63b8a29834d7fcc5574288852f78a5c70f19015
      
https://github.com/qemu/qemu/commit/e63b8a29834d7fcc5574288852f78a5c70f19015
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Introduce atom_and_align_for_opc

Examine MemOp for atomicity and alignment, adjusting alignment
as required to implement atomicity on the host.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1c5322d90cb0c5a3cf4723992f4baa21691542ca
      
https://github.com/qemu/qemu/commit/1c5322d90cb0c5a3cf4723992f4baa21691542ca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 64741d9902ca1c0c111c53baa6bc11a55c2474c9
      
https://github.com/qemu/qemu/commit/64741d9902ca1c0c111c53baa6bc11a55c2474c9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3e3d994276058db45dae3998f7fc21608c65fcc4
      
https://github.com/qemu/qemu/commit/3e3d994276058db45dae3998f7fc21608c65fcc4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Use atom_and_align_for_opc

No change to the ultimate load/store routines yet, so some atomicity
conditions not yet honored, but plumbs the change to alignment through
the relevant functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7658a6cf567b66b1c118292da2c81789dc0643e7
      
https://github.com/qemu/qemu/commit/7658a6cf567b66b1c118292da2c81789dc0643e7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c0cafab5a52ea3830b2e3605116170106c5d044c
      
https://github.com/qemu/qemu/commit/c0cafab5a52ea3830b2e3605116170106c5d044c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1bac4697199dd9aa5d8d0e3c56d0ea52b2bd0fa1
      
https://github.com/qemu/qemu/commit/1bac4697199dd9aa5d8d0e3c56d0ea52b2bd0fa1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 37e523f04b09f2e653629ac16206512d8a5ebc85
      
https://github.com/qemu/qemu/commit/37e523f04b09f2e653629ac16206512d8a5ebc85
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 00406e6d3f3e4d3f852af9991a0e03df66362de6
      
https://github.com/qemu/qemu/commit/00406e6d3f3e4d3f852af9991a0e03df66362de6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9ca6343103e13968b44aee56e34523bda13be78a
      
https://github.com/qemu/qemu/commit/9ca6343103e13968b44aee56e34523bda13be78a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/sparc64: Use atom_and_align_for_opc

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a1429ca26e13bdfd10f16348c2d9e5d2a23c1377
      
https://github.com/qemu/qemu/commit/a1429ca26e13bdfd10f16348c2d9e5d2a23c1377
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/meson.build
    A tcg/tcg-op-ldst.c
    M tcg/tcg-op.c

  Log Message:
  -----------
  tcg: Split out memory ops to tcg-op-ldst.c

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c9ad8d27caa01b13f01c22e04788f4e33068afb4
      
https://github.com/qemu/qemu/commit/c9ad8d27caa01b13f01c22e04788f4e33068afb4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg-op.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Widen gen_insn_data to uint64_t

We already pass uint64_t to restore_state_to_opc; this changes all
of the other uses from insn_start through the encoding to decoding.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 24e46e6c9d9927121ac703db79819c688d2a5c5b
      
https://github.com/qemu/qemu/commit/24e46e6c9d9927121ac703db79819c688d2a5c5b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/user-exec.c
    M include/tcg/tcg-ldst.h
    M tcg/tcg.c

  Log Message:
  -----------
  accel/tcg: Widen tcg-ldst.h addresses to uint64_t

Always pass the target address as uint64_t.
Adjust tcg_out_{ld,st}_helper_args to match.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e570597a8a7762bc85196b699c0d733dc33929ec
      
https://github.com/qemu/qemu/commit/e570597a8a7762bc85196b699c0d733dc33929ec
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/tcg-runtime.h
    M accel/tcg/user-exec.c
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Widen helper_{ld,st}_i128 addresses to uint64_t

Always pass the target address as uint64_t.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ddfdd4178beb56543ac98976efbc885d7e2b5150
      
https://github.com/qemu/qemu/commit/ddfdd4178beb56543ac98976efbc885d7e2b5150
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/tcg-runtime.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Widen helper_atomic_* addresses to uint64_t

Always pass the target address as uint64_t.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 76cef4b233da82641fca61cb7783a30fc7096053
      
https://github.com/qemu/qemu/commit/76cef4b233da82641fca61cb7783a30fc7096053
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Widen tcg_gen_code pc_start argument to uint64_t

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f5c346ac41759aea9dbce333a0dbfa9cc52f9f11
      
https://github.com/qemu/qemu/commit/f5c346ac41759aea9dbce333a0dbfa9cc52f9f11
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c

  Log Message:
  -----------
  accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback

As gen_mem_wrapped is only used in plugin_gen_empty_mem_callback,
we can avoid the curiosity of union mem_gen_fn by inlining it.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b6d9164518b377bf77a6962f1a8bcc8cf6c085f1
      
https://github.com/qemu/qemu/commit/b6d9164518b377bf77a6962f1a8bcc8cf6c085f1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c

  Log Message:
  -----------
  accel/tcg: Merge do_gen_mem_cb into caller

As do_gen_mem_cb is called once, merge it into gen_empty_mem_cb.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eb9d02f24b1ce877a60ffaf6cc1ecc8484740b37
      
https://github.com/qemu/qemu/commit/eb9d02f24b1ce877a60ffaf6cc1ecc8484740b37
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Reduce copies for plugin_gen_mem_callbacks

We only need to make copies for loads, when the destination
overlaps the address.  For now, only eliminate the copy for
stores and 128-bit loads.

Rename plugin_prep_mem_callbacks to plugin_maybe_preserve_addr,
returning NULL if no copy is made.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fcdab382c8b92bcc689b18f8ba5cd036139945bf
      
https://github.com/qemu/qemu/commit/fcdab382c8b92bcc689b18f8ba5cd036139945bf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/plugin-gen.c
    M include/exec/plugin-gen.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  accel/tcg: Widen plugin_gen_empty_mem_callback to i64

Since we do this inside gen_empty_mem_cb anyway, let's
do this earlier inside tcg expansion.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4baf3978c02b387c39dc6a75d323126ab386aece
      
https://github.com/qemu/qemu/commit/4baf3978c02b387c39dc6a75d323126ab386aece
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add addr_type to TCGContext

This will enable replacement of TARGET_LONG_BITS within tcg/.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c44239d23528d5f36dfc450b5e60e96b1ad6fc18
      
https://github.com/qemu/qemu/commit/c44239d23528d5f36dfc450b5e60e96b1ad6fc18
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-op.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*

Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.
These inlines will eventually be seen only by target-specific code.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7bb9b20a576fa4d5d633b592b5592c2700052704
      
https://github.com/qemu/qemu/commit/7bb9b20a576fa4d5d633b592b5592c2700052704
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-op.h
    M tcg/tcg-op-ldst.c

  Log Message:
  -----------
  tcg: Remove TCGv from tcg_gen_atomic_*

Expand from TCGv to TCGTemp inline in the translators,
and validate that the size matches tcg_ctx->addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8c25e8f03a13c9b0ffe607ece4afd5990648210c
      
https://github.com/qemu/qemu/commit/8c25e8f03a13c9b0ffe607ece4afd5990648210c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/tcg/tcg-opc.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc
    M tcg/tcg-op-ldst.c
    M tcg/tcg.c
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Split INDEX_op_qemu_{ld,st}* for guest address size

For 32-bit hosts, we cannot simply rely on TCGContext.addr_bits,
as we need one or two host registers to represent the guest address.

Create the new opcodes and update all users.  Since we have not
yet eliminated TARGET_LONG_BITS, only one of the two opcodes will
ever be used, so we can get away with treating them the same in
the backends.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fc1ee3f90fd2344ef415ccac8f3f6c911248af98
      
https://github.com/qemu/qemu/commit/fc1ee3f90fd2344ef415ccac8f3f6c911248af98
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc

  Log Message:
  -----------
  tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong

We now have the address size as part of the opcode, so
we no longer need to test TARGET_LONG_BITS.  We can use
uint64_t for target_ulong, as passed into load/store helpers.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2aea77c04729d6d3bf5fc0f597629dd10f34449b
      
https://github.com/qemu/qemu/commit/2aea77c04729d6d3bf5fc0f597629dd10f34449b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.h

  Log Message:
  -----------
  tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32

Keep all 32-bit values zero extended in the register, not solely when
addresses are 32 bits.  This eliminates a dependency on TARGET_LONG_BITS.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 757604bf23ffbfb798930fadafe1f9c85f1dc965
      
https://github.com/qemu/qemu/commit/757604bf23ffbfb798930fadafe1f9c85f1dc965
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Conditionalize tcg_out_extu_i32_i64

Since TCG_TYPE_I32 values are kept zero-extended in registers, via
omission of the REXW bit, we need not extend if the register matches.
This is already relied upon by qemu_{ld,st}.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1d0cfc6a1b50b86c5243c85832dd85e82c94ec17
      
https://github.com/qemu/qemu/commit/1d0cfc6a1b50b86c5243c85832dd85e82c94ec17
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Adjust type of tlb_mask

Because of its use on tgen_arithi, this value must be a signed
32-bit quantity, as that is what may be encoded in the insn.
The truncation of the value to unsigned for 32-bit guests is
done via the REX bit via 'trexw'.

Removes the only uses of target_ulong from this tcg backend.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c2c1db0f732797a69de0a160d1df44af6366a5e5
      
https://github.com/qemu/qemu/commit/c2c1db0f732797a69de0a160d1df44af6366a5e5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses can be infered from the INDEX_op_qemu_*_a{32,64}_* opcode
being used.  Add a field into TCGLabelQemuLdst to record the usage.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 66c99c954ab49306fb12ad555ae80c68c48040ed
      
https://github.com/qemu/qemu/commit/66c99c954ab49306fb12ad555ae80c68c48040ed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Remove TARGET_LONG_BITS

All uses can be infered from the INDEX_op_qemu_*_a{32,64}_*
opcode being used.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 15b8187ff23163cab082bfc11b52abc006615346
      
https://github.com/qemu/qemu/commit/15b8187ff23163cab082bfc11b52abc006615346
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Remove USE_GUEST_BASE

Eliminate the test vs TARGET_LONG_BITS by considering this
predicate to be always true, and simplify accordingly.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 994d33525de77c99a0403aa6d484a81492544139
      
https://github.com/qemu/qemu/commit/994d33525de77c99a0403aa6d484a81492544139
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 30e9d82b067500585132e587635e6c3edaa0d208
      
https://github.com/qemu/qemu/commit/30e9d82b067500585132e587635e6c3edaa0d208
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6904d7272a6bb74c6603adb7f1e3c120666572cd
      
https://github.com/qemu/qemu/commit/6904d7272a6bb74c6603adb7f1e3c120666572cd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7b051e94c1cd907376e92aee613e8584816a370e
      
https://github.com/qemu/qemu/commit/7b051e94c1cd907376e92aee613e8584816a370e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL

All uses replaced with TCGContext.addr_type.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 73a9f3aa19af8a43569794e0f2b52bf46f3308a2
      
https://github.com/qemu/qemu/commit/73a9f3aa19af8a43569794e0f2b52bf46f3308a2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target.c.inc
    M tcg/sparc64/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Add page_bits and page_mask to TCGContext

Disconnect guest page size from TCG compilation.
While this could be done via exec/target_page.h, we want to cache
the value across multiple memory access operations, so we might
as well initialize this early.

The changes within tcg/ are entirely mechanical:

    sed -i s/TARGET_PAGE_BITS/s->page_bits/g
    sed -i s/TARGET_PAGE_MASK/s->page_mask/g

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0726010c83092534d6b4c8736c83c24e8ce0a252
      
https://github.com/qemu/qemu/commit/0726010c83092534d6b4c8736c83c24e8ce0a252
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/translate-all.c
    M include/tcg/tcg.h
    M tcg/aarch64/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg: Add tlb_dyn_max_bits to TCGContext

Disconnect guest tlb parameters from TCG compilation.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 44fe8f47fce3bdc8dcf49e3f001519a375ecc88a
      
https://github.com/qemu/qemu/commit/44fe8f47fce3bdc8dcf49e3f001519a375ecc88a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M include/exec/cpu-all.h
    A include/exec/user/guest-base.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Split out exec/user/guest-base.h

TCG will need this declaration, without all of the other
bits that come with cpu-all.h.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1c3a828a4edeaf18612cf8f01d111caea87cc999
      
https://github.com/qemu/qemu/commit/1c3a828a4edeaf18612cf8f01d111caea87cc999
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M accel/tcg/atomic_common.c.inc
    M accel/tcg/cputlb.c
    A accel/tcg/ldst_atomicity.c.inc
    M accel/tcg/plugin-gen.c
    M accel/tcg/tcg-runtime.h
    M accel/tcg/translate-all.c
    M accel/tcg/user-exec.c
    M docs/devel/loads-stores.rst
    M docs/devel/tcg-ops.rst
    M include/exec/cpu-all.h
    M include/exec/memop.h
    M include/exec/plugin-gen.h
    A include/exec/user/guest-base.h
    M include/qemu/cpuid.h
    M include/tcg/tcg-ldst.h
    M include/tcg/tcg-op.h
    M include/tcg/tcg-opc.h
    M include/tcg/tcg.h
    M meson.build
    M tcg/aarch64/tcg-target.c.inc
    M tcg/aarch64/tcg-target.h
    M tcg/arm/tcg-target-con-set.h
    M tcg/arm/tcg-target-con-str.h
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/i386/tcg-target.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/loongarch64/tcg-target.h
    M tcg/meson.build
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/optimize.c
    M tcg/ppc/tcg-target.c.inc
    M tcg/ppc/tcg-target.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/riscv/tcg-target.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/s390x/tcg-target.h
    M tcg/sparc64/tcg-target-con-set.h
    M tcg/sparc64/tcg-target-con-str.h
    M tcg/sparc64/tcg-target.c.inc
    M tcg/sparc64/tcg-target.h
    M tcg/tcg-internal.h
    A tcg/tcg-op-ldst.c
    M tcg/tcg-op.c
    M tcg/tcg.c
    M tcg/tci.c
    M tcg/tci/tcg-target.c.inc
    M tcg/tci/tcg-target.h

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230516-2' of https://gitlab.com/rth7680/qemu into 
staging

tcg/i386: Fix tcg_out_addi_ptr for win64
tcg: Implement atomicity for TCGv_i128
tcg: First quarter of cleanups for building tcg once

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# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
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[ultimate]

* tag 'pull-tcg-20230516-2' of https://gitlab.com/rth7680/qemu: (74 commits)
  tcg: Split out exec/user/guest-base.h
  tcg: Add tlb_dyn_max_bits to TCGContext
  tcg: Add page_bits and page_mask to TCGContext
  tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/aarch64: Remove USE_GUEST_BASE
  tcg/arm: Remove TARGET_LONG_BITS
  tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
  tcg/i386: Adjust type of tlb_mask
  tcg/i386: Conditionalize tcg_out_extu_i32_i64
  tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
  tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
  tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
  tcg: Remove TCGv from tcg_gen_atomic_*
  tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
  tcg: Add addr_type to TCGContext
  accel/tcg: Widen plugin_gen_empty_mem_callback to i64
  tcg: Reduce copies for plugin_gen_mem_callbacks
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/ee58e412fde9...1c3a828a4ede



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