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[Qemu-commits] [qemu/qemu] 94692c: target/riscv: Use xl instead of mxl f
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 94692c: target/riscv: Use xl instead of mxl for disassemble |
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Date: |
Mon, 10 Jul 2023 15:58:58 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 94692c3a34d9e2e149bd9db188425e9da6e578c6
https://github.com/qemu/qemu/commit/94692c3a34d9e2e149bd9db188425e9da6e578c6
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Use xl instead of mxl for disassemble
Disassemble function(plugin_disas, target_disas, monitor_disas) will
always call set_disas_info before disassembling instructions.
plugin_disas and target_disas will always be called under a TB, which
has the same XLEN.
We can't ensure that monitor_disas will always be called under a TB,
but current XLEN will still be a better choice, thus we can ensure at
least the disassemble of the nearest one TB is right.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2e8c1e0215449eb0a88bbb3fae2f6277777611c3
https://github.com/qemu/qemu/commit/2e8c1e0215449eb0a88bbb3fae2f6277777611c3
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu_cfg.h
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Factor out extension tests to cpu_cfg.h
This patch moves the extension test functions that are used
to gate vendor extension decoders, into cpu_cfg.h.
This allows to reuse them in the disassembler.
This patch does not introduce new functionality.
However, the patch includes a small change:
The parameter for the extension test functions has been changed
from 'DisasContext*' to 'const RISCVCPUConfig*' to keep
the code in cpu_cfg.h self-contained.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-Id: <20230612111034.3955227-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5d326db2f9d0f4c90a3298f12bcb803e7bf302dc
https://github.com/qemu/qemu/commit/5d326db2f9d0f4c90a3298f12bcb803e7bf302dc
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
A disas/riscv.h
Log Message:
-----------
disas/riscv: Move types/constants to new header file
In order to enable vendor disassembler support, we need to
move types and constants into a header file so that other
compilation units can use them as well.
This patch does not introduce any functional changes.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 01b1361f84d55a86be486323836a29488b52e3a6
https://github.com/qemu/qemu/commit/01b1361f84d55a86be486323836a29488b52e3a6
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
M disas/riscv.h
Log Message:
-----------
disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: fd7c64f6bd863df28081576a6f5c7a44dd65721f
https://github.com/qemu/qemu/commit/fd7c64f6bd863df28081576a6f5c7a44dd65721f
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
M disas/riscv.h
Log Message:
-----------
disas/riscv: Encapsulate opcode_data into decode
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
the code for more struct rv_opcode_data objects in the future.
This patch is based on previous work from Liu Zhiwei:
https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c859a2424dbbae8f5ea64c0f8445981402cd8552
https://github.com/qemu/qemu/commit/c859a2424dbbae8f5ea64c0f8445981402cd8552
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Provide infrastructure for vendor extensions
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension support can be added to the disassembler.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f6f72338d80ec6f15a6b18643797bc10901aadf3
https://github.com/qemu/qemu/commit/f6f72338d80ec6f15a6b18643797bc10901aadf3
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/meson.build
A disas/riscv-xventana.c
A disas/riscv-xventana.h
M disas/riscv.c
Log Message:
-----------
disas/riscv: Add support for XVentanaCondOps
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 318df7238b9f842af96aad01ec183012c8fecab9
https://github.com/qemu/qemu/commit/318df7238b9f842af96aad01ec183012c8fecab9
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/meson.build
A disas/riscv-xthead.c
A disas/riscv-xthead.h
M disas/riscv.c
M disas/riscv.h
M target/riscv/cpu_cfg.h
Log Message:
-----------
disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 869d76f2073f6ed28e26bb264d4c2c8841f06496
https://github.com/qemu/qemu/commit/869d76f2073f6ed28e26bb264d4c2c8841f06496
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Make MPV only work when MPP != PRV_M
Upon MRET or explicit memory access with MPRV=1, MPV should be ignored
when MPP=PRV_M.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230603134236.15719-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 03dd405dd5da6e0df3023bf9394ad0490b8369ab
https://github.com/qemu/qemu/commit/03dd405dd5da6e0df3023bf9394ad0490b8369ab
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
MPV and GVA bits are added by hypervisor extension to mstatus
and mstatush (if MXLEN=32).
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230603134236.15719-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 98fbdaaed50781e18d9a612590d1d47106de0aca
https://github.com/qemu/qemu/commit/98fbdaaed50781e18d9a612590d1d47106de0aca
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Remove redundant assignment to SXL
SXL is initialized as env->misa_mxl which is also the mxl value.
So we can just remain it unchanged to keep it read-only.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230603134236.15719-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 029f5feed6e5b7173788b7414af3e8aa32746344
https://github.com/qemu/qemu/commit/029f5feed6e5b7173788b7414af3e8aa32746344
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: fix veyron-v1 CPU properties
Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from
riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei
and ext_icsr from riscv_cpu_init(), the init() function of
TYPE_RISCV_CPU, parent type of all RISC-V CPUss. This was done to force
CPUs to explictly enable all extensions and features it requires,
without any 'magic values' that were inherited by the parent type.
This commit failed to make appropriate changes in the 'veyron-v1' CPU,
added earlier by commit e1d084a8524a. The result is that the veyron-v1
CPU has ext_ifencei, ext_icsr and pmp set to 'false', which is not the
case.
The reason why it took this long to notice (thanks LIU Zhiwei for
reporting it) is because Linux doesn't mind 'ifencei' and 'icsr' being
absent in the 'riscv,isa' DT, implying that they're both present if the
'i' extension is enabled. OpenSBI also doesn't error out or warns about
the lack of 'pmp', it'll just not protect memory pages.
Fix it by setting them to 'true' in rv64_veyron_v1_cpu_init() like
7f0bdfb5bfc2 already did with other CPUs.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Fixes: 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from
riscv_cpu_init()")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230620152443.137079-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 3a610f5430f61bd67f0ac78ef40c8d3bd2b4f8ee
https://github.com/qemu/qemu/commit/3a610f5430f61bd67f0ac78ef40c8d3bd2b4f8ee
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add additional xlen for address when MPRV=1
As specified in privilege spec:"When MPRV=1, load and store memory
addresses are treated as though the current XLEN were set to MPP’s
XLEN". So the xlen for address may be different from current xlen.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230614032547.35895-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ef1ba32afff6b3d9be377804904b784da6594219
https://github.com/qemu/qemu/commit/ef1ba32afff6b3d9be377804904b784da6594219
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
should also take MPRV into consideration. As pointer mask for instruction
is not supported currently, so we can directly update cur_pmbase/pmmask
based on address related mode and xlen affected by MPRV now.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230614032547.35895-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: aa903cf31391dd505b399627158f1292a6d19896
https://github.com/qemu/qemu/commit/aa903cf31391dd505b399627158f1292a6d19896
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
Log Message:
-----------
roms/opensbi: Upgrade from v1.2 to v1.3
Upgrade OpenSBI from v1.2 to v1.3 and the pre-built bios images.
The v1.3 release includes the following commits:
440fa81 treewide: Replace TRUE/FALSE with true/false
6509127 Makefile: Remove -N ldflag to prevent linker RWX warning
65638f8 lib: utils/sys: Allow custom HTIF base address for RV32
f14595a lib: sbi: Allow platform to influence cold boot HART selection
6957ae0 platform: generic: Allow platform_override to select cold boot HART
cb7e7c3 platform: generic: Allow platform_override to perform firmware init
8020df8 generic/starfive: Add Starfive JH7110 platform implementation
6997552 lib: sbi_hsm: Rename 'priv' argument to 'arg1'
9e397e3 docs: domain_support: Use capital letter for privilege modes
9e0ba09 include: sbi: Fine grain the permissions for M and SU modes
aace1e1 lib: sbi: Use finer permission semantics for address validation
22dbdb3 lib: sbi: Add permissions for the firmware start till end
1ac14f1 lib: sbi: Use finer permission sematics to decide on PMP bits
44f736c lib: sbi: Modify the boot time region flag prints
20646e0 lib: utils: Use SU-{R/W/X} flags for region permissions during parsing
3e2f573 lib: utils: Disallow non-root domains from adding M-mode regions
59a08cd lib: utils: Add M-mode {R/W} flags to the MMIO regions
001106d docs: Update domain's region permissions and requirements
da5594b platform: generic: allwinner: Fix PLIC array bounds
ce2a834 docs: generic.md: fix typo of andes-ae350
8ecbe6d lib: sbi_hsm: handle failure when hart_stop returns SBI_ENOTSUPP
b1818ee include: types: add always inline compiler attribute
9c4eb35 lib: utils: atcsmu: Add Andes System Management Unit support
787296a platform: andes/ae350: Implement hart hotplug using HSM extension
7aaeeab lib: reset/fdt_reset_atcwdt200: Use defined macros and function in
atcsmu.h
a990309 lib: utils: Fix reserved memory node for firmware memory
fefa548 firmware: Split RO/RX and RW sections
2f40a99 firmware: Move dynsym and reladyn sections to RX section
c10e3fe firmware: Add RW section offset in scratch
b666760 lib: sbi: Print the RW section offset
230278d lib: sbi: Add separate entries for firmware RX and RW regions
dea0922 platform: renesas/rzfive: Configure Local memory regions as part of
root domain
33bf917 lib: utils: Add fdt_add_cpu_idle_states() helper function
c45992c platform: generic: allwinner: Advertise nonretentive suspend
c8ea836 firmware: Fix fw_rw_offset computation in fw_base.S
8050081 firmware: Not to clear all the MIP
84d15f4 lib: sbi_hsm: Use csr_set to restore the MIP
199189b lib: utils: Mark only the largest region as reserved in FDT
66b0e23 lib: sbi: Ensure domidx_to_domain_table is null-terminated
642f3de Makefile: Add missing .dep files for fw_*.elf.ld
09b34d8 include: Add support for byteorder/endianness conversion
680bea0 lib: utils/fdt: Use byteorder conversion functions in libfdt_env.h
b224ddb include: types: Add typedefs for endianness
aa5dafc include: sbi: Fix BSWAPx() macros for big-endian host
e3bf1af include: Add defines for SBI debug console extension
0ee3a86 lib: sbi: Add sbi_nputs() function
4e0572f lib: sbi: Add sbi_ngets() function
eab48c3 lib: sbi: Add sbi_domain_check_addr_range() function
5a41a38 lib: sbi: Implement SBI debug console extension
c43903c lib: sbi: Add console_puts() callback in the console device
29285ae lib: utils/serial: Implement console_puts() for semihosting
65c2190 lib: sbi: Speed-up sbi_printf() and friends using nputs()
321293c lib: utils/fdt: Fix fdt_pmu.c header dependency
aafcc90 platform: generic/allwinner: Fix sun20i-d1.c header dependency
745aaec platform: generic/andes: Fix ae350.c header dependency
99d09b6 include: fdt/fdt_helper: Change fdt_get_address() to return
root.next_arg1
6861ee9 lib: utils: fdt_fixup: Fix compile error
4f2be40 docs: fix typo in fw.md
30ea806 lib: sbi_hart: Enable hcontext and scontext
81adc62 lib: sbi: Align SBI vendor extension id with mvendorid CSR
31b82e0 include: sbi: Remove extid parameter from vendor_ext_provider() callback
c100951 platform: generic: renesas: rzfive: Add support to configure the PMA
2491242 platform: generic: renesas: rzfive: Configure the PMA region
67b2a40 lib: sbi: sbi_ecall: Check the range of SBI error
5a75f53 lib: sbi/sbi_domain: cosmetic style fixes
bc06ff6 lib: utils/fdt/fdt_domain: Simplify region access permission check
17b3776 docs: domain_support: Update the DT example
1364d5a lib: sbi_hsm: Factor out invalid state detection
40f16a8 lib: sbi_hsm: Don't try to restore state on failed change
c88e039 lib: sbi_hsm: Ensure errors are consistent with spec
b1ae6ef lib: sbi_hsm: Move misplaced comment
07673fc lib: sbi_hsm: Remove unnecessary include
8a40306 lib: sbi_hsm: Export some functions
73623a0 lib: sbi: Add system suspend skeleton
c9917b6 lib: sbi: Add system_suspend_allowed domain property
7c964e2 lib: sbi: Implement system suspend
37558dc docs: Correct opensbi-domain property name
5ccebf0 platform: generic: Add system suspend test
908be1b gpio/starfive: add gpio driver and support gpio reset
4b28afc make: Add a command line option for debugging OpenSBI
e9d08bd lib: utils/i2c: Add minimal StarFive jh7110 I2C driver
568ea49 platform: starfive: add PMIC power ops in JH7110 visionfive2 board
506144f lib: serial: Cadence: Enable compatibility for cdns,uart-r1p8
1fe8dc9 lib: sbi_pmu: add callback for counter width
51951d9 lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi
60c358e lib: sbi_pmu: Reserve space for implementation specific firmware events
548e4b4 lib: sbi_pmu: Rename fw_counter_value
b51ddff lib: sbi_pmu: Update sbi_pmu dev ops
641d2e9 lib: sbi_pmu: Use dedicated event code for platform firmware events
57d3aa3 lib: sbi_pmu: Introduce fw_counter_write_value API
c631a7d lib: sbi_pmu: Add hartid parameter PMU device ops
d56049e lib: sbi: Refactor the calls to sbi_hart_switch_mode()
e8e9ed3 lib: sbi: Set the state of a hart to START_PENDING after the hart is
ready
c6a092c lib: sbi: Clear IPIs before init_warm_startup in non-boot harts
ed88a63 lib: sbi_scratch: Optimize the alignment code for alloc size
73ab11d lib: sbi: Fix how to check whether the domain contains fw_region
f64dfcd lib: sbi: Introduce sbi_entry_count() function
30b9e7e lib: sbi_hsm: Fix sbi_hsm_hart_start() for platform with hart hotplug
8e90259 lib: sbi_hart: clear mip csr during hart init
45ba2b2 include: Add defines for SBI CPPC extension
33caae8 lib: sbi: Implement SBI CPPC extension
91767d0 lib: sbi: Print the CPPC device name
edc9914 lib: sbi_pmu: Align the event type offset as per SBI specification
ee016a7 docs: Correct FW_JUMP_FDT_ADDR calculation example
2868f26 lib: utils: fdt_fixup: avoid buffer overrun
66fa925 lib: sbi: Optimize sbi_tlb
24dde46 lib: sbi: Optimize sbi_ipi
80078ab sbi: tlb: Simplify to tlb_process_count/tlb_process function
bf40e07 lib: sbi: Optimize sbi_tlb queue waiting
eeab500 platform: generic: andes/renesas: Add SBI EXT to check for enabling
IOCP errata
f692289 firmware: Optimize loading relocation type
e41dbb5 firmware: Change to use positive offset to access relocation entries
bdb3c42 lib: sbi: Do not clear active_events for cycle/instret when stopping
674e019 lib: sbi: Fix counter index calculation for SBI_PMU_CFG_FLAG_SKIP_MATCH
f5dfd99 lib: sbi: Don't check SBI error range for legacy console getchar
7919530 lib: sbi: Add debug print when sbi_pmu_init fails
4e33530 lib: sbi: Remove unnecessary semicolon
6bc02de lib: sbi: Simplify sbi_ipi_process remove goto
dc1c7db lib: sbi: Simplify BITS_PER_LONG definition
f58c140 lib: sbi: Introduce register_extensions extension callback
e307ba7 lib: sbi: Narrow vendor extension range
042f0c3 lib: sbi: pmu: Remove unnecessary probe function
8b952d4 lib: sbi: Only register available extensions
767b5fc lib: sbi: Optimize probe of srst/susp
c3e31cb lib: sbi: Remove 0/1 probe implementations
33f1722 lib: sbi: Document sbi_ecall_extension members
d4c46e0 Makefile: Dereference symlinks on install
8b99a7f lib: sbi: Fix return of sbi_console_init
264d0be lib: utils: Improve fdt_serial_init
9a0bdd0 lib: utils: Improve fdt_ipi
122f226 lib: utils: Improve fdt_timer
df75e09 lib: utils/ipi: buffer overrun aclint_mswi_cold_init
bdde2ec lib: sbi: Align system suspend errors with spec
aad7a37 include: sbi_scratch: Add helper macros to access data type
5cf9a54 platform: Allow platforms to specify heap size
40d36a6 lib: sbi: Introduce simple heap allocator
2a04f70 lib: sbi: Print scratch size and usage at boot time
bbff53f lib: sbi_pmu: Use heap for per-HART PMU state
ef4542d lib: sbi: Use heap for root domain creation
66daafe lib: sbi: Use scratch space to save per-HART domain pointer
fa5ad2e lib: utils/gpio: Use heap in SiFive and StartFive GPIO drivers
903e88c lib: utils/i2c: Use heap in DesignWare and SiFive I2C drivers
5a8cfcd lib: utils/ipi: Use heap in ACLINT MSWI driver
3013716 lib: utils/irqchip: Use heap in PLIC, APLIC and IMSIC drivers
7e5636a lib: utils/timer: Use heap in ACLINT MTIMER driver
3c1c972 lib: utils/fdt: Use heap in FDT domain parsing
acbd8fc lib: utils/ipi: Use scratch space to save per-HART MSWI pointer
f0516be lib: utils/timer: Use scratch space to save per-HART MTIMER pointer
b3594ac lib: utils/irqchip: Use scratch space to save per-HART PLIC pointer
1df52fa lib: utils/irqchip: Don't check hartid in imsic_update_hartid_table()
355796c lib: utils/irqchip: Use scratch space to save per-HART IMSIC pointer
524feec docs: Add OpenSBI logo and use it in the top-level README.md
932be2c README.md: Improve project copyright information
8153b26 platform/lib: Set no-map attribute on all PMP regions
d64942f firmware: Fix find hart index
27c957a lib: reset: Move fdt_reset_init into generic_early_init
8bd666a lib: sbi: check A2 register in ecall_dbcn_handler.
2552799 include: Bump-up version to 1.3
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230630160717.843044-1-bmeng@tinylab.org>
Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 11b937b65256537cff74fe731a96465f8d0c2d88
https://github.com/qemu/qemu/commit/11b937b65256537cff74fe731a96465f8d0c2d88
Author: Bin Meng <bmeng@tinylab.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M tests/avocado/riscv_opensbi.py
Log Message:
-----------
tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing
The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3.
Let's enable the 32-bit Spike OpenSBI boot testing.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230630160717.843044-2-bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: bf01a04f5fbb4c22ac861a76fdc4c7a74247e44b
https://github.com/qemu/qemu/commit/bf01a04f5fbb4c22ac861a76fdc4c7a74247e44b
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_e_aon.c
A include/hw/misc/sifive_e_aon.h
Log Message:
-----------
hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.
The watchdog timer is in the always-on domain device of HiFive 1 rev b,
so this patch added the AON device to the sifive_e machine. This patch
only implemented the functionality of the watchdog timer.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627141216.3962299-2-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82193640c49ded26835fe90e60cdfd4385d4c0e2
https://github.com/qemu/qemu/commit/82193640c49ded26835fe90e60cdfd4385d4c0e2
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/sifive_e.c
M include/hw/riscv/sifive_e.h
Log Message:
-----------
hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.
Create the AON device when we realize the sifive_e machine.
This patch only implemented the functionality of the watchdog timer,
not all the functionality of the AON device.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230627141216.3962299-3-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2f849e9d7aa4ee8782c524b4521ba36451cfd414
https://github.com/qemu/qemu/commit/2f849e9d7aa4ee8782c524b4521ba36451cfd414
Author: Tommy Wu <tommy.wu@sifive.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M tests/qtest/meson.build
A tests/qtest/sifive-e-aon-watchdog-test.c
Log Message:
-----------
tests/qtest: sifive-e-aon-watchdog-test.c: Add QTest of watchdog of sifive_e
Add some simple tests of the watchdog timer in the always-on domain device
of HiFive 1 rev b.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627141216.3962299-4-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 278c1bcef568f41e298792f9f437efd333305812
https://github.com/qemu/qemu/commit/278c1bcef568f41e298792f9f437efd333305812
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M meson.build
Log Message:
-----------
target/riscv: Only unify 'riscv32/64' -> 'riscv' for host cpu in meson
We want to keep the ability to distinct between 32/64-bit host.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627143235.29947-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4de81093f894c42bce975e52fc7b470a76046301
https://github.com/qemu/qemu/commit/4de81093f894c42bce975e52fc7b470a76046301
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M meson.build
Log Message:
-----------
target/riscv: Only build KVM guest with same wordsize as host
Per Anup Patel in [*]:
> Currently, we only support running rv64 guest on rv64 host
> and rv32 guest on rv32 host.
>
> In the future, we might support running rv32 guest on rv64
> host but as of now we don't see a strong push for it.
Therefore, when only using the KVM accelerator it is pointless
to build qemu-system-riscv32 on a rv64 host (or qemu-system-riscv64
on a rv32 host). Restrict meson to only build the correct binary,
avoiding to waste ressources building unusable code.
[*]
https://lore.kernel.org/qemu-devel/CAAhSdy2JeRHeeoEc1XKQhPO3aDz4YKeyQsPT4S8yKJcYTA+AiQ@mail.gmail.com/
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627143235.29947-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b227f6a8a7db28f48b4f1120d521eacdc25e66ef
https://github.com/qemu/qemu/commit/b227f6a8a7db28f48b4f1120d521eacdc25e66ef
Author: Ivan Klokov <ivan.klokov@syntacore.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add RVV registers to log
Print RvV extension register to log if VPU option is enabled.
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230629083730.386604-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c0716c81b2e436eb69975f1890dd2ae46bce5369
https://github.com/qemu/qemu/commit/c0716c81b2e436eb69975f1890dd2ae46bce5369
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M docs/system/riscv/virt.rst
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Restrict ACLINT to TCG
The Advanced Core Local Interruptor (ACLINT) device can
only be used with TCG. Check for TCG enabled instead of
KVM being not. Only add the property when TCG is used.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230629121103.87733-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9e1c7d982d7feb5b6547276ecc4c10468c0f5092
https://github.com/qemu/qemu/commit/9e1c7d982d7feb5b6547276ecc4c10468c0f5092
Author: Robbin Ehn <rehn@rivosinc.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M linux-user/riscv/syscall32_nr.h
M linux-user/riscv/syscall64_nr.h
M linux-user/syscall.c
Log Message:
-----------
linux-user/riscv: Add syscall riscv_hwprobe
This patch adds the new syscall for the
"RISC-V Hardware Probing Interface"
(https://docs.kernel.org/riscv/hwprobe.html).
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Robbin Ehn <rehn@rivosinc.com>
Message-Id: <06a4543df2aa6101ca9a48f21a3198064b4f1f87.camel@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 4556fdaa5cb7157b9adb3ee136f44d5952b94736
https://github.com/qemu/qemu/commit/4556fdaa5cb7157b9adb3ee136f44d5952b94736
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add properties for BF16 extensions
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230615063302.102409-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 5d1270caac2ef7b8c887d4cb5a2444ba6d237516
https://github.com/qemu/qemu/commit/5d1270caac2ef7b8c887d4cb5a2444ba6d237516
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add support for Zfbfmin extension
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230615063302.102409-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 87b27bfca432c69a2abfd7a9ebc1fa27876b31f5
https://github.com/qemu/qemu/commit/87b27bfca432c69a2abfd7a9ebc1fa27876b31f5
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Add support for Zvfbfmin extension
Add trans_* and helper function for Zvfbfmin instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230615063302.102409-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: adf772b0f788b80bea427c945a48343610d4af49
https://github.com/qemu/qemu/commit/adf772b0f788b80bea427c945a48343610d4af49
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Add support for Zvfbfwma extension
Add trans_* and helper function for Zvfbfwma instructions.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230615063302.102409-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 889caa44011d32a584c8e3a31bf91a7f9b73f2a3
https://github.com/qemu/qemu/commit/889caa44011d32a584c8e3a31bf91a7f9b73f2a3
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Expose properties for BF16 extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230615063302.102409-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 60ef34a48cf1990c55f0ff86086f40d7dfbb4181
https://github.com/qemu/qemu/commit/60ef34a48cf1990c55f0ff86086f40d7dfbb4181
Author: Jason Chien <jason.chien@sifive.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Set the correct exception for implict G-stage translation fail
The privileged spec states:
For a memory access made to support VS-stage address translation (such as
to read/write a VS-level page table), permissions are checked as though
for a load or store, not for the original access type. However, any
exception is always reported for the original access type (instruction,
load, or store/AMO).
The current implementation converts the access type to LOAD if implicit
G-stage translation fails which results in only reporting "Load guest-page
fault". This commit removes the convertion of access type, so the reported
exception conforms to the spec.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230627074915.7686-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 32b2d75bf7fab6fa82dd01b2413ca14753b90973
https://github.com/qemu/qemu/commit/32b2d75bf7fab6fa82dd01b2413ca14753b90973
Author: Weiwei Li <liweiwei@iscas.ac.cn>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
Log Message:
-----------
target/riscv: Add disas support for BF16 extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230703071759.86775-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c5cc248b478bc21e50845ba6b2414c4a688e195f
https://github.com/qemu/qemu/commit/c5cc248b478bc21e50845ba6b2414c4a688e195f
Author: yang.zhang <yang.zhang@hexintek.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
Should set/get riscv all reg timer,i.e, time/compare/frequency/state.
Signed-off-by: Yang Zhang <yang.zhang@hexintek.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230707032306.4606-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 49554856f0b6f622ab6afdcc275d4ab2ecb3625c
https://github.com/qemu/qemu/commit/49554856f0b6f622ab6afdcc275d4ab2ecb3625c
Author: Guenter Roeck <linux@roeck-us.net>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
riscv: Generate devicetree only after machine initialization is complete
If the devicetree is created before machine initialization is complete,
it misses dynamic devices. Specifically, the tpm device is not added
to the devicetree file and is therefore not instantiated in Linux.
Load/create devicetree in virt_machine_done() to solve the problem.
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Alistair Francis <alistair23@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.c>
Fixes: 325b7c4e75 hw/riscv: Enable TPM backends
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706035937.1870483-1-linux@roeck-us.net>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1ad53688b9e15b179dbbfe44ee8b86d7e46715a8
https://github.com/qemu/qemu/commit/1ad53688b9e15b179dbbfe44ee8b86d7e46715a8
Author: Lakshmi Bai Raja Subramanian
<lakshmi.bai.rajasubramanian@bodhicomputing.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: virt: Convert fdt_load_addr to uint64_t
fdt_load_addr was previously declared as uint32_t which doe not match
with the return type of riscv_compute_fdt_addr().
This patch modifies the fdt_load_addr type from a uint32_t to a uint64_t
to match the riscv_compute_fdt_addr() return type.
This fixes calculating the fdt address when DRAM is mapped to higher
64-bit address.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Lakshmi Bai Raja Subramanian
<lakshmi.bai.rajasubramanian@bodhicomputing.com>
[ Change by AF:
- Cleanup commit title and message
]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <168872495192.6334.3845988291412774261-1@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: eddabb6b888fa915ed679637983d8f39adfb725c
https://github.com/qemu/qemu/commit/eddabb6b888fa915ed679637983d8f39adfb725c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: skip features setup for KVM CPUs
As it is today it's not possible to use '-cpu host' if the RISC-V host
has RVH enabled. This is the resulting error:
$ ./qemu/build/qemu-system-riscv64 \
-machine virt,accel=kvm -m 2G -smp 1 \
-nographic -snapshot -kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.img \
-append "earlycon=sbi root=/dev/ram rw" \
-cpu host
qemu-system-riscv64: H extension requires priv spec 1.12.0
This happens because we're checking for priv spec for all CPUs, and
since we're not setting env->priv_ver for the 'host' CPU, it's being
default to zero (i.e. PRIV_SPEC_1_10_0).
In reality env->priv_ver does not make sense when running with the KVM
'host' CPU. It's used to gate certain CSRs/extensions during translation
to make them unavailable if the hart declares an older spec version. It
doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec
checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs
are available [1].
'priv_ver' is just one example. We're doing a lot of feature validation
and setup during riscv_cpu_realize() that it doesn't apply to KVM CPUs.
Validating the feature set for those CPUs is a KVM problem that should
be handled in KVM specific code.
The new riscv_cpu_realize_tcg() helper contains all validation logic that
are applicable to TCG CPUs only. riscv_cpu_realize() verifies if we're
running TCG and, if it's the case, proceed with the usual TCG realize()
logic.
[1] lib/sbi/sbi_hart.c, hart_detect_features()
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 43d1de32f8ef4502005e6b48e6602408fa711390
https://github.com/qemu/qemu/commit/43d1de32f8ef4502005e6b48e6602408fa711390
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:
$ ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \
-m 2G -smp 1 -nographic -snapshot \
-kernel ./guest_imgs/Image \
-initrd ./guest_imgs/rootfs_kvm_riscv64.img \
-append "earlycon=sbi root=/dev/ram rw" \
-cpu host
**
ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be
reached
Bail out! ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should
not be reached
Aborted
The error is triggered from create_fdt_socket_cpus() in hw/riscv/virt.c.
It's trying to get satp_mode_str for a NULL cpu->cfg.satp_mode.map.
For this KVM cpu we would need to inherit the satp supported modes
from the RISC-V host. At this moment this is not possible because the
KVM driver does not support it. And even when it does we can't just let
this broken for every other older kernel.
Since mmu-type is not a required node, according to [1], skip the
'mmu-type' FDT node if there's no satp_mode set. We'll revisit this
logic when we can get satp information from KVM.
[1]
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/riscv/cpus.yaml
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230706101738.460804-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1e341500459e0900a07b0c3a86de4526ebe4496d
https://github.com/qemu/qemu/commit/1e341500459e0900a07b0c3a86de4526ebe4496d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: restrict 'mvendorid' value
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't make sense to allow 'mvendorid' to be different than it
is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have
any 'mvendorid' they want.
Change 'mvendorid' to be a class property created via
'object_class_property_add', instead of using the DEFINE_PROP_UINT32()
macro. This allow us to define a custom setter for it that will verify,
for named CPUs, if mvendorid is different than it is already set by the
CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is
set to an invalid value:
$ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=2
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=2:
Unable to change veyron-v1-riscv-cpu mvendorid (0x61f)
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a1863ad368d32b53153bf417a83f01c85bb9d82c
https://github.com/qemu/qemu/commit/a1863ad368d32b53153bf417a83f01c85bb9d82c
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: restrict 'mimpid' value
Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.
Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEMU version, regardless of whether the actual
implementation of the CPU changed from one QEMU version to the other.
Named CPU should set it to a meaningful value instead and generic CPUs
can set whatever they want.
This is the error thrown for an invalid 'mimpid' value for the veyron-v1
CPU:
$ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=2
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=2:
Unable to change veyron-v1-riscv-cpu mimpid (0x111)
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d6a427e2c0b249bc8d3e0b4d7c5150f829d0907a
https://github.com/qemu/qemu/commit/d6a427e2c0b249bc8d3e0b4d7c5150f829d0907a
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: restrict 'marchid' value
'marchid' shouldn't be set to a different value as previously set for
named CPUs.
For all other CPUs it shouldn't be freely set either - the spec requires
that 'marchid' can't have the MSB (most significant bit) set and every
other bit set to zero, i.e. 0x80000000 is an invalid 'marchid' value for
32 bit CPUs.
As with 'mimpid', setting a default value based on the current QEMU
version is not a good idea because it implies that the CPU
implementation changes from one QEMU version to the other. Named CPUs
should set 'marchid' to a meaningful value instead, and generic CPUs can
set to any valid value.
For the 'veyron-v1' CPU this is the error thrown if 'marchid' is set to
a different val:
$ ./build/qemu-system-riscv64 -M virt -nographic -cpu
veyron-v1,marchid=0x80000000
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.marchid=0x80000000:
Unable to change veyron-v1-riscv-cpu marchid (0x8000000000010000)
And, for generics CPUs, this is the error when trying to set to an
invalid val:
$ ./build/qemu-system-riscv64 -M virt -nographic -cpu
rv64,marchid=0x8000000000000000
qemu-system-riscv64: can't apply global
rv64-riscv-cpu.marchid=0x8000000000000000:
Unable to set marchid with MSB (64) bit set and the remaining bits zero
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 492265ae8be70537391c08390cb7c64580c902d9
https://github.com/qemu/qemu/commit/492265ae8be70537391c08390cb7c64580c902d9
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
Log Message:
-----------
target/riscv: use KVM scratch CPUs to init KVM properties
Certain validations, such as the validations done for the machine IDs
(mvendorid/marchid/mimpid), are done before starting the CPU.
Non-dynamic (named) CPUs tries to match user input with a preset
default. As it is today we can't prefetch a KVM default for these cases
because we're only able to read/write KVM regs after the vcpu is
spinning.
Our target/arm friends use a concept called "scratch CPU", which
consists of creating a vcpu for doing queries and validations and so on,
which is discarded shortly after use [1]. This is a suitable solution
for what we need so let's implement it in target/riscv as well.
kvm_riscv_init_machine_ids() will be used to do any pre-launch setup for
KVM CPUs, via riscv_cpu_add_user_properties(). The function will create
a KVM scratch CPU, fetch KVM regs that work as default values for user
properties, and then discard the scratch CPU afterwards.
We're starting by initializing 'mvendorid'. This concept will be used to
init other KVM specific properties in the next patches as well.
[1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu()
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d758f8849851dd4e97a575e52c11ec748ab1bbec
https://github.com/qemu/qemu/commit/d758f8849851dd4e97a575e52c11ec748ab1bbec
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()
Allow 'marchid' and 'mimpid' to also be initialized in
kvm_riscv_init_machine_ids().
After this change, the handling of mvendorid/marchid/mimpid for the
'host' CPU type will be equal to what we already have for TCG named
CPUs, i.e. the user is not able to set these values to a different val
than the one that is already preset.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 1fb5a622f7ef0cfd65b39decd768983e1d0ba1c2
https://github.com/qemu/qemu/commit/1fb5a622f7ef0cfd65b39decd768983e1d0ba1c2
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs
After changing user validation for mvendorid/marchid/mimpid to guarantee
that the value is validated on user input time, coupled with the work in
fetching KVM default values for them by using a scratch CPU, we're
certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are
already good to be written back to KVM.
There's no need to write the values back for 'host' type CPUs since the
values can't be changed, so let's do that just for generic CPUs.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e28b9c497428f9efccc7b7f5fc69e7c6524b41a0
https://github.com/qemu/qemu/commit/e28b9c497428f9efccc7b7f5fc69e7c6524b41a0
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
At this moment we're retrieving env->misa_ext during
kvm_arch_init_cpu(), leaving env->misa_ext_mask behind.
We want to set env->misa_ext_mask, and we want to set it as early as
possible. The reason is that we're going to use it in the validation
process of the KVM MISA properties we're going to add next. Setting it
during arch_init_cpu() is too late for user validation.
Move the code to a new helper that is going to be called during init()
time, via kvm_riscv_init_user_properties(), like we're already doing for
the machine ID properties. Set both misa_ext and misa_ext_mask to the
same value retrieved by the 'isa' config reg.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ed7e6182063ead28274751bd59f11f74a4cf3063
https://github.com/qemu/qemu/commit/ed7e6182063ead28274751bd59f11f74a4cf3063
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv/cpu: add misa_ext_info_arr[]
Next patch will add KVM specific user properties for both MISA and
multi-letter extensions. For MISA extensions we want to make use of what
is already available in misa_ext_cfgs[] to avoid code repetition.
misa_ext_info_arr[] array will hold name and description for each MISA
extension that misa_ext_cfgs[] is declaring. We'll then use this new
array in KVM code to avoid duplicating strings. Two getters were added
to allow KVM to retrieve the 'name' and 'description' for each MISA
property.
There's nothing holding us back from doing the same with multi-letter
extensions. For now doing just with MISA extensions is enough.
It is worth documenting that even using the __bultin_ctz() directive to
populate the misa_ext_info_arr[] we are forced to assign 'name' and
'description' during runtime in riscv_cpu_add_misa_properties(). The
reason is that some Gitlab runners ('clang-user' and 'tsan-build') will
throw errors like this if we fetch 'name' and 'description' from the
array in the MISA_CFG() macro:
../target/riscv/cpu.c:1624:5: error: initializer element is not a
compile-time constant
MISA_CFG(RVA, true),
^~~~~~~~~~~~~~~~~~~
../target/riscv/cpu.c:1619:53: note: expanded from macro 'MISA_CFG'
{.name = misa_ext_info_arr[MISA_INFO_IDX(_bit)].name, \
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~
gcc and others compilers/builders were fine with that change. We can't
ignore failures in the Gitlab pipeline though, so code was changed to
make every runner happy.
As a side effect, misa_ext_cfg[] is no longer a 'const' array because
it must be set during runtime.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 92becce5e172357d9be047306d92b986242f0f0d
https://github.com/qemu/qemu/commit/92becce5e172357d9be047306d92b986242f0f0d
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: add KVM specific MISA properties
Using all TCG user properties in KVM is tricky. First because KVM
supports only a small subset of what TCG provides, so most of the
cpu->cfg flags do nothing for KVM.
Second, and more important, we don't have a way of telling if any given
value is an user input or not. For TCG this has a small impact since we
just validating everything and error out if needed. But for KVM it would
be good to know if a given value was set by the user or if it's a value
already provided by KVM. Otherwise we don't know how to handle failed
kvm_set_one_regs() when writing the configurations back.
These characteristics make it overly complicated to use the same user
facing flags for both KVM and TCG. A simpler approach is to create KVM
specific properties that have specialized logic, forking KVM and TCG use
cases for those cases only. Fully separating KVM/TCG properties is
unneeded at this point - in fact we want the user experience to be as
equal as possible, regardless of the acceleration chosen.
We'll start this fork with the MISA properties, adding the MISA bits
that the KVM driver currently supports. A new KVMCPUConfig type is
introduced. It'll hold general information about an extension. For MISA
extensions we're going to use the newly created getters of
misa_ext_infos[] to populate their name and description. 'offset' holds
the MISA bit (RVA, RVC, ...). We're calling it 'offset' instead of
'misa_bit' because this same KVMCPUConfig struct will be used to
multi-letter extensions later on.
This new type also holds a 'user_set' flag. This flag will be set when
the user set an option that's different than what is already configured
in the host, requiring KVM intervention to write the regs back during
kvm_arch_init_vcpu(). Similar mechanics will be implemented for
multi-letter extensions as well.
There is no need to duplicate more code than necessary, so we're going
to use the existing kvm_riscv_init_user_properties() to add the KVM
specific properties. Any code that is adding a TCG user prop is then
changed slightly to verify first if there's a KVM prop with the same
name already added.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 7313fffb40ea9775b38ff2ce73c4d6b0f43edc2f
https://github.com/qemu/qemu/commit/7313fffb40ea9775b38ff2ce73c4d6b0f43edc2f
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv/kvm.c: update KVM MISA bits
Our design philosophy with KVM properties can be resumed in two main
decisions based on KVM interface availability and what the user wants to
do:
- if the user disables an extension that the host KVM module doesn't
know about (i.e. it doesn't implement the kvm_get_one_reg() interface),
keep booting the CPU. This will avoid users having to deal with issues
with older KVM versions while disabling features they don't care;
- for any other case we're going to error out immediately. If the user
wants to enable a feature that KVM doesn't know about this a problem that
is worth aborting - the user must know that the feature wasn't enabled
in the hart. Likewise, if KVM knows about the extension, the user wants
to enable/disable it, and we fail to do it so, that's also a problem we
can't shrug it off.
In the case of MISA bits we won't even try enabling bits that aren't
already available in the host. The ioctl() is so likely to fail that
it's not worth trying. This check is already done in the previous patch,
in kvm_cpu_set_misa_ext_cfg(), thus we don't need to worry about it now.
In kvm_riscv_update_cpu_misa_ext() we'll go through every potential user
option and do as follows:
- if the user didn't set the property or set to the same value of the
host, do nothing;
- Disable the given extension in KVM. Error out if anything goes wrong.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: f7a69fa6e6e21580b6e56dac87ad2ab0bf228065
https://github.com/qemu/qemu/commit/f7a69fa6e6e21580b6e56dac87ad2ab0bf228065
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
M target/riscv/kvm.c
Log Message:
-----------
target/riscv/kvm.c: add multi-letter extension KVM properties
Let's add KVM user properties for the multi-letter extensions that KVM
currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
svinval and svpbmt.
As with MISA extensions, we're using the KVMCPUConfig type to hold
information about the state of each extension. However, multi-letter
extensions have more cases to cover than MISA extensions, so we're
adding an extra 'supported' flag as well. This flag will reflect if a
given extension is supported by KVM, i.e. KVM knows how to handle it.
This is determined during KVM extension discovery in
kvm_riscv_init_multiext_cfg(), where we test for EINVAL errors. Any
other error will cause an abort.
The use of the 'user_set' is similar to what we already do with MISA
extensions: the flag set only if the user is changing the extension
state.
The 'supported' flag will be used later on to make an exception for
users that are disabling multi-letter extensions that are unknown to
KVM.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20230706101738.460804-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b71f9dcada2edacfa9baaf872de717c903fb333b
https://github.com/qemu/qemu/commit/b71f9dcada2edacfa9baaf872de717c903fb333b
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: add satp_mode properties earlier
riscv_cpu_add_user_properties() ended up with an excess of "#ifndef
CONFIG_USER_ONLY" blocks after changes that added KVM properties
handling.
KVM specific properties are required to be created earlier than their
TCG counterparts, but the remaining props can be created at any order.
Move riscv_add_satp_mode_properties() to the start of the function,
inside the !CONFIG_USER_ONLY block already present there, to remove the
last ifndef block.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 63c7eedc28f25141a44e34534c6b5317caaf38cc
https://github.com/qemu/qemu/commit/63c7eedc28f25141a44e34534c6b5317caaf38cc
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
riscv_isa_string_ext() is being used by riscv_isa_string(), which is
then used by boards to retrieve the 'riscv,isa' string to be written in
the FDT. All this happens after riscv_cpu_realize(), meaning that we're
already past riscv_cpu_validate_set_extensions() and, more important,
riscv_cpu_disable_priv_spec_isa_exts().
This means that all extensions that needed to be disabled due to
priv_spec mismatch are already disabled. Checking this again during
riscv_isa_string_ext() is unneeded. Remove it.
As a bonus, riscv_isa_string_ext() can now be used with the 'host'
KVM-only CPU type since it doesn't have a env->priv_ver assigned and it
would fail this check for no good reason.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 56f0e992ca01391f81a42b29883288fa1e4380c1
https://github.com/qemu/qemu/commit/56f0e992ca01391f81a42b29883288fa1e4380c1
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu.c: create KVM mock properties
KVM-specific properties are being created inside target/riscv/kvm.c. But
at this moment we're gathering all the remaining properties from TCG and
adding them as is when running KVM. This creates a situation where
non-KVM properties are setting flags to 'true' due to its default
settings (e.g. Zawrs). Users can also freely enable them via command
line.
This doesn't impact runtime per se because KVM doesn't care about these
flags, but code such as riscv_isa_string_ext() take those flags into
account. The result is that, for a KVM guest, setting non-KVM properties
will make them appear in the riscv,isa DT.
We want to keep the same API for both TCG and KVM and at the same time,
when running KVM, forbid non-KVM extensions to be enabled internally. We
accomplish both by changing riscv_cpu_add_user_properties() to add a
mock boolean property for every non-KVM extension in
riscv_cpu_extensions[]. Then, when running KVM, users are still free to
set extensions at will, but we'll error out if a non-KVM extension is
enabled. Setting such extension to 'false' will be ignored.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: df817297d7a5397a3383207b0e0174b464cf42ab
https://github.com/qemu/qemu/commit/df817297d7a5397a3383207b0e0174b464cf42ab
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv: update multi-letter extension KVM properties
We're now ready to update the multi-letter extensions status for KVM.
kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation
time to verify which user options changes host defaults (via the 'user_set'
flag) and tries to write them back to KVM.
Failure to commit a change to KVM is only ignored in case KVM doesn't
know about the extension (-EINVAL error code) and the user wanted to
disable the given extension. Otherwise we're going to abort the boot
process.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a1be1d9a77a8170822258663e5fb0580f5252536
https://github.com/qemu/qemu/commit/a1be1d9a77a8170822258663e5fb0580f5252536
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper
There are 2 places in which we need to get a pointer to a certain
property of the cpu->cfg struct based on property offset. Next patch
will add a couple more.
Create a helper to avoid repeating this code over and over.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b9f822215ee58b57863bc082c322bb88529bd958
https://github.com/qemu/qemu/commit/b9f822215ee58b57863bc082c322bb88529bd958
Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M target/riscv/kvm.c
Log Message:
-----------
target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM
If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
Linux Kernel will fail to detect the availability of the CBOM/CBOZ
extensions, regardless of the contents of the 'riscv,isa' DT prop.
The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes,
so let's expose them as user properties like it is already done with
TCG.
This will also require us to determine proper blocksize values during
init() time since the FDT is already created during realize(). We'll
take a ride in kvm_riscv_init_multiext_cfg() to do it. Note that we
don't need to fetch both cbom and cboz blocksizes every time: check for
their parent extensions (icbom and icboz) and only read the blocksizes
if needed.
In contrast with cbom|z_blocksize properties from TCG, the user is not
able to set any value that is different from the 'host' value when
running KVM. KVM can be particularly harsh dealing with it: a ENOTSUPP
can be thrown for the mere attempt of executing kvm_set_one_reg() for
these 2 regs.
Hopefully we don't need to call kvm_set_one_reg() for these regs.
We'll check if the user input matches the host value in
kvm_cpu_set_cbomz_blksize(), the set() accessor for both blocksize
properties. We'll fail fast since it's already known to not be
supported.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: a47842d16653b4f73b5d56ff0c252dd8a329481b
https://github.com/qemu/qemu/commit/a47842d16653b4f73b5d56ff0c252dd8a329481b
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/riscv.c
M disas/riscv.h
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzfa.c.inc
M target/riscv/translate.c
M tests/tcg/riscv64/Makefile.target
A tests/tcg/riscv64/test-fcvtmod.c
Log Message:
-----------
riscv: Add support for the Zfa extension
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since QEMU does not support the RISC-V quad-precision floating-point
ISA extension (Q), this patch does not include the instructions that
depend on this extension. All other instructions are included in this
patch.
The Zfa specification can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
The patch also includes a TCG test for the fcvtmod.w.d instruction.
The test cases test for correct results and flag behaviour.
Note, that the Zfa specification requires fcvtmod's flag behaviour
to be identical to a fcvt with the same operands (which is also
tested).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 27076d03990feba9e2f0d1eb955c66f711411b80
https://github.com/qemu/qemu/commit/27076d03990feba9e2f0d1eb955c66f711411b80
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M qga/main.c
Log Message:
-----------
qga: Rename ga_disable_not_allowed -> ga_disable_not_allowed_freeze
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 133789e1bf369d592a67297f57e4adb2b7c64c3f
https://github.com/qemu/qemu/commit/133789e1bf369d592a67297f57e4adb2b7c64c3f
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M docs/interop/qemu-ga.rst
M qga/main.c
Log Message:
-----------
qga: Add new option --allow-rpcs
The allow-rpcs option accepts a comma-separated list of RPCs to
enable. This option is opposite to --block-rpcs. Using --block-rpcs
and --allow-rpcs at the same time is not allowed.
resolves: https://gitlab.com/qemu-project/qemu/-/issues/1505
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: fcd1ab3add662316d6b5219edf40122e4d9c57d0
https://github.com/qemu/qemu/commit/fcd1ab3add662316d6b5219edf40122e4d9c57d0
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M tests/unit/test-qga.c
Log Message:
-----------
qga: Add tests for --allow-rpcs option
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 925d05d38a2bc76b5a49359370650a820bc891da
https://github.com/qemu/qemu/commit/925d05d38a2bc76b5a49359370650a820bc891da
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M qga/vss-win32/meson.build
A qga/vss-win32/vss-debug.cpp
A qga/vss-win32/vss-debug.h
Log Message:
-----------
QGA VSS: Add wrapper to send log to debugger and stderr
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 2f84cf699460f1182402b250064d12d4ab32ef4d
https://github.com/qemu/qemu/commit/2f84cf699460f1182402b250064d12d4ab32ef4d
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M qga/vss-win32/install.cpp
M qga/vss-win32/requester.cpp
Log Message:
-----------
QGA VSS: Replace 'fprintf(stderr' with qga_debug
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 24eecad3ad47e5660c12aff9c3ab6b365f28a9bd
https://github.com/qemu/qemu/commit/24eecad3ad47e5660c12aff9c3ab6b365f28a9bd
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M qga/vss-win32/requester.cpp
Log Message:
-----------
QGA VSS: Print error in err_set
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 61df91b33caf646cd39f9879d4b190eab5b7201b
https://github.com/qemu/qemu/commit/61df91b33caf646cd39f9879d4b190eab5b7201b
Author: Konstantin Kostiuk <kkostiuk@redhat.com>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M qga/vss-win32/install.cpp
M qga/vss-win32/provider.cpp
M qga/vss-win32/requester.cpp
Log Message:
-----------
QGA VSS: Add log in functions begin/end
Add several qga_debug() statements in functions.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
Commit: 94d68c11362240a26ce425f56e2451d88f6814e1
https://github.com/qemu/qemu/commit/94d68c11362240a26ce425f56e2451d88f6814e1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M disas/meson.build
A disas/riscv-xthead.c
A disas/riscv-xthead.h
A disas/riscv-xventana.c
A disas/riscv-xventana.h
M disas/riscv.c
A disas/riscv.h
M docs/system/riscv/virt.rst
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/sifive_e_aon.c
M hw/riscv/Kconfig
M hw/riscv/sifive_e.c
M hw/riscv/virt.c
A include/hw/misc/sifive_e_aon.h
M include/hw/riscv/sifive_e.h
M linux-user/riscv/syscall32_nr.h
M linux-user/riscv/syscall64_nr.h
M linux-user/syscall.c
M meson.build
M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
M roms/opensbi
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/fpu_helper.c
M target/riscv/helper.h
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvbf16.c.inc
A target/riscv/insn_trans/trans_rvzfa.c.inc
M target/riscv/insn_trans/trans_rvzfh.c.inc
M target/riscv/kvm.c
M target/riscv/kvm_riscv.h
M target/riscv/op_helper.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
M tests/avocado/riscv_opensbi.py
M tests/qtest/meson.build
A tests/qtest/sifive-e-aon-watchdog-test.c
M tests/tcg/riscv64/Makefile.target
A tests/tcg/riscv64/test-fcvtmod.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20230710-1' of
https://github.com/alistair23/qemu into staging
Third RISC-V PR for 8.1
* Use xl instead of mxl for disassemble
* Factor out extension tests to cpu_cfg.h
* disas/riscv: Add vendor extension support
* disas/riscv: Add support for XVentanaCondOps
* disas/riscv: Add support for XThead* instructions
* Fix mstatus related problems
* Fix veyron-v1 CPU properties
* Fix the xlen for data address when MPRV=1
* opensbi: Upgrade from v1.2 to v1.3
* Enable 32-bit Spike OpenSBI boot testing
* Support the watchdog timer of HiFive 1 rev b
* Only build qemu-system-riscv$$ on rv$$ host
* Add RVV registers to log
* Restrict ACLINT to TCG
* Add syscall riscv_hwprobe
* Add support for BF16 extensions
* KVM_RISCV_SET_TIMER macro is not configured correctly
* Generate devicetree only after machine initialization is complete
* virt: Convert fdt_load_addr to uint64_t
* KVM: fixes and enhancements
* Add support for the Zfa extension
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# gpg: Signature made Mon 10 Jul 2023 01:30:33 PM BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu:
(54 commits)
riscv: Add support for the Zfa extension
target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM
target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper
target/riscv: update multi-letter extension KVM properties
target/riscv/cpu.c: create KVM mock properties
target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()
target/riscv/cpu.c: add satp_mode properties earlier
target/riscv/kvm.c: add multi-letter extension KVM properties
target/riscv/kvm.c: update KVM MISA bits
target/riscv: add KVM specific MISA properties
target/riscv/cpu: add misa_ext_info_arr[]
target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU
target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs
target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids()
target/riscv: use KVM scratch CPUs to init KVM properties
target/riscv/cpu.c: restrict 'marchid' value
target/riscv/cpu.c: restrict 'mimpid' value
target/riscv/cpu.c: restrict 'mvendorid' value
hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set
target/riscv: skip features setup for KVM CPUs
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: adc97c4b808bb23d6bb17b8871787333af0086d2
https://github.com/qemu/qemu/commit/adc97c4b808bb23d6bb17b8871787333af0086d2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-07-10 (Mon, 10 Jul 2023)
Changed paths:
M docs/interop/qemu-ga.rst
M qga/main.c
M qga/vss-win32/install.cpp
M qga/vss-win32/meson.build
M qga/vss-win32/provider.cpp
M qga/vss-win32/requester.cpp
A qga/vss-win32/vss-debug.cpp
A qga/vss-win32/vss-debug.h
M tests/unit/test-qga.c
Log Message:
-----------
Merge tag 'qga-pull-2023-07-10' of https://github.com/kostyanf14/qemu into
staging
qga-pull-2023-07-10
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# gpg: Signature made Mon 10 Jul 2023 02:17:19 PM BST
# gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7
# gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign)
<kkostiuk@redhat.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7
* tag 'qga-pull-2023-07-10' of https://github.com/kostyanf14/qemu:
QGA VSS: Add log in functions begin/end
QGA VSS: Print error in err_set
QGA VSS: Replace 'fprintf(stderr' with qga_debug
QGA VSS: Add wrapper to send log to debugger and stderr
qga: Add tests for --allow-rpcs option
qga: Add new option --allow-rpcs
qga: Rename ga_disable_not_allowed -> ga_disable_not_allowed_freeze
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/8d309a3a97e2...adc97c4b808b