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[Qemu-commits] [qemu/qemu] 765fdc: target/openrisc: Set EPCR to next PC

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 765fdc: target/openrisc: Set EPCR to next PC on FPE except...
Date: Wed, 09 Aug 2023 18:16:00 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 765fdc1e8355d4bae563b3b185c5f9d079384164
  Author: Stafford Horne <shorne@gmail.com>
  Date:   2023-07-31 (Mon, 31 Jul 2023)

  Changed paths:
    M target/openrisc/interrupt.c

  Log Message:
  target/openrisc: Set EPCR to next PC on FPE exceptions

The architecture specification calls for the EPCR to be set to "Address
of next not executed instruction" when there is a floating point
exception (FPE).  This was not being done, so fix it by using the same
pattern as syscall.  Also, we move this logic down to be done for
instructions not in the delay slot as called for by the architecture

Without this patch FPU exceptions will loop, as the exception handling
will always return back to the failed floating point instruction.

This was not noticed in earlier testing because:

 1. The compiler usually generates code which clobbers the input operand
    such as:

      lf.div.s r19,r17,r19

 2. The target will store the operation output before to the register
    before handling the exception.  So an operation such as:

      float a = 100.0f;
      float b = 0.0f;
      float c = a / b;    /* lf.div.s r19,r17,r19 */

    Will first execute:

      100 / 0    -> Store inf to c (r19)
                 -> triggering divide by zero exception
                 -> handle and return

    Then it will execute:

      100 / inf  -> Store 0 to c  (no exception)

To confirm the looping behavior and the fix I used the following:

    float fpu_div(float a, float b) {
        float c;
        asm volatile("lf.div.s %0, %1, %2"
                      : "+r" (c)
                      : "r" (a), "r" (b));
        return c;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>

  Commit: 64d3be986f9e2379bc688bf1d0aca0557e0035ca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-09 (Wed, 09 Aug 2023)

  Changed paths:
    M target/openrisc/interrupt.c

  Log Message:
  Merge tag 'or1k-pull-request-20230809' of https://github.com/stffrdhrn/qemu 
into staging

OpenRISC FPU Fix for 8.1

A patch to pass the correct exception address when handling floating
point exceptions.

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# =yZi9
# gpg: Signature made Wed 09 Aug 2023 01:31:23 PM PDT
# gpg:                using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* tag 'or1k-pull-request-20230809' of https://github.com/stffrdhrn/qemu:
  target/openrisc: Set EPCR to next PC on FPE exceptions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Compare: https://github.com/qemu/qemu/compare/e53e2e2a1bfe...64d3be986f9e

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