qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 3d449b: hw/pci-host: Allow extended config sp


From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 3d449b: hw/pci-host: Allow extended config space access fo...
Date: Fri, 11 Aug 2023 14:47:13 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 3d449bc6030904ead784a4e4644c9640c2152796
      
https://github.com/qemu/qemu/commit/3d449bc6030904ead784a4e4644c9640c2152796
  Author: Jason Chien <jason.chien@sifive.com>
  Date:   2023-08-11 (Fri, 11 Aug 2023)

  Changed paths:
    M hw/pci-host/designware.c

  Log Message:
  -----------
  hw/pci-host: Allow extended config space access for Designware PCIe host

In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCIe bus. Thus, the extended configuration space is not accessible
on "dw-pcie". The issue can be resolved by adding the
PCI_BUS_EXTENDED_CONFIG_SPACE flag to "pcie" before "dw-pcie" is realized.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Message-Id: <20230809102257.25121-1-jason.chien@sifive.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Jason Chien &lt;<a href="mailto:jason.chien@sifive.com"; 
target="_blank">jason.chien@sifive.com</a>&gt;<br>


  Commit: 0f936247e8ed0ab5fb7e75827dd8c8f73d5ef4b5
      
https://github.com/qemu/qemu/commit/0f936247e8ed0ab5fb7e75827dd8c8f73d5ef4b5
  Author: Guoyi Tu <tugy@chinatelecom.cn>
  Date:   2023-08-11 (Fri, 11 Aug 2023)

  Changed paths:
    M hw/pci/pci.c

  Log Message:
  -----------
  pci: Fix the update of interrupt disable bit in PCI_COMMAND register

The PCI_COMMAND register is located at offset 4 within
the PCI configuration space and occupies 2 bytes. The
interrupt disable bit is at the 10th bit, which corresponds
to the byte at offset 5 in the PCI configuration space.

In our testing environment, the guest driver may directly
updates the byte at offset 5 in the PCI configuration space.
The backtrace looks like as following:
    at hw/pci/pci.c:1442
    at hw/virtio/virtio-pci.c:605
    val=5, len=1) at hw/pci/pci_host.c:81

In this situation, the range_covers_byte function called
by the pci_default_write_config function will return false,
resulting in the inability to handle the interrupt disable
update event.

To fix this issue, we can use the ranges_overlap function
instead of range_covers_byte to determine whether the interrupt
bit has been updated.

Signed-off-by: Guoyi Tu <tugy@chinatelecom.cn>
Signed-off-by: yuanminghao <yuanmh12@chinatelecom.cn>
Message-Id: <ce2d0437-8faa-4d61-b536-4668f645a959@chinatelecom.cn>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes: b6981cb57be5 ("pci: interrupt disable bit support")


  Commit: 44e13cb441e08cb4635914ca03d95a282fb70e5c
      
https://github.com/qemu/qemu/commit/44e13cb441e08cb4635914ca03d95a282fb70e5c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-11 (Fri, 11 Aug 2023)

  Changed paths:
    M hw/pci-host/designware.c
    M hw/pci/pci.c

  Log Message:
  -----------
  Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu 
into staging

pci: last minute bugfixes

two fixes that seem very safe and important enough to sneak
in before the release.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# -----BEGIN PGP SIGNATURE-----
#
# iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmTWXvIPHG1zdEByZWRo
# YXQuY29tAAoJECgfDbjSjVRpe7sH/0KteOBt324LUYZ+4NR6EQE5KDsCANGiySBK
# r0B6lhcFHvNd2ej0g2hW7lL6nVVCQBkJLLzfNIR/aHkeCmOttfbhv4eF4S6Ho27d
# DpkXCPZRT6F11gY7G1swFapNS/f0P7F5LGRjq4sbuw3FpyHBz0DqCQ0GOab2Qorq
# VfuOfA01nYGNzHOKrEL7k9Io55oqPVcAe+5TaipNCQ4nW82i32ItTyFjQFdLIAay
# qY4HEwP9vPuVwWNdQjXJNfirLMO5GQfEbyKDAjap2sL25zAV2w+mgn7xg/xkTfM6
# iMX2m14lKRMy2hr8dEVh/XdLf7loAN1jSE8/Wdt+PEaexolqxCM=
# =1GLE
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 11 Aug 2023 09:16:50 AM PDT
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu:
  pci: Fix the update of interrupt disable bit in PCI_COMMAND register
  hw/pci-host: Allow extended config space access for Designware PCIe host

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/3944e93af06f...44e13cb441e0



reply via email to

[Prev in Thread] Current Thread [Next in Thread]