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[Qemu-commits] [qemu/qemu] 2f7350: gitlab: enable ccache for many build


From: Alex Bennée
Subject: [Qemu-commits] [qemu/qemu] 2f7350: gitlab: enable ccache for many build jobs
Date: Thu, 31 Aug 2023 05:31:42 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 2f7350cd43ebda0011c9cf191c621eed1439bcf2
      
https://github.com/qemu/qemu/commit/2f7350cd43ebda0011c9cf191c621eed1439bcf2
  Author: Daniel P. Berrangé <berrange@redhat.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M .gitlab-ci.d/buildtest-template.yml
    M .gitlab-ci.d/crossbuild-template.yml
    M .gitlab-ci.d/windows.yml
    M docs/devel/ci-jobs.rst.inc
    M tests/docker/dockerfiles/debian-hexagon-cross.docker

  Log Message:
  -----------
  gitlab: enable ccache for many build jobs

The `ccache` tool can be very effective at reducing compilation times
when re-running pipelines with only minor changes each time. For example
a fresh 'build-system-fedora' job will typically take 20 minutes on the
gitlab.com shared runners. With ccache this is reduced to as little as
6 minutes.

Normally meson would auto-detect existance of ccache in $PATH and use
it automatically, but the way we wrap meson from configure breaks this,
as we're passing in an config file with explicitly set compiler paths.
Thus we need to add $CCACHE_WRAPPERSPATH to the front of $PATH. For
unknown reasons if doing this in msys though, gcc becomes unable to
invoke 'cc1' when run from meson. For msys we thus set CC='ccache gcc'
before invoking 'configure' instead.

A second problem with msys is that cache misses are incredibly
expensive, so enabling ccache massively slows down the build when
the cache isn't well populated. This is suspected to be a result of
the cost of spawning processes under the msys architecture. To deal
with this we set CCACHE_DEPEND=1 which enables ccache's 'depend_only'
strategy. This avoids extra spawning of the pre-processor during
cache misses, with the downside that is it less likely ccache will
find a cache hit after semantically benign compiler flag changes.
This is the lesser of two evils, as otherwise we can't use ccache
at all under msys and remain inside the job time limit.

If people are finding ccache to hurt their pipelines, it can be
disabled by setting the 'CCACHE_DISABLE=1' env variable against
their gitlab fork CI settings.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230804111054.281802-2-berrange@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-2-alex.bennee@linaro.org>


  Commit: 6445c2cace9f284e8326510c01d6d83c2bef12da
      
https://github.com/qemu/qemu/commit/6445c2cace9f284e8326510c01d6d83c2bef12da
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M tests/docker/Makefile.include

  Log Message:
  -----------
  tests/docker: cleanup non-verbose output

Even with --quiet docker will spam the sha256 to the console. Avoid
this by redirecting stdout. While we are at it fix the name we echo
which was broken during 0b1a649047 (tests/docker: use direct RUNC call
to build containers).

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-3-alex.bennee@linaro.org>


  Commit: bb16cb45192b344c8bd5e3c2f423b96fb438ed29
      
https://github.com/qemu/qemu/commit/bb16cb45192b344c8bd5e3c2f423b96fb438ed29
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M tests/tcg/aarch64/Makefile.target
    M tests/tcg/multiarch/system/Makefile.softmmu-target

  Log Message:
  -----------
  tests/tcg: remove quoting for info output

This avoids ugly multi-line wrapping for the test on non V=1 builds.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-4-alex.bennee@linaro.org>


  Commit: 4b77429adbecf970d0ebb7213b99b82771b6368f
      
https://github.com/qemu/qemu/commit/4b77429adbecf970d0ebb7213b99b82771b6368f
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M docs/devel/style.rst

  Log Message:
  -----------
  docs/style: permit inline loop variables

I've already wasted enough of my time debugging aliased variables in
deeply nested loops. While not scattering variable declarations around
is a good aim I think we can make an exception for stuff used inside a
loop.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-5-alex.bennee@linaro.org>


  Commit: e05a4beaecc346346c1fa7d5c1d13941dc609c80
      
https://github.com/qemu/qemu/commit/e05a4beaecc346346c1fa7d5c1d13941dc609c80
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M .gitlab-ci.d/cirrus.yml

  Log Message:
  -----------
  .gitlab-ci.d/cirrus.yml: Update FreeBSD to v13.2

The FreeBSD CI job started to fail due to linking problems ... time
to update to the latest version to get this fixed.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20230823144533.230477-1-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-6-alex.bennee@linaro.org>


  Commit: d84842be6c53c03c9498101b509a25961ed5856f
      
https://github.com/qemu/qemu/commit/d84842be6c53c03c9498101b509a25961ed5856f
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    R tests/guest-debug/test-gdbstub.py

  Log Message:
  -----------
  tests: remove test-gdbstub.py

This isn't directly called by our CI and because it doesn't run via
our run-test.py script does things slightly differently. Lets remove
it as we have plenty of working in-tree tests now for various aspects
of gdbstub.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-7-alex.bennee@linaro.org>


  Commit: a8fea70f656416b2ed7d388fbcc7cc6cda126a82
      
https://github.com/qemu/qemu/commit/a8fea70f656416b2ed7d388fbcc7cc6cda126a82
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M tests/guest-debug/run-test.py
    M tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
    M tests/tcg/aarch64/gdbstub/test-sve.py
    M tests/tcg/multiarch/gdbstub/memory.py
    M tests/tcg/multiarch/gdbstub/sha1.py
    M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
    M tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
    M tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
    M tests/tcg/s390x/gdbstub/test-signals-s390x.py
    M tests/tcg/s390x/gdbstub/test-svc.py

  Log Message:
  -----------
  tests/tcg: clean-up gdb confirm/pagination settings

We can do this all in the run-test.py script so remove the extraneous
bits from the individual tests which got copied from the original
non-CI gdb tests.

Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-8-alex.bennee@linaro.org>


  Commit: 761e3c10881b5f521b19b713cf8d16c72c47affb
      
https://github.com/qemu/qemu/commit/761e3c10881b5f521b19b713cf8d16c72c47affb
  Author: Matheus Branco Borella <dark.ryu.550@gmail.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M gdbstub/gdbstub.c
    A tests/tcg/multiarch/gdbstub/interrupt.py
    M tests/tcg/multiarch/system/Makefile.softmmu-target
    A tests/tcg/multiarch/system/interrupt.c

  Log Message:
  -----------
  gdbstub: fixes cases where wrong threads were reported to GDB on SIGINT

This fix is implemented by having the vCont handler set the value of
`gdbserver_state.c_cpu` if any threads are to be resumed. The specific
CPU picked is arbitrarily from the ones to be resumed, but it should
be okay, as all GDB cares about is that it is a resumed thread.

Signed-off-by: Matheus Branco Borella <dark.ryu.550@gmail.com>
Message-Id: <20230804182633.47300-2-dark.ryu.550@gmail.com>
[AJB: style and whitespace fixes]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1725
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-9-alex.bennee@linaro.org>


  Commit: 5b030993dba1bbb841431506c0919c7a7bef986c
      
https://github.com/qemu/qemu/commit/5b030993dba1bbb841431506c0919c7a7bef986c
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M gdbstub/gdbstub.c

  Log Message:
  -----------
  gdbstub: remove unused user_ctx field

This was always NULL so drop it.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-10-alex.bennee@linaro.org>


  Commit: 56e534bd116afda6f7b9ef96691549373c64040d
      
https://github.com/qemu/qemu/commit/56e534bd116afda6f7b9ef96691549373c64040d
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M gdbstub/gdbstub.c
    M gdbstub/internals.h

  Log Message:
  -----------
  gdbstub: refactor get_feature_xml

Try to bring up the code to more modern standards by:

  - use dynamic GString built xml over a fixed buffer
  - use autofree to save on explicit g_free() calls
  - don't hand hack strstr to find the delimiter
  - fix up style of xml_builtin and invert loop

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-11-alex.bennee@linaro.org>


  Commit: d0e5fa849db4d729e0607ef597cb31eac79532a3
      
https://github.com/qemu/qemu/commit/d0e5fa849db4d729e0607ef597cb31eac79532a3
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M gdbstub/gdbstub.c
    M gdbstub/internals.h
    M gdbstub/softmmu.c
    M gdbstub/user.c
    M include/exec/gdbstub.h
    M target/arm/gdbstub.c
    M target/ppc/gdbstub.c

  Log Message:
  -----------
  gdbstub: replace global gdb_has_xml with a function

Try and make the self reported global hack a little less hackish by
providing a query function instead. As gdb_has_xml was always set if
we negotiated XML we can now use the presence of ->target_xml as the
test instead.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-12-alex.bennee@linaro.org>


  Commit: 8dd7a4b3487ab93ff8fddc5f818942ff39d4550f
      
https://github.com/qemu/qemu/commit/8dd7a4b3487ab93ff8fddc5f818942ff39d4550f
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M gdbstub/gdbstub.c
    M include/exec/gdbstub.h

  Log Message:
  -----------
  gdbstub: move comment for gdb_register_coprocessor

Use proper kdoc style comments for this API function.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230829161528.2707696-13-alex.bennee@linaro.org>


  Commit: 0c8ab1cddd6c1bf4e3722fcea111e614c22dcc09
      
https://github.com/qemu/qemu/commit/0c8ab1cddd6c1bf4e3722fcea111e614c22dcc09
  Author: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M hw/arm/xen_arm.c
    M include/hw/xen/xen_native.h

  Log Message:
  -----------
  xen_arm: Create virtio-mmio devices during initialization

In order to use virtio backends we need to allocate virtio-mmio
parameters (irq and base) and register corresponding buses.

Use the constants defined in public header arch-arm.h to be
aligned with the toolstack. So the number of current supported
virtio-mmio devices is 10.

For the interrupts triggering use already existing on Arm
device-model hypercall.

The toolstack should then insert the same amount of device nodes
into guest device-tree.

Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>


  Commit: 560142190bc347fdd4511a795bdcff768799519d
      
https://github.com/qemu/qemu/commit/560142190bc347fdd4511a795bdcff768799519d
  Author: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
  Date:   2023-08-30 (Wed, 30 Aug 2023)

  Changed paths:
    M hw/arm/xen_arm.c
    M include/hw/xen/xen_native.h

  Log Message:
  -----------
  xen_arm: Initialize RAM and add hi/low memory regions

In order to use virtio backends we need to initialize RAM for the
xen-mapcache (which is responsible for mapping guest memory using foreign
mapping) to work. Calculate and add hi/low memory regions based on
machine->ram_size.

Use the constants defined in public header arch-arm.h to be aligned with the xen
toolstack.

While using this machine, the toolstack should then pass real ram_size using
"-m" arg. If "-m" is not given, create a QEMU machine without IOREQ and other
emulated devices like TPM and VIRTIO. This is done to keep this QEMU machine
usable for /etc/init.d/xencommons.

Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com>
Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <stefano.stabellini@amd.com>


  Commit: ae4acc696f34bf0cb8865521c16ff378b19915b3
      
https://github.com/qemu/qemu/commit/ae4acc696f34bf0cb8865521c16ff378b19915b3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Reduce dcz_blocksize to uint8_t

This value is only 4 bits wide.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 851ec6eba56d0153574c042bff05a3d0f235a00e
      
https://github.com/qemu/qemu/commit/851ec6eba56d0153574c042bff05a3d0f235a00e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/mte_helper.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Allow cpu to configure GM blocksize

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7134cb07b749b669c25526c044b19204686f4663
      
https://github.com/qemu/qemu/commit/7134cb07b749b669c25526c044b19204686f4663
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/tcg/mte_helper.c

  Log Message:
  -----------
  target/arm: Support more GM blocksizes

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cd305b5f311d6ecea6cf487f3ec78b84bcd60d63
      
https://github.com/qemu/qemu/commit/cd305b5f311d6ecea6cf487f3ec78b84bcd60d63
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: When tag memory is not present, set MTE=1

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d8100822d6988cf7837aa780eaa24de6752b1c59
      
https://github.com/qemu/qemu/commit/d8100822d6988cf7837aa780eaa24de6752b1c59
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Introduce make_ccsidr64

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6d482423fcecb34056013268fa552b1ce2efcfeb
      
https://github.com/qemu/qemu/commit/6d482423fcecb34056013268fa552b1ce2efcfeb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/helper.c
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Apply access checks to neoverse-n1 special registers

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 87da10b45ce50b55c0306862a511c77243b1b065
      
https://github.com/qemu/qemu/commit/87da10b45ce50b55c0306862a511c77243b1b065
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Apply access checks to neoverse-v1 special registers

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3d5f45ec895b278bfc442a436eebefab598f416a
      
https://github.com/qemu/qemu/commit/3d5f45ec895b278bfc442a436eebefab598f416a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: df9a391757c7fc5a6c88f6d32b82d6f2f860bd1d
      
https://github.com/qemu/qemu/commit/df9a391757c7fc5a6c88f6d32b82d6f2f860bd1d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/tcg/cpu32.c
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Implement FEAT_HPDS2 as a no-op

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9e771a2fc68d98c5719b877e008d1dca64e6896e
      
https://github.com/qemu/qemu/commit/9e771a2fc68d98c5719b877e008d1dca64e6896e
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: properly document FEAT_CRC32

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6f97cfd8e0e081c9f5e4ee27984b239912b911b9
      
https://github.com/qemu/qemu/commit/6f97cfd8e0e081c9f5e4ee27984b239912b911b9
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx6ul.c
    M include/hw/arm/fsl-imx6ul.h

  Log Message:
  -----------
  Remove i.MX7 IOMUX GPR device from i.MX6UL

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 
48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0cd4926b855c491c88facaa0abeaf910f7d6ff01
      
https://github.com/qemu/qemu/commit/0cd4926b855c491c88facaa0abeaf910f7d6ff01
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx6ul.c
    M include/hw/arm/fsl-imx6ul.h

  Log Message:
  -----------
  Refactor i.MX6UL processor code

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 
d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f6020845e20d1cc033770bbff8c1d92855d2bba5
      
https://github.com/qemu/qemu/commit/f6020845e20d1cc033770bbff8c1d92855d2bba5
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx6ul.c
    M include/hw/arm/fsl-imx6ul.h

  Log Message:
  -----------
  Add i.MX6UL missing devices.

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 
59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 45b8b34dfacb14503d6f8692fa450f81175328e6
      
https://github.com/qemu/qemu/commit/45b8b34dfacb14503d6f8692fa450f81175328e6
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx7.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  Refactor i.MX7 processor code

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 
59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 736988a040b58b7021445580634d4d2d35a4a6cc
      
https://github.com/qemu/qemu/commit/736988a040b58b7021445580634d4d2d35a4a6cc
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx7.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  Add i.MX7 missing TZ devices and memory regions

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add various memory segments
  - OCRAM
  - OCRAM EPDC
  - OCRAM PXP
  - OCRAM S
  - ROM
  - CAAM

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 
f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 12517bc978e62ce19df0160ad2ef229169a567b2
      
https://github.com/qemu/qemu/commit/12517bc978e62ce19df0160ad2ef229169a567b2
  Author: Jean-Christophe Dubois <jcd@tribudubois.net>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/fsl-imx7.c
    A hw/misc/imx7_src.c
    M hw/misc/meson.build
    M hw/misc/trace-events
    M include/hw/arm/fsl-imx7.h
    A include/hw/misc/imx7_src.h

  Log Message:
  -----------
  Add i.MX7 SRC device implementation

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 
ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 35aa6715ddcd9748bae5bc01563331e8eae8d7cf
      
https://github.com/qemu/qemu/commit/35aa6715ddcd9748bae5bc01563331e8eae8d7cf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/tcg/helper-a64.c

  Log Message:
  -----------
  target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org


  Commit: 7038b6e4e71d9fb3a234e00da31c222d3e97dd5c
      
https://github.com/qemu/qemu/commit/7038b6e4e71d9fb3a234e00da31c222d3e97dd5c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/rtc/m48t59.c

  Log Message:
  -----------
  hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()

In the m48t59 device we almost always use 64-bit arithmetic when
dealing with time_t deltas.  The one exception is in set_alarm(),
which currently uses a plain 'int' to hold the difference between two
time_t values.  Switch to int64_t instead to avoid any possible
overflow issues.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: 279695a4a4472c41d8764317e4fae04d93ee2b42
      
https://github.com/qemu/qemu/commit/279695a4a4472c41d8764317e4fae04d93ee2b42
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/rtc/twl92230.c

  Log Message:
  -----------
  hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec

In the twl92230 device, use int64_t for the two state fields
sec_offset and alm_sec, because we set these to values that
are either time_t or differences between two time_t values.

These fields aren't saved in vmstate anywhere, so we can
safely widen them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: c0a63857282afebaeed606a3dca803bb3bfb6aa3
      
https://github.com/qemu/qemu/commit/c0a63857282afebaeed606a3dca803bb3bfb6aa3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/rtc/aspeed_rtc.c
    M include/hw/rtc/aspeed_rtc.h

  Log Message:
  -----------
  hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5ec008a2bd7e928d41d2a158120223311742d860
      
https://github.com/qemu/qemu/commit/5ec008a2bd7e928d41d2a158120223311742d860
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M include/sysemu/rtc.h
    M softmmu/rtc.c

  Log Message:
  -----------
  rtc: Use time_t for passing and returning time offsets

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


  Commit: b8f7959f28c4f36496bc0a694fa28bf5078152c5
      
https://github.com/qemu/qemu/commit/b8f7959f28c4f36496bc0a694fa28bf5078152c5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org


  Commit: cb0929bb1344d095c9e7980e3803562b8b3cd604
      
https://github.com/qemu/qemu/commit/cb0929bb1344d095c9e7980e3803562b8b3cd604
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/armv7m.h

  Log Message:
  -----------
  hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org


  Commit: e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb
      
https://github.com/qemu/qemu/commit/e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/armsse.c
    M hw/arm/mps2-tz.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm: Set number of MPU regions correctly for an505, an521, an524

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global 
sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org


  Commit: db1a88a5acc0df7d8a941aa772ef63c8941d1893
      
https://github.com/qemu/qemu/commit/db1a88a5acc0df7d8a941aa772ef63c8941d1893
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M .gitlab-ci.d/buildtest-template.yml
    M .gitlab-ci.d/cirrus.yml
    M .gitlab-ci.d/crossbuild-template.yml
    M .gitlab-ci.d/windows.yml
    M docs/devel/ci-jobs.rst.inc
    M docs/devel/style.rst
    M gdbstub/gdbstub.c
    M gdbstub/internals.h
    M gdbstub/softmmu.c
    M gdbstub/user.c
    M include/exec/gdbstub.h
    M target/arm/gdbstub.c
    M target/ppc/gdbstub.c
    M tests/docker/Makefile.include
    M tests/docker/dockerfiles/debian-hexagon-cross.docker
    M tests/guest-debug/run-test.py
    R tests/guest-debug/test-gdbstub.py
    M tests/tcg/aarch64/Makefile.target
    M tests/tcg/aarch64/gdbstub/test-sve-ioctl.py
    M tests/tcg/aarch64/gdbstub/test-sve.py
    A tests/tcg/multiarch/gdbstub/interrupt.py
    M tests/tcg/multiarch/gdbstub/memory.py
    M tests/tcg/multiarch/gdbstub/sha1.py
    M tests/tcg/multiarch/gdbstub/test-proc-mappings.py
    M tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
    M tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py
    M tests/tcg/multiarch/system/Makefile.softmmu-target
    A tests/tcg/multiarch/system/interrupt.c
    M tests/tcg/s390x/gdbstub/test-signals-s390x.py
    M tests/tcg/s390x/gdbstub/test-svc.py

  Log Message:
  -----------
  Merge tag 'pull-maintainer-ominbus-300823-1' of 
https://gitlab.com/stsquad/qemu into staging

testing and gdbstub updates:

  - enable ccache for gitlab builds
  - fix various test info leakages for non V=1
  - update style to allow loop vars
  - bump FreeBSD to v13.2
  - clean-up gdbstub tests
  - various gdbstub doc and refactorings

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# =Km9m
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 30 Aug 2023 10:00:00 EDT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) 
<alex.bennee@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-maintainer-ominbus-300823-1' of https://gitlab.com/stsquad/qemu:
  gdbstub: move comment for gdb_register_coprocessor
  gdbstub: replace global gdb_has_xml with a function
  gdbstub: refactor get_feature_xml
  gdbstub: remove unused user_ctx field
  gdbstub: fixes cases where wrong threads were reported to GDB on SIGINT
  tests/tcg: clean-up gdb confirm/pagination settings
  tests: remove test-gdbstub.py
  .gitlab-ci.d/cirrus.yml: Update FreeBSD to v13.2
  docs/style: permit inline loop variables
  tests/tcg: remove quoting for info output
  tests/docker: cleanup non-verbose output
  gitlab: enable ccache for many build jobs

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 2b0612dea37802ab623e811c63a217a0b0fb9f1a
      
https://github.com/qemu/qemu/commit/2b0612dea37802ab623e811c63a217a0b0fb9f1a
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M hw/arm/xen_arm.c
    M include/hw/xen/xen_native.h

  Log Message:
  -----------
  Merge tag 'xen-virtio-2-tag' of https://gitlab.com/sstabellini/qemu into 
staging

xen-virtio-2-tag

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# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 30 Aug 2023 21:23:40 EDT
# gpg:                using RSA key D04E33ABA51F67BA07D30AEA894F8F4870E1AE90
# gpg: Good signature from "Stefano Stabellini <sstabellini@kernel.org>" 
[unknown]
# gpg:                 aka "Stefano Stabellini 
<stefano.stabellini@eu.citrix.com>" [full]
# Primary key fingerprint: D04E 33AB A51F 67BA 07D3  0AEA 894F 8F48 70E1 AE90

* tag 'xen-virtio-2-tag' of https://gitlab.com/sstabellini/qemu:
  xen_arm: Initialize RAM and add hi/low memory regions
  xen_arm: Create virtio-mmio devices during initialization

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: c4e5f9a29faadc50fed673d720199db5638fbdab
      
https://github.com/qemu/qemu/commit/c4e5f9a29faadc50fed673d720199db5638fbdab
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-08-31 (Thu, 31 Aug 2023)

  Changed paths:
    M docs/system/arm/emulation.rst
    M hw/arm/armsse.c
    M hw/arm/armv7m.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c
    M hw/arm/mps2-tz.c
    A hw/misc/imx7_src.c
    M hw/misc/meson.build
    M hw/misc/trace-events
    M hw/rtc/aspeed_rtc.c
    M hw/rtc/m48t59.c
    M hw/rtc/twl92230.c
    M include/hw/arm/armsse.h
    M include/hw/arm/armv7m.h
    M include/hw/arm/fsl-imx6ul.h
    M include/hw/arm/fsl-imx7.h
    A include/hw/misc/imx7_src.h
    M include/hw/rtc/aspeed_rtc.h
    M include/sysemu/rtc.h
    M softmmu/rtc.c
    M target/arm/cpregs.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/tcg/cpu32.c
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/helper-a64.c
    M target/arm/tcg/mte_helper.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20230831' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

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# =MFh3
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 31 Aug 2023 06:43:53 EDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20230831' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (24 commits)
  hw/arm: Set number of MPU regions correctly for an505, an521, an524
  hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
  target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
  rtc: Use time_t for passing and returning time offsets
  hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
  hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
  hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
  target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
  Add i.MX7 SRC device implementation
  Add i.MX7 missing TZ devices and memory regions
  Refactor i.MX7 processor code
  Add i.MX6UL missing devices.
  Refactor i.MX6UL processor code
  Remove i.MX7 IOMUX GPR device from i.MX6UL
  target/arm: properly document FEAT_CRC32
  target/arm: Implement FEAT_HPDS2 as a no-op
  target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
  target/arm: Apply access checks to neoverse-v1 special registers
  target/arm: Apply access checks to neoverse-n1 special registers
  target/arm: Introduce make_ccsidr64
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/156618d9ea67...c4e5f9a29faa



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