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[Qemu-commits] [qemu/qemu] bb67ec: target/hppa: Include PSW_P in tb flag


From: Alex Bennée
Subject: [Qemu-commits] [qemu/qemu] bb67ec: target/hppa: Include PSW_P in tb flags and mmu index
Date: Tue, 07 Nov 2023 01:36:32 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9
      
https://github.com/qemu/qemu/commit/bb67ec32a0bb90a4d392a778f97f1e86ed75f0a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/helper.c
    M target/hppa/mem_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Include PSW_P in tb flags and mmu index

Use a separate mmu index for PSW_P enabled vs disabled.
This means we can elide the tlb flush in cpu_hppa_put_psw
when PSW_P changes.  This turns out to be the majority
of all tlb flushes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 729cd3506dbf2dde010486de913eae56a615422c
      
https://github.com/qemu/qemu/commit/729cd3506dbf2dde010486de913eae56a615422c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/machine.c
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Rename hppa_tlb_entry to HPPATLBEntry

Rename to CamelCase per coding style.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 66866cc74fc77e6f08eaeb1054bf1e2454fa4721
      
https://github.com/qemu/qemu/commit/66866cc74fc77e6f08eaeb1054bf1e2454fa4721
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/machine.c
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Use IntervalTreeNode in HPPATLBEntry

Replace the va_b and va_b fields with the interval tree node.
The actual interval tree is not yet used.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f8cda28b8dd6f9d52042a3d45558de81e4c54e36
      
https://github.com/qemu/qemu/commit/f8cda28b8dd6f9d52042a3d45558de81e4c54e36
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Always report one page to tlb_set_page

No need to trigger the large_page_mask code unnecessarily.
Drop the now unused HPPATLBEntry.page_size field.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 09cae8255ffc6d133b32073b6d8d99b56b3379b5
      
https://github.com/qemu/qemu/commit/09cae8255ffc6d133b32073b6d8d99b56b3379b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Split out hppa_flush_tlb_range

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d7553f3591bbf495b4c35355179c793d03e106dc
      
https://github.com/qemu/qemu/commit/d7553f3591bbf495b4c35355179c793d03e106dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/machine.c
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Populate an interval tree with valid tlb entries

Complete the data structure conversion started earlier.  This reduces
the perf overhead of hppa_get_physical_address from ~5% to ~0.25%.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e12c63090be5b5eda50a9f30c8292c17823c6fb0
      
https://github.com/qemu/qemu/commit/e12c63090be5b5eda50a9f30c8292c17823c6fb0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove get_temp

Replace with tcg_temp_new without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a6779861fd7d5dc8f90e89bd1fae3e689f9b8f65
      
https://github.com/qemu/qemu/commit/a6779861fd7d5dc8f90e89bd1fae3e689f9b8f65
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove get_temp_tl

Replace with tcg_temp_new_tl without recording into ctx.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d4e5803316a85dcff78490e6c18a0a84371220e6
      
https://github.com/qemu/qemu/commit/d4e5803316a85dcff78490e6c18a0a84371220e6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove load_const

Replace with tcg_constant_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0238e678ebdfeb3a74f947f2c3cde401ae60267f
      
https://github.com/qemu/qemu/commit/0238e678ebdfeb3a74f947f2c3cde401ae60267f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/machine.c

  Log Message:
  -----------
  target/hppa: Fix hppa64 case in machine.c

Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c1f55d9795b69f17f002b7d6e8580bcd23f49be5
      
https://github.com/qemu/qemu/commit/c1f55d9795b69f17f002b7d6e8580bcd23f49be5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix load in do_load_32

The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32
not tcg_gen_qemu_ld_reg.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e1d635e871f4e0dcea7ec08309509bbb82c2047c
      
https://github.com/qemu/qemu/commit/e1d635e871f4e0dcea7ec08309509bbb82c2047c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Truncate rotate count in trans_shrpw_sar

When forcing rotate by i32, the shift count must be as well.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 72ca87535e5055852c3fa5e3913c9190e0f11911
      
https://github.com/qemu/qemu/commit/72ca87535e5055852c3fa5e3913c9190e0f11911
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix trans_ds for hppa64

This instruction always uses the input carry from bit 32,
but produces all 16 output carry bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bdcccc17acb3f4cbf85cc81601edc1f87e76e088
      
https://github.com/qemu/qemu/commit/bdcccc17acb3f4cbf85cc81601edc1f87e76e088
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix do_add, do_sub for hppa64

Select the proper carry bit for input to the arithmetic
and for output for the condition.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1e9ab9fbe06b6b343409029f5be2f184d6b69fde
      
https://github.com/qemu/qemu/commit/1e9ab9fbe06b6b343409029f5be2f184d6b69fde
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix bb_sar for hppa64

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d781cb7798e41141f377784257e27f615041603d
      
https://github.com/qemu/qemu/commit/d781cb7798e41141f377784257e27f615041603d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix extrw and depw with sar for hppa64

These are 32-bit operations regardless of processor.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bd6243a33fed93844ea24d77ed62d35f13d644e7
      
https://github.com/qemu/qemu/commit/bd6243a33fed93844ea24d77ed62d35f13d644e7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu-qom.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Introduce TYPE_HPPA64_CPU

Prepare for the qemu binary supporting both pa10 and pa20
at the same time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9cf2112be4fe84d41083435e44fa146d13d3f8d7
      
https://github.com/qemu/qemu/commit/9cf2112be4fe84d41083435e44fa146d13d3f8d7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c
    M target/hppa/cpu.h
    M target/hppa/machine.c
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Make HPPA_BTLB_ENTRIES variable

Depend on hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d3ae32d4d208bd73c8e1bc81d76017268e2455fc
      
https://github.com/qemu/qemu/commit/d3ae32d4d208bd73c8e1bc81d76017268e2455fc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.c
    M target/hppa/cpu.h

  Log Message:
  -----------
  target/hppa: Implement cpu_list

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ca4c2008f53cd08dd82789384aeba87754d15152
      
https://github.com/qemu/qemu/commit/ca4c2008f53cd08dd82789384aeba87754d15152
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M linux-user/hppa/target_elf.h
    M target/hppa/cpu.c

  Log Message:
  -----------
  target/hppa: Implement hppa_cpu_class_by_name

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 931adff3147826a27748c9cdc862cacfd0807a92
      
https://github.com/qemu/qemu/commit/931adff3147826a27748c9cdc862cacfd0807a92
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.c

  Log Message:
  -----------
  target/hppa: Update cpu_hppa_get/put_psw for hppa64

With 64-bit registers, there are 16 carry bits in the PSW.
Clear reserved bits based on cpu revision.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ccdf741c48db62319539a31bb5ae73a67316b295
      
https://github.com/qemu/qemu/commit/ccdf741c48db62319539a31bb5ae73a67316b295
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Handle absolute addresses for pa2.0

With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5718fe4cfe947cb46b188ccd9bc5f9673ad9dd5b
      
https://github.com/qemu/qemu/commit/5718fe4cfe947cb46b188ccd9bc5f9673ad9dd5b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.c

  Log Message:
  -----------
  target/hppa: Adjust hppa_cpu_dump_state for hppa64

Dump all 64 bits for pa2.0 and low 32 bits for pa1.x.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 698240d19b0d8c880a6e8c1baeec6d6048d2ca4b
      
https://github.com/qemu/qemu/commit/698240d19b0d8c880a6e8c1baeec6d6048d2ca4b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Fix hppa64 addressing

In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0.
In space_select, the bits that choose the space depend on PSW_W.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 741322f471627b829fc1ac01c16ae40cacb0c133
      
https://github.com/qemu/qemu/commit/741322f471627b829fc1ac01c16ae40cacb0c133
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass DisasContext to copy_iaoq_entry

Interface change only, no functional effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a01809737e07e2f882cf09746f348424f7c04526
      
https://github.com/qemu/qemu/commit/a01809737e07e2f882cf09746f348424f7c04526
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]

This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9a91dd845277dd1d7c4c8f37662aa076e685dccc
      
https://github.com/qemu/qemu/commit/9a91dd845277dd1d7c4c8f37662aa076e685dccc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Use copy_iaoq_entry for link in do_ibranch

We need to make sure the link is masked properly along the
use_nullify_skip path.  The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f13bf343ccdb7df14233133f42670e1b16bb6b20
      
https://github.com/qemu/qemu/commit/f13bf343ccdb7df14233133f42670e1b16bb6b20
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Mask inputs in copy_iaoq_entry

Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f3618f59f3559eae69c34e0fe621685614b4350d
      
https://github.com/qemu/qemu/commit/f3618f59f3559eae69c34e0fe621685614b4350d
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: sar register allows only 5 bits on 32-bit CPU

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: a751eb31b669d4daa27cd31996f3cd26a47b26eb
      
https://github.com/qemu/qemu/commit/a751eb31b669d4daa27cd31996f3cd26a47b26eb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass d to do_cond

Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4fe9533accedd2729667aa7568c9b5a690c15d1d
      
https://github.com/qemu/qemu/commit/4fe9533accedd2729667aa7568c9b5a690c15d1d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass d to do_sub_cond

Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b5af84233d423fba25569f4c2df338eb2be30415
      
https://github.com/qemu/qemu/commit/b5af84233d423fba25569f4c2df338eb2be30415
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass d to do_log_cond

Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4fa52edf912115e0ad7011da9f9b2e43fd99f3aa
      
https://github.com/qemu/qemu/commit/4fa52edf912115e0ad7011da9f9b2e43fd99f3aa
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass d to do_sed_cond

Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 59963d8fdf42244b8688b60b778a6209a1359fc2
      
https://github.com/qemu/qemu/commit/59963d8fdf42244b8688b60b778a6209a1359fc2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Pass d to do_unit_cond

Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0c01f9ba2df42cef26596f5fa0ff5e741fb3c37f
      
https://github.com/qemu/qemu/commit/0c01f9ba2df42cef26596f5fa0ff5e741fb3c37f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M linux-user/hppa/signal.c

  Log Message:
  -----------
  linux-user/hppa: Fixes for TARGET_ABI32

Avoid target_ulong and use abi_* types.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e207b4aa718ebe65f76775bc360408605b139a86
      
https://github.com/qemu/qemu/commit/e207b4aa718ebe65f76775bc360408605b139a86
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/gdbstub.c

  Log Message:
  -----------
  target/hppa: Drop attempted gdbstub support for hppa64

There is no support for hppa64 in gdb.  Any attempt to provide the
data for the larger hppa64 registers results in an error from gdb.
Mask CR_SAR writes to the width of the register: 5 or 6 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 08db1785449614ab35c521e365868435b0a0debd
      
https://github.com/qemu/qemu/commit/08db1785449614ab35c521e365868435b0a0debd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M configs/targets/hppa-linux-user.mak
    M target/hppa/cpu-param.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove TARGET_HPPA64

Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fa8e3bed3885522260f796ed9d2a17f693c85381
      
https://github.com/qemu/qemu/commit/fa8e3bed3885522260f796ed9d2a17f693c85381
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for logical instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: af240753331940d0f3f8be6fe625c00fc64c4398
      
https://github.com/qemu/qemu/commit/af240753331940d0f3f8be6fe625c00fc64c4398
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for unit instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 345aa35f151a446e325dc120d0b6a6bebafc4d69
      
https://github.com/qemu/qemu/commit/345aa35f151a446e325dc120d0b6a6bebafc4d69
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for cmpclr instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: faf97ba1577755eba593c59601f7a9ed93cf6728
      
https://github.com/qemu/qemu/commit/faf97ba1577755eba593c59601f7a9ed93cf6728
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for add instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 63c427c615ea927fd93901f2dfeebb62ad3bf2bc
      
https://github.com/qemu/qemu/commit/63c427c615ea927fd93901f2dfeebb62ad3bf2bc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for sub instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 84e224d4226001ed73b8da42e4ad155cf80b1eef
      
https://github.com/qemu/qemu/commit/84e224d4226001ed73b8da42e4ad155cf80b1eef
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for bb instructions

Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e9efd4bcdc5d94eb9e1bbc53e2d635438ba166a7
      
https://github.com/qemu/qemu/commit/e9efd4bcdc5d94eb9e1bbc53e2d635438ba166a7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode d for cmpb instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c65c3ee16b6e5382a93e3ed28fccf2fa545794e8
      
https://github.com/qemu/qemu/commit/c65c3ee16b6e5382a93e3ed28fccf2fa545794e8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode CMPIB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f25d316098dd52ac74adf9416713cfe68c72f66e
      
https://github.com/qemu/qemu/commit/f25d316098dd52ac74adf9416713cfe68c72f66e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Decode ADDB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 51416c4e41a2cfc084a08d8c78c8b90f14ea8661
      
https://github.com/qemu/qemu/commit/51416c4e41a2cfc084a08d8c78c8b90f14ea8661
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement LDD, LDCD, LDDA, STD, STDA

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 72ae4f2b82acbcbe32d30432e41e12b7b8f2785d
      
https://github.com/qemu/qemu/commit/72ae4f2b82acbcbe32d30432e41e12b7b8f2785d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement DEPD, DEPDI

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bd792da3548cb8fcbfb58b37343f0cbc8500dc5f
      
https://github.com/qemu/qemu/commit/bd792da3548cb8fcbfb58b37343f0cbc8500dc5f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement EXTRD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f7b775a9c0750873ae68d33721df5becaf62a59a
      
https://github.com/qemu/qemu/commit/f7b775a9c0750873ae68d33721df5becaf62a59a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement SHRPD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a8966ba70a6fdf5602d7235f24215a75aea5c98a
      
https://github.com/qemu/qemu/commit/a8966ba70a6fdf5602d7235f24215a75aea5c98a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 25460fc5a71ef2bf6679d263e16f86ed7bb341a5
      
https://github.com/qemu/qemu/commit/25460fc5a71ef2bf6679d263e16f86ed7bb341a5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement STDBY

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8577f354792414a2b24ef72c64730ed0f6bb071e
      
https://github.com/qemu/qemu/commit/8577f354792414a2b24ef72c64730ed0f6bb071e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/mem_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement IDTLBT, IITLBT

Rename the existing insert tlb helpers to emphasize that they
are for pa1.1 cpus.  Implement a combined i/d tlb for pa2.0.
Still missing is the new 'P' tlb bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a4529fa83b3c1e8cd3303161a5895a5adc01a076
      
https://github.com/qemu/qemu/commit/a4529fa83b3c1e8cd3303161a5895a5adc01a076
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  hw/hppa: Use uint32_t instead of target_ureg

The size of target_ureg is going to change.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c53e401ed9ffe4a5f5fe914828c0bfe9bf813cff
      
https://github.com/qemu/qemu/commit/c53e401ed9ffe4a5f5fe914828c0bfe9bf813cff
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu-param.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/helper.c
    M target/hppa/helper.h
    M target/hppa/int_helper.c
    M target/hppa/machine.c
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    M target/hppa/sys_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove TARGET_REGISTER_BITS

Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6fd0c7bc91d81244c8a0f418ac8d19bca0c20577
      
https://github.com/qemu/qemu/commit/6fd0c7bc91d81244c8a0f418ac8d19bca0c20577
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove most of the TARGET_REGISTER_BITS redirections

Remove all but those intended to change type to or from i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 967662cd5a0c05544c5d4dc1ba20b24fa42af6c4
      
https://github.com/qemu/qemu/commit/967662cd5a0c05544c5d4dc1ba20b24fa42af6c4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Remove remaining TARGET_REGISTER_BITS redirections

The conversions to/from i64 can be eliminated entirely,
folding computation into adjacent operations.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ea6c40b0f13e8aa79ffe27031ad260cb91b6a935
      
https://github.com/qemu/qemu/commit/ea6c40b0f13e8aa79ffe27031ad260cb91b6a935
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/machine.c

  Log Message:
  -----------
  target/hppa: Adjust vmstate_env for pa2.0 tlb

Split out the tlb to a subsection so that it can be separately
versioned -- the format is only partially following the architecture
and is partially guided by the qemu implementation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: aac0f603de963fe6dc8a4b1c83dc43006635f1bc
      
https://github.com/qemu/qemu/commit/aac0f603de963fe6dc8a4b1c83dc43006635f1bc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Use tcg_temp_new_i64 not tcg_temp_new

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d265360f07b83f658431425a384a27c303feab9e
      
https://github.com/qemu/qemu/commit/d265360f07b83f658431425a384a27c303feab9e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0843563f3ef42db0ccaa1ac219439413f8083d34
      
https://github.com/qemu/qemu/commit/0843563f3ef42db0ccaa1ac219439413f8083d34
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement HADD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 10c9e58d5c317d8bc6a0a2b36e2f130bad6b8cea
      
https://github.com/qemu/qemu/commit/10c9e58d5c317d8bc6a0a2b36e2f130bad6b8cea
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement HSUB

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1b3cb7c874bd92d6022f4f99b16531f66148d905
      
https://github.com/qemu/qemu/commit/1b3cb7c874bd92d6022f4f99b16531f66148d905
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement HAVG

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 151f309b989fd84bec0cbd5bc84dbe83bbe0b2f4
      
https://github.com/qemu/qemu/commit/151f309b989fd84bec0cbd5bc84dbe83bbe0b2f4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement HSHL, HSHR

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3bbb8e4832b56cea29a61eb32cfb4931e00244c1
      
https://github.com/qemu/qemu/commit/3bbb8e4832b56cea29a61eb32cfb4931e00244c1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/op_helper.c
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement HSHLADD, HSHRADD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c2a7ee3f9d7605f494d738825beef1b792bfb357
      
https://github.com/qemu/qemu/commit/c2a7ee3f9d7605f494d738825beef1b792bfb357
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement MIXH, MIXW

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4e7abdb120d7456aaa754a7101ef43a5916ed8a0
      
https://github.com/qemu/qemu/commit/4e7abdb120d7456aaa754a7101ef43a5916ed8a0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/insns.decode
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement PERMH

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ab9af359c175378c6aa716de0f8e2acbcbcba376
      
https://github.com/qemu/qemu/commit/ab9af359c175378c6aa716de0f8e2acbcbcba376
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.h
    M target/hppa/int_helper.c

  Log Message:
  -----------
  target/hppa: Fix interruption based on default PSW

The default PSW is set by the operating system with the PDC_PSW
firmware call.  Use that setting to decide if wide mode is to be
enabled for interruptions and EIRR usage.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a4db4a7811e1be790012ab000707c40004f237e0
      
https://github.com/qemu/qemu/commit/a4db4a7811e1be790012ab000707c40004f237e0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Precompute zero into DisasContext

Reduce the number of times we look for the constant 0.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bc3da3cf6237dea2d91affe2116529d4c580c288
      
https://github.com/qemu/qemu/commit/bc3da3cf6237dea2d91affe2116529d4c580c288
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Return zero for r0 from load_gpr

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e1fee58fea3a8d215029269235d82cf6f79c1749
      
https://github.com/qemu/qemu/commit/e1fee58fea3a8d215029269235d82cf6f79c1749
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M include/hw/elf_ops.h

  Log Message:
  -----------
  include/hw/elf: Remove truncating signed casts

There's nothing about elf that specifically requires signed vs unsigned.
This is very much a target-specific preference.

In the meantime, casting low and high from uint64_t back to Elf_SWord
to uint64_t discards high bits that might have been set by translate_fn.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f386a16e45867c4476a5bbbc06cfa1ebf91297f8
      
https://github.com/qemu/qemu/commit/f386a16e45867c4476a5bbbc06cfa1ebf91297f8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  hw/hppa: Translate phys addresses for the cpu

Hack the machine to use pa2.0 physical layout when required,
using the PSW.W=0 absolute to physical mapping.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 54111124fb9097635ec784131ceec26798e2ba77
      
https://github.com/qemu/qemu/commit/54111124fb9097635ec784131ceec26798e2ba77
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M linux-user/hppa/cpu_loop.c

  Log Message:
  -----------
  linux-user/hppa: Drop EXCP_DUMP from handled exceptions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b5caa17cdaf153fca500cf8bb0fa3a14c02def6e
      
https://github.com/qemu/qemu/commit/b5caa17cdaf153fca500cf8bb0fa3a14c02def6e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Implement pa2.0 data prefetch instructions

These are aliased onto the normal integer loads to %g0.
Since we don't emulate caches, prefetch is a nop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eb25d10f4d601f29169c876f9463e37db674b132
      
https://github.com/qemu/qemu/commit/eb25d10f4d601f29169c876f9463e37db674b132
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/mem_helper.c
    M target/hppa/trace-events
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Add pa2.0 cpu local tlb flushes

The previous decoding misnamed the bit it called "local".
Other than the name, the implementation was correct for pa1.x.
Rename this field to "tlbe".

PA2.0 adds (a real) local bit to PxTLB, and also adds a range
of pages to flush in GR[b].

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 34a0d9eefe7dd6161c100e6ffaf25c6c6f4a7282
      
https://github.com/qemu/qemu/commit/34a0d9eefe7dd6161c100e6ffaf25c6c6f4a7282
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4c34bab0d3dc59fef4ebce831fbca784a1e3e06a
      
https://github.com/qemu/qemu/commit/4c34bab0d3dc59fef4ebce831fbca784a1e3e06a
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Clear upper bits in mtctl for pa1.x

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f5b5c85760c6d3cf073d8e0ee85d170c569d3ddf
      
https://github.com/qemu/qemu/commit/f5b5c85760c6d3cf073d8e0ee85d170c569d3ddf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Add unwind_breg to CPUHPPAState

Fill in the insn_start value during form_gva, and copy
it out to the env field in hppa_restore_state_to_opc.
The value is not yet consumed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8a02b9a68e4cded2b8751d803a3e3aedfce93609
      
https://github.com/qemu/qemu/commit/8a02b9a68e4cded2b8751d803a3e3aedfce93609
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/mem_helper.c

  Log Message:
  -----------
  target/hppa: Create raise_exception_with_ior

Handle pa2.0 logic for filling in ISR+IOR.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b10700d826c864872deae6c28aca041fc97df79f
      
https://github.com/qemu/qemu/commit/b10700d826c864872deae6c28aca041fc97df79f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/int_helper.c
    M target/hppa/sys_helper.c

  Log Message:
  -----------
  target/hppa: Update IIAOQ, IIASQ for pa2.0

These registers have a different format for pa2.0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5dd5c003661c364d5c339675532c3d5c60207994
      
https://github.com/qemu/qemu/commit/5dd5c003661c364d5c339675532c3d5c60207994
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M target/hppa/int_helper.c

  Log Message:
  -----------
  target/hppa: Improve interrupt logging

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fd842b2f4ce2da082b400f9b9278fa6bd45d0864
      
https://github.com/qemu/qemu/commit/fd842b2f4ce2da082b400f9b9278fa6bd45d0864
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/pci-host/astro.c

  Log Message:
  -----------
  hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region

Map Astro into high F-region and add alias for 32-bit OS in low region.

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: 64bf09674a5911fd70a3b4050c2d7081b0353cf5
      
https://github.com/qemu/qemu/commit/64bf09674a5911fd70a3b4050c2d7081b0353cf5
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/pci-host/astro.c

  Log Message:
  -----------
  hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory

The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND()
to trigger interrupt request at the right CPU HPA address.
Note that the cpu_hpa value comes out of the IRT, which doesn't store the
higher addresss bits.

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: fd9b04bf9299e8db36db3b677bc0a433fc3a34b3
      
https://github.com/qemu/qemu/commit/fd9b04bf9299e8db36db3b677bc0a433fc3a34b3
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  hw/hppa: Turn on 64-bit CPU for C3700 machine

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: 3d1611bfa129182d2e867e8a9da7d2fc6efefce5
      
https://github.com/qemu/qemu/commit/3d1611bfa129182d2e867e8a9da7d2fc6efefce5
  Author: Helge Deller <deller@gmx.de>
  Date:   2023-11-06 (Mon, 06 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c

  Log Message:
  -----------
  hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only

Prevent that users try to boot a 64-bit only C3700 machine with a 32-bit
CPU, and to boot a 32-bit only B160L machine with a 64-bit CPU.

Signed-off-by: Helge Deller <deller@gmx.de>


  Commit: bb541a7068d2eee51a9abbe2dedcdf27298b1872
      
https://github.com/qemu/qemu/commit/bb541a7068d2eee51a9abbe2dedcdf27298b1872
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-07 (Tue, 07 Nov 2023)

  Changed paths:
    M configs/targets/hppa-linux-user.mak
    M hw/hppa/machine.c
    M hw/pci-host/astro.c
    M include/hw/elf_ops.h
    M linux-user/hppa/cpu_loop.c
    M linux-user/hppa/signal.c
    M linux-user/hppa/target_elf.h
    M target/hppa/cpu-param.h
    M target/hppa/cpu-qom.h
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/gdbstub.c
    M target/hppa/helper.c
    M target/hppa/helper.h
    M target/hppa/insns.decode
    M target/hppa/int_helper.c
    M target/hppa/machine.c
    M target/hppa/mem_helper.c
    M target/hppa/op_helper.c
    M target/hppa/sys_helper.c
    M target/hppa/trace-events
    M target/hppa/translate.c

  Log Message:
  -----------
  Merge tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu into staging

target/hppa: Implement PA2.0 instructions
hw/hppa: Map astro chip 64-bit I/O mem
hw/hppa: Turn on 64-bit cpu for C3700

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# gpg: Signature made Tue 07 Nov 2023 11:00:01 HKT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu: (85 commits)
  hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only
  hw/hppa: Turn on 64-bit CPU for C3700 machine
  hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory
  hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region
  target/hppa: Improve interrupt logging
  target/hppa: Update IIAOQ, IIASQ for pa2.0
  target/hppa: Create raise_exception_with_ior
  target/hppa: Add unwind_breg to CPUHPPAState
  target/hppa: Clear upper bits in mtctl for pa1.x
  target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system
  target/hppa: Add pa2.0 cpu local tlb flushes
  target/hppa: Implement pa2.0 data prefetch instructions
  linux-user/hppa: Drop EXCP_DUMP from handled exceptions
  hw/hppa: Translate phys addresses for the cpu
  include/hw/elf: Remove truncating signed casts
  target/hppa: Return zero for r0 from load_gpr
  target/hppa: Precompute zero into DisasContext
  target/hppa: Fix interruption based on default PSW
  target/hppa: Implement PERMH
  target/hppa: Implement MIXH, MIXW
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/8aba939e77da...bb541a7068d2



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