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[Qemu-commits] [qemu/qemu] e867a1: target/arm: enable FEAT_RNG on Neover


From: Alex Bennée
Subject: [Qemu-commits] [qemu/qemu] e867a1: target/arm: enable FEAT_RNG on Neoverse-N2
Date: Tue, 21 Nov 2023 03:25:49 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: e867a1242ebab8b7dbab99da8187b7813407d395
      
https://github.com/qemu/qemu/commit/e867a1242ebab8b7dbab99da8187b7813407d395
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: enable FEAT_RNG on Neoverse-N2

I noticed that Neoverse-V1 has FEAT_RNG enabled so let enable it also on
Neoverse-N2.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231114103443.1652308-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 70726a15bc7e61d16f3efe5bfd9b061ca077f533
      
https://github.com/qemu/qemu/commit/70726a15bc7e61d16f3efe5bfd9b061ca077f533
  Author: Ben Dooks <ben.dooks@codethink.co.uk>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ

The ICC_PMR_ELx and ICV_PMR_ELx bit masks returned from
ic{c,v}_fullprio_mask should technically also remove any
bit above 7 as these are marked reserved (read 0) and should
therefore should not be written as anything other than 0.

This was noted during a run of a proprietary test system and
discused on the mailing list [1] and initially thought not to
be an issue due to RES0 being technically allowed to be
written to and read back as long as the implementation does
not use the RES0 bits. It is very possible that the values
are used in comparison without masking, as pointed out by
Peter in [2], if (cs->hppi.prio >= cs->icc_pmr_el1) may well
do the wrong thing.

Masking these values in ic{c,v}_fullprio_mask() should fix
this and prevent any future problems with playing with the
values.

[1]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00607.html
[2]: https://lists.nongnu.org/archive/html/qemu-arm/2023-11/msg00737.html

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Message-id: 20231116172818.792364-1-ben.dooks@codethink.co.uk
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3efd8495735c69b863476e9003e624877382a72d
      
https://github.com/qemu/qemu/commit/3efd8495735c69b863476e9003e624877382a72d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M target/arm/tcg/sme_helper.c

  Log Message:
  -----------
  target/arm: Fix SME FMOPA (16-bit), BFMOPA

Perform the loop increment unconditionally, not nested
within the predication.

Cc: qemu-stable@nongnu.org
Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1985
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231117193135.1180657-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 790a4428f2e2a32944f3cefc4753ab3c71611453
      
https://github.com/qemu/qemu/commit/790a4428f2e2a32944f3cefc4753ab3c71611453
  Author: Gavin Shan <gshan@redhat.com>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/hppa/machine.c
    M hw/m68k/q800.c
    M include/hw/boards.h

  Log Message:
  -----------
  hw/core/machine: Constify MachineClass::valid_cpu_types[]

Constify MachineClass::valid_cpu_types[i], as suggested by Richard
Henderson.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231117071704.35040-2-philmd@linaro.org
[PMD: Constify HPPA machines,
      restrict valid_cpu_types to machine_class_init() handlers]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e1b72c55b1f7f77a976f9af7a6ccd437ec804916
      
https://github.com/qemu/qemu/commit/e1b72c55b1f7f77a976f9af7a6ccd437ec804916
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/arm/netduinoplus2.c
    M hw/arm/olimex-stm32-h405.c
    M hw/arm/stm32f405_soc.c
    M include/hw/arm/stm32f405_soc.h

  Log Message:
  -----------
  hw/arm/stm32f405: Report error when incorrect CPU is used

Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the
CPU type requested by the command line. This might confuse users,
since the following will create a machine with a Cortex-M4 CPU:

  $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f

Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.

We now get:

  $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f
  qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu
  The valid types are: cortex-m4-arm-cpu

Since the SoC family can only use Cortex-M4 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ff6cda35f143082a2c24e9fe74ea0ce4bf3167c1
      
https://github.com/qemu/qemu/commit/ff6cda35f143082a2c24e9fe74ea0ce4bf3167c1
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/arm/netduino2.c
    M hw/arm/stm32f205_soc.c
    M include/hw/arm/stm32f205_soc.h

  Log Message:
  -----------
  hw/arm/stm32f205: Report error when incorrect CPU is used

The 'netduino2' machine ignores the CPU type requested by the
command line. This might confuse users, since the following will
create a machine with a Cortex-M3 CPU:

  $ qemu-system-arm -M netduino2 -cpu cortex-a9

Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.

We now get:

  $ qemu-system-arm -M netduino2 -cpu cortex-a9
  qemu-system-arm: Invalid CPU type: cortex-a9-arm-cpu
  The valid types are: cortex-m3-arm-cpu

Since the SoC family can only use Cortex-M3 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d652866007fc6fae718b0bcfdaf757231b378dd7
      
https://github.com/qemu/qemu/commit/d652866007fc6fae718b0bcfdaf757231b378dd7
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/arm/stm32f100_soc.c
    M hw/arm/stm32vldiscovery.c
    M include/hw/arm/stm32f100_soc.h

  Log Message:
  -----------
  hw/arm/stm32f100: Report error when incorrect CPU is used

The 'stm32vldiscovery' machine ignores the CPU type requested by
the command line. This might confuse users, since the following
will create a machine with a Cortex-M3 CPU:

  $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1

Set the MachineClass::valid_cpu_types field (introduced in commit
c9cf636d48 "machine: Add a valid_cpu_types property").
Remove the now unused MachineClass::default_cpu_type field.

We now get:

  $ qemu-system-aarch64 -M stm32vldiscovery -cpu neoverse-n1
  qemu-system-aarch64: Invalid CPU type: neoverse-n1-arm-cpu
  The valid types are: cortex-m3-arm-cpu

Since the SoC family can only use Cortex-M3 CPUs, hard-code the
CPU type name at the SoC level, removing the QOM property
entirely.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Message-id: 20231117071704.35040-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0cbb56c236a4a28f5149eed227d74bb737321cfc
      
https://github.com/qemu/qemu/commit/0cbb56c236a4a28f5149eed227d74bb737321cfc
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx6.c

  Log Message:
  -----------
  hw/arm/fsl-imx: Do not ignore Error argument

Both i.MX25 and i.MX6 SoC models ignore the Error argument when
setting the PHY number. Pick &error_abort which is the error
used by the i.MX7 SoC (see commit 1f7197deb0 "ability to change
the FEC PHY on i.MX7 processor").

Fixes: 74c1330582 ("ability to change the FEC PHY on i.MX25 processor")
Fixes: a9c167a3c4 ("ability to change the FEC PHY on i.MX6 processor")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231120115116.76858-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 85d57a37be1461d599747ab86dc0acc46732dbce
      
https://github.com/qemu/qemu/commit/85d57a37be1461d599747ab86dc0acc46732dbce
  Author: Song Gao <gaosong@loongson.cn>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Fix tcg_out_mov() Aborted

On LoongArch host,  we got an Aborted from tcg_out_mov().

qemu-x86_64 configure with '--enable-debug'.

> (gdb) b /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312
> Breakpoint 1 at 0x2576f0: file 
> /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc, line 312.
> (gdb) run hello
[...]
> Thread 1 "qemu-x86_64" hit Breakpoint 1, tcg_out_mov (s=0xaaaae91760 
> <tcg_init_ctx>, type=TCG_TYPE_V128, ret=TCG_REG_V2,
>     arg=TCG_REG_V0) at 
> /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312
> 312           g_assert_not_reached();
> (gdb) bt
> #0  tcg_out_mov (s=0xaaaae91760 <tcg_init_ctx>, type=TCG_TYPE_V128, 
> ret=TCG_REG_V2, arg=TCG_REG_V0)
>     at /home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312
> #1  0x000000aaaad0fee0 in tcg_reg_alloc_mov (s=0xaaaae91760 <tcg_init_ctx>, 
> op=0xaaaaf67c20) at ../tcg/tcg.c:4632
> #2  0x000000aaaad142f4 in tcg_gen_code (s=0xaaaae91760 <tcg_init_ctx>, 
> tb=0xffe8030340 <code_gen_buffer+197328>,
>     pc_start=4346094) at ../tcg/tcg.c:6135
[...]
> (gdb) c
> Continuing.
> **
> ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov:
>  code should not be reached
> Bail out! 
> ERROR:/home1/gaosong/code/qemu/tcg/loongarch64/tcg-target.c.inc:312:tcg_out_mov:
>  code should not be reached
>
> Thread 1 "qemu-x86_64" received signal SIGABRT, Aborted.
> 0x000000fff7b1c390 in raise () from /lib64/libc.so.6
> (gdb) q

Fixes: 16288ded94 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20231120065916.374045-1-gaosong@loongson.cn>


  Commit: 8bc5ae046d15fcd3e5de65225d5d3a8f1a5a6413
      
https://github.com/qemu/qemu/commit/8bc5ae046d15fcd3e5de65225d5d3a8f1a5a6413
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/ppc/pnv_i2c.c

  Log Message:
  -----------
  ppc/pnv: Fix potential overflow in I2C model

Coverity warns that "i2c_bus_busy(i2c->busses[i]) << i" might overflow
because the expression is evaluated using 32-bit arithmetic and then
used in a context expecting a uint64_t.

While we are at it, introduce a PNV_I2C_MAX_BUSSES constant and check
the number of busses at realize time.

Fixes: Coverity CID 1523918
Cc: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d18b0652869a39688d0fd2897bc035b309d1b6e8
      
https://github.com/qemu/qemu/commit/d18b0652869a39688d0fd2897bc035b309d1b6e8
  Author: John Platts <john_platts@hotmail.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M target/ppc/fpu_helper.c
    M tests/tcg/ppc64/Makefile.target
    A tests/tcg/ppc64/vsx_f2i_nan.c

  Log Message:
  -----------
  target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros

The patch below fixes a bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2
macros in target/ppc/fpu_helper.c where a non-NaN floating point value from the
source vector is incorrectly converted to 0, 0x80000000, or 0x8000000000000000
instead of the expected value if a preceding source floating point value from
the same source vector was a NaN.

The bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros in
target/ppc/fpu_helper.c was introduced with commit c3f24257e3c0.

This patch also adds a new vsx_f2i_nan test in tests/tcg/ppc64 that checks that
the VSX xvcvspsxws, xvcvspuxws, xvcvspsxds, xvcvspuxds, xvcvdpsxws, xvcvdpuxws,
xvcvdpsxds, and xvcvdpuxds instructions correctly convert non-NaN floating point
values to integer values if the source vector contains NaN floating point 
values.

Fixes: c3f24257e3c0 ("target/ppc: Clear fpstatus flags on helpers missing it")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1941
Signed-off-by: John Platts <john_platts@hotmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 47dfdd238dd0cc3c4834668fdd79ac5db85699f6
      
https://github.com/qemu/qemu/commit/47dfdd238dd0cc3c4834668fdd79ac5db85699f6
  Author: Glenn Miles <milesg@linux.vnet.ibm.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_i2c.c

  Log Message:
  -----------
  ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses

The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C engine's address range such
that engine 0 had engine 1's address and so on.  The xscom address
assignment was being based on the device tree engine numbering, which
starts at 1.  Rather than changing the device tree numbering to start
with 0, the addressing was changed to be based on the existing device
tree numbers minus one.

Fixes: 1ceda19c28a1 ("ppc/pnv: Connect PNV I2C controller to powernv10)
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: b664466d8f3c7b448fc7e9bd50d03a36538c6c27
      
https://github.com/qemu/qemu/commit/b664466d8f3c7b448fc7e9bd50d03a36538c6c27
  Author: Glenn Miles <milesg@linux.vnet.ibm.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/ppc/pnv_i2c.c

  Log Message:
  -----------
  ppc/pnv: Fix PNV I2C invalid status after reset

The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and the SCL/SDA input
level fields.

Fixed this for resets caused by a system reset as well
as from writing to the "Immediate Reset" register.

Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 7d0fefdf81f5973334c344f6b8e1896c309dff66
      
https://github.com/qemu/qemu/commit/7d0fefdf81f5973334c344f6b8e1896c309dff66
  Author: Akihiko Odaki <akihiko.odaki@daynix.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/net/allwinner-sun8i-emac.c
    M hw/net/allwinner_emac.c
    M hw/net/cadence_gem.c
    M hw/net/dp8393x.c
    M hw/net/e1000.c
    M hw/net/e1000e.c
    M hw/net/eepro100.c
    M hw/net/etraxfs_eth.c
    M hw/net/fsl_etsec/etsec.c
    M hw/net/ftgmac100.c
    M hw/net/i82596.c
    M hw/net/igb.c
    M hw/net/imx_fec.c
    M hw/net/lan9118.c
    M hw/net/mcf_fec.c
    M hw/net/mipsnet.c
    M hw/net/msf2-emac.c
    M hw/net/mv88w8618_eth.c
    M hw/net/ne2000-isa.c
    M hw/net/ne2000-pci.c
    M hw/net/npcm7xx_emc.c
    M hw/net/opencores_eth.c
    M hw/net/pcnet.c
    M hw/net/rocker/rocker_fp.c
    M hw/net/rtl8139.c
    M hw/net/smc91c111.c
    M hw/net/spapr_llan.c
    M hw/net/stellaris_enet.c
    M hw/net/sungem.c
    M hw/net/sunhme.c
    M hw/net/tulip.c
    M hw/net/virtio-net.c
    M hw/net/vmxnet3.c
    M hw/net/xen_nic.c
    M hw/net/xgmac.c
    M hw/net/xilinx_axienet.c
    M hw/net/xilinx_ethlite.c
    M hw/usb/dev-network.c
    M include/net/net.h
    M net/net.c

  Log Message:
  -----------
  net: Provide MemReentrancyGuard * to qemu_new_nic()

Recently MemReentrancyGuard was added to DeviceState to record that the
device is engaging in I/O. The network device backend needs to update it
when delivering a packet to a device.

In preparation for such a change, add MemReentrancyGuard * as a
parameter of qemu_new_nic().

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Jason Wang <jasowang@redhat.com>


  Commit: 9050f976e447444ea6ee2ba12c9f77e4b0dc54bc
      
https://github.com/qemu/qemu/commit/9050f976e447444ea6ee2ba12c9f77e4b0dc54bc
  Author: Akihiko Odaki <akihiko.odaki@daynix.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M include/net/net.h
    M net/net.c

  Log Message:
  -----------
  net: Update MemReentrancyGuard for NIC

Recently MemReentrancyGuard was added to DeviceState to record that the
device is engaging in I/O. The network device backend needs to update it
when delivering a packet to a device.

This implementation follows what bottom half does, but it does not add
a tracepoint for the case that the network device backend started
delivering a packet to a device which is already engaging in I/O. This
is because such reentrancy frequently happens for
qemu_flush_queued_packets() and is insignificant.

Fixes: CVE-2023-3019
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Jason Wang <jasowang@redhat.com>


  Commit: 84f85eb95f14add02efd5e69f2ff7783d79b24f7
      
https://github.com/qemu/qemu/commit/84f85eb95f14add02efd5e69f2ff7783d79b24f7
  Author: David Woodhouse <dwmw@amazon.co.uk>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M net/net.c

  Log Message:
  -----------
  net: do not delete nics in net_cleanup()

In net_cleanup() we only need to delete the netdevs, as those may have
state which outlives Qemu when it exits, and thus may actually need to
be cleaned up on exit.

The nics, on the other hand, are owned by the device which created them.
Most devices don't bother to clean up on exit because they don't have
any state which will outlive Qemu... but XenBus devices do need to clean
up their nodes in XenStore, and do have an exit handler to delete them.

When the XenBus exit handler destroys the xen-net-device, it attempts
to delete its nic after net_cleanup() had already done so. And crashes.

Fix this by only deleting netdevs as we walk the list. As the comment
notes, we can't use QTAILQ_FOREACH_SAFE() as each deletion may remove
*multiple* entries, including the "safely" saved 'next' pointer. But
we can store the *previous* entry, since nics are safe.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>


  Commit: 69562648f9c35382041d96dc267768cbcc008a41
      
https://github.com/qemu/qemu/commit/69562648f9c35382041d96dc267768cbcc008a41
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M system/vl.c

  Log Message:
  -----------
  vl: revert behaviour for -display none

Commit 1bec1cc0d ("ui/console: allow to override the default VC") changed
the behaviour of the "-display none" option, so that it now creates a
QEMU monitor on the terminal. "-display none" should not be tangled up
with whether we create a monitor or a serial terminal; it should purely
and only disable the graphical window. Changing its behaviour like this
breaks command lines which, for example, use semihosting for their
output and don't want a graphical window, as they now get a monitor they
never asked for.

It also breaks the command line we document for Xen in
docs/system/i386/xen.html:

 $ ./qemu-system-x86_64 --accel kvm,xen-version=0x40011,kernel-irqchip=split \
    -display none -chardev stdio,mux=on,id=char0,signal=off -mon char0 \
    -device xen-console,chardev=char0  -drive file=${GUEST_IMAGE},if=xen

qemu-system-x86_64: cannot use stdio by multiple character devices
qemu-system-x86_64: could not connect serial device to character backend
'stdio'

When qemu is compiled without PIXMAN, by default the serials aren't
muxed with the monitor anymore on stdio. The serials are redirected to
"null" instead, and the monitor isn't set up.

Fixes: commit 1bec1cc0d ("ui/console: allow to override the default VC")
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>


  Commit: b7f1bb38b011efd13784e8781dafeedcc6e900a1
      
https://github.com/qemu/qemu/commit/b7f1bb38b011efd13784e8781dafeedcc6e900a1
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M ui/dbus.c
    M ui/gtk.c
    M ui/spice-app.c

  Log Message:
  -----------
  ui: use "vc" chardev for dbus, gtk & spice-app

Those display have their own implementation of "vc" chardev, which
doesn't use pixman. They also don't implement the width/height/cols/rows
options, so qemu_display_get_vc() should return a compatible argument.

This patch was meant to be with the pixman series, when the "vc" field
was introduced. It fixes a regression where VC are created on the
tty (or null) instead of the display own "vc" implementation.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>


  Commit: 0e8823072e1d6c5320864f734d01f11210109320
      
https://github.com/qemu/qemu/commit/0e8823072e1d6c5320864f734d01f11210109320
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M ui/console.c

  Log Message:
  -----------
  ui/console: fix default VC when there are no display

When display is "none", we may still have remote displays (I think it
would be simpler if VNC/Spice were regular display btw). Return the
default VC then, and set them up to fix a regression when using remote
display and it used the TTY instead.

Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1989
Fixes: commit 1bec1cc0d ("ui/console: allow to override the default VC")
Reported-by: German Maglione <gmaglione@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>


  Commit: ff2a5bed5f28cc59b25de76cb90196329da6c1f4
      
https://github.com/qemu/qemu/commit/ff2a5bed5f28cc59b25de76cb90196329da6c1f4
  Author: Marc-André Lureau <marcandre.lureau@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M system/vl.c

  Log Message:
  -----------
  vl: add missing display_remote++

We should also consider -display vnc= as setting up a remote display,
and not attempt to add another default one.

The display_remote++ in qemu_setup_display() isn't necessary at this
point, but is there for completeness and further usages of the variable.

Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1988
Fixes: commit 484629fc81 ("vl: simplify display_remote logic ")
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>


  Commit: e0c58720bfd8c0553f170b64717278b07438d2f5
      
https://github.com/qemu/qemu/commit/e0c58720bfd8c0553f170b64717278b07438d2f5
  Author: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M include/ui/pixman-minimal.h

  Log Message:
  -----------
  ui/pixman-minimal.h: fix empty allocation

In the minimal pixman API stub that is used when the real pixman
dependency is missing a NULL dereference happens when
virtio-gpu-rutabaga allocates a pixman image with bits = NULL and
rowstride_bytes = zero. A buffer of rowstride_bytes * height is
allocated which is NULL. However, in that scenario pixman calculates a
new stride value based on given width, height and format size.

This commit adds a helper function that performs the same logic as
pixman.

Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20231121093840.2121195-1-manos.pitsidianakis@linaro.org>


  Commit: 06080478f7ceb71014d15fb6f2b0de8226e5f015
      
https://github.com/qemu/qemu/commit/06080478f7ceb71014d15fb6f2b0de8226e5f015
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  Merge tag 'pull-loongarch-20231121' of https://gitlab.com/gaosong/qemu into 
staging

fixes tcg_out_mov aborted.

# -----BEGIN PGP SIGNATURE-----
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# McGzDIH/IbF0qG1HBako00jiwgGpx90aBU0KwOVgBjyjvUK2VXE268UoRs+WYVG/
# 7ljOHEnpvwJVTquAtDNFZIw0EFwiF75MP2rKvrSG8KmmrSu4hg==
# =oHNA
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 20 Nov 2023 21:34:14 EST
# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C  6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20231121' of https://gitlab.com/gaosong/qemu:
  tcg/loongarch64: Fix tcg_out_mov() Aborted

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: adf798b3795edb2cc333579309937cc7bd889593
      
https://github.com/qemu/qemu/commit/adf798b3795edb2cc333579309937cc7bd889593
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_i2c.c
    M target/ppc/fpu_helper.c
    M tests/tcg/ppc64/Makefile.target
    A tests/tcg/ppc64/vsx_f2i_nan.c

  Log Message:
  -----------
  Merge tag 'pull-ppc-20231121' of https://github.com/legoater/qemu into staging

ppc queue:

* PNV I2C fixes
* VSX instruction fix when converting floating point to integer values

# -----BEGIN PGP SIGNATURE-----
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# GUyVwScLWlspCJRpX/y4ubyfGB3ZqAQ9REita4YIMveDvNU83LS344MRrBpzQ+ZI
# 1yCoHdBsNUkpr9dN/uwkjDSBlDoyWJ2TAgQHsprNUD04ChML7Fs=
# =qx4p
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Nov 2023 03:16:31 EST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown]
# gpg:                 aka "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20231121' of https://github.com/legoater/qemu:
  ppc/pnv: Fix PNV I2C invalid status after reset
  ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses
  target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros
  ppc/pnv: Fix potential overflow in I2C model

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 19c63383a72408c9e0400db31bb4a96a913db78d
      
https://github.com/qemu/qemu/commit/19c63383a72408c9e0400db31bb4a96a913db78d
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/net/allwinner-sun8i-emac.c
    M hw/net/allwinner_emac.c
    M hw/net/cadence_gem.c
    M hw/net/dp8393x.c
    M hw/net/e1000.c
    M hw/net/e1000e.c
    M hw/net/eepro100.c
    M hw/net/etraxfs_eth.c
    M hw/net/fsl_etsec/etsec.c
    M hw/net/ftgmac100.c
    M hw/net/i82596.c
    M hw/net/igb.c
    M hw/net/imx_fec.c
    M hw/net/lan9118.c
    M hw/net/mcf_fec.c
    M hw/net/mipsnet.c
    M hw/net/msf2-emac.c
    M hw/net/mv88w8618_eth.c
    M hw/net/ne2000-isa.c
    M hw/net/ne2000-pci.c
    M hw/net/npcm7xx_emc.c
    M hw/net/opencores_eth.c
    M hw/net/pcnet.c
    M hw/net/rocker/rocker_fp.c
    M hw/net/rtl8139.c
    M hw/net/smc91c111.c
    M hw/net/spapr_llan.c
    M hw/net/stellaris_enet.c
    M hw/net/sungem.c
    M hw/net/sunhme.c
    M hw/net/tulip.c
    M hw/net/virtio-net.c
    M hw/net/vmxnet3.c
    M hw/net/xen_nic.c
    M hw/net/xgmac.c
    M hw/net/xilinx_axienet.c
    M hw/net/xilinx_ethlite.c
    M hw/usb/dev-network.c
    M include/net/net.h
    M net/net.c

  Log Message:
  -----------
  Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging

# -----BEGIN PGP SIGNATURE-----
# Version: GnuPG v1
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# iQEcBAABAgAGBQJlXF+GAAoJEO8Ells5jWIROT0H/RGk64ds4eiKskWxwG9p8K8s
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# gpg: Signature made Tue 21 Nov 2023 02:43:02 EST
# gpg:                using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) 
<jasowang@redhat.com>" [full]
# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* tag 'net-pull-request' of https://github.com/jasowang/qemu:
  net: do not delete nics in net_cleanup()
  net: Update MemReentrancyGuard for NIC
  net: Provide MemReentrancyGuard * to qemu_new_nic()

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: 85f10512488a1f9f2cc68ce8ef5078e966e1bb70
      
https://github.com/qemu/qemu/commit/85f10512488a1f9f2cc68ce8ef5078e966e1bb70
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx6.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/olimex-stm32-h405.c
    M hw/arm/stm32f100_soc.c
    M hw/arm/stm32f205_soc.c
    M hw/arm/stm32f405_soc.c
    M hw/arm/stm32vldiscovery.c
    M hw/hppa/machine.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/m68k/q800.c
    M include/hw/arm/stm32f100_soc.h
    M include/hw/arm/stm32f205_soc.h
    M include/hw/arm/stm32f405_soc.h
    M include/hw/boards.h
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/sme_helper.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20231121' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * enable FEAT_RNG on Neoverse-N2
 * hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
 * Fix SME FMOPA (16-bit), BFMOPA
 * hw/core/machine: Constify MachineClass::valid_cpu_types[]
 * stm32f* machines: Report error when user asks for wrong CPU type
 * hw/arm/fsl-imx: Do not ignore Error argument

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Nov 2023 05:21:42 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231121' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  hw/arm/fsl-imx: Do not ignore Error argument
  hw/arm/stm32f100: Report error when incorrect CPU is used
  hw/arm/stm32f205: Report error when incorrect CPU is used
  hw/arm/stm32f405: Report error when incorrect CPU is used
  hw/core/machine: Constify MachineClass::valid_cpu_types[]
  target/arm: Fix SME FMOPA (16-bit), BFMOPA
  hw/intc/arm_gicv3: ICC_PMR_EL1 high bits should be RAZ
  target/arm: enable FEAT_RNG on Neoverse-N2

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


  Commit: c14ae763d548842c6abd1afaf5dc7ce7322ed901
      
https://github.com/qemu/qemu/commit/c14ae763d548842c6abd1afaf5dc7ce7322ed901
  Author: Stefan Hajnoczi <stefanha@redhat.com>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M include/ui/pixman-minimal.h
    M system/vl.c
    M ui/console.c
    M ui/dbus.c
    M ui/gtk.c
    M ui/spice-app.c

  Log Message:
  -----------
  Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into 
staging

UI: fixes for 8.2-rc1

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# gpg: Signature made Tue 21 Nov 2023 05:39:40 EST
# gpg:                using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg:                issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" 
[full]
# gpg:                 aka "Marc-André Lureau <marcandre.lureau@gmail.com>" 
[full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276  F62D DAE8 E109 7596 9CE5

* tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
  ui/pixman-minimal.h: fix empty allocation
  vl: add missing display_remote++
  ui/console: fix default VC when there are no display
  ui: use "vc" chardev for dbus, gtk & spice-app
  vl: revert behaviour for -display none

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>


Compare: https://github.com/qemu/qemu/compare/af9264da8007...c14ae763d548



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