qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] cd0403: util/fifo8: Allow fifo8_pop_buf() to


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] cd0403: util/fifo8: Allow fifo8_pop_buf() to not populate ...
Date: Wed, 10 Jan 2024 03:42:30 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: cd04033dbeb0bbdd613780ff4b412fc3d3c768d6
      
https://github.com/qemu/qemu/commit/cd04033dbeb0bbdd613780ff4b412fc3d3c768d6
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M include/qemu/fifo8.h
    M util/fifo8.c

  Log Message:
  -----------
  util/fifo8: Allow fifo8_pop_buf() to not populate popped length

There might be cases where we know the number of bytes we can
pop from the FIFO, or we simply don't care how many bytes is
returned. Allow fifo8_pop_buf() to take a NULL numptr.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231109192814.95977-2-philmd@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 995d8348eb3d8ddf24882ed384a5c50eaf3aeae9
      
https://github.com/qemu/qemu/commit/995d8348eb3d8ddf24882ed384a5c50eaf3aeae9
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M include/qemu/fifo8.h
    M util/fifo8.c

  Log Message:
  -----------
  util/fifo8: Introduce fifo8_peek_buf()

To be able to peek at FIFO content without popping it,
introduce the fifo8_peek_buf() method by factoring
common content from fifo8_pop_buf().

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231109192814.95977-3-philmd@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 4eff52cd463e5d130a73bd16d81787c36acc0ec7
      
https://github.com/qemu/qemu/commit/4eff52cd463e5d130a73bd16d81787c36acc0ec7
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: Add vill check for whole vector register move instructions

The ratified version of RISC-V V spec section 16.6 says that
`The instructions operate as if EEW=SEW`.

So the whole vector register move instructions depend on the vtype
register that means the whole vector register move instructions should
raise an illegal-instruction exception when vtype.vill=1.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231129170400.21251-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 79fc6d38a819cd30e578023a231385f63583eafb
      
https://github.com/qemu/qemu/commit/79fc6d38a819cd30e578023a231385f63583eafb
  Author: Max Chou <max.chou@sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc

  Log Message:
  -----------
  target/riscv: The whole vector register move instructions depend on vsew

The RISC-V v spec 16.6 section says that the whole vector register move
instructions operate as if EEW=SEW. So it should depends on the vsew
field of vtype register.

Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231129170400.21251-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 564a28bda1b06eb54dc555c0e34403c6f5657a00
      
https://github.com/qemu/qemu/commit/564a28bda1b06eb54dc555c0e34403c6f5657a00
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/insn_trans/trans_xthead.c.inc

  Log Message:
  -----------
  target/riscv: Fix th.dcache.cval1 priviledge check

According to the specification, the th.dcache.cvall1 can be executed
under all priviledges.
The specification about xtheadcmo located in,
https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadcmo/dcache_cval1.adoc

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Christoph Muellner <christoph.muellner@vrull.eu>
Message-ID: <20231208094315.177-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7767f8b122dc061f9a68802b41b82117e755b03a
      
https://github.com/qemu/qemu/commit/7767f8b122dc061f9a68802b41b82117e755b03a
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Not allow write mstatus_vs without RVV

If CPU does not implement the Vector extension, it usually means
mstatus vs hardwire to zero. So we should not allow write a
non-zero value to this field.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231215023313.1708-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6f5bb7d40591386059077060508226b737080d95
      
https://github.com/qemu/qemu/commit/6f5bb7d40591386059077060508226b737080d95
  Author: Ivan Klokov <ivan.klokov@syntacore.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  target/riscv/pmp: Use hwaddr instead of target_ulong for RV32

The Sv32 page-based virtual-memory scheme described in RISCV privileged
spec Section 5.3 supports 34-bit physical addresses for RV32, so the
PMP scheme must support addresses wider than XLEN for RV32. However,
PMP address register format is still 32 bit wide.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231123091214.20312-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8d326cb88b03b593708262947e9ec30411fb99ab
      
https://github.com/qemu/qemu/commit/8d326cb88b03b593708262947e9ec30411fb99ab
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv/cpu.c: fix machine IDs getters

mvendorid is an uint32 property, mimpid/marchid are uint64 properties.
But their getters are returning bools. The reason this went under the
radar for this long is because we have no code using the getters.

The problem can be seem via the 'qom-get' API though. Launching QEMU
with the 'veyron-v1' CPU, a model with:

VEYRON_V1_MVENDORID: 0x61f (1567)
VEYRON_V1_MIMPID: 0x111 (273)
VEYRON_V1_MARCHID: 0x8000000000010000 (9223372036854841344)

This is what the API returns when retrieving these properties:

(qemu) qom-get /machine/soc0/harts[0] mvendorid
true
(qemu) qom-get /machine/soc0/harts[0] mimpid
true
(qemu) qom-get /machine/soc0/harts[0] marchid
true

After this patch:

(qemu) qom-get /machine/soc0/harts[0] mvendorid
1567
(qemu) qom-get /machine/soc0/harts[0] mimpid
273
(qemu) qom-get /machine/soc0/harts[0] marchid
9223372036854841344

Fixes: 1e34150045 ("target/riscv/cpu.c: restrict 'mvendorid' value")
Fixes: a1863ad368 ("target/riscv/cpu.c: restrict 'mimpid' value")
Fixes: d6a427e2c0 ("target/riscv/cpu.c: restrict 'marchid' value")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231211170732.2541368-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 49c211ffca00fdf7c0c29072c224e88527a14838
      
https://github.com/qemu/qemu/commit/49c211ffca00fdf7c0c29072c224e88527a14838
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32

KVM_REG_RISCV_FP_F regs have u32 size according to the API, but by using
kvm_riscv_reg_id() in RISCV_FP_F_REG() we're returning u64 sizes when
running with TARGET_RISCV64. The most likely reason why no one noticed
this is because we're not implementing kvm_cpu_synchronize_state() in
RISC-V yet.

Create a new helper that returns a KVM ID with u32 size and use it in
RISCV_FP_F_REG().

Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 450bd6618fda3d2e2ab02b2fce1c79efd5b66084
      
https://github.com/qemu/qemu/commit/450bd6618fda3d2e2ab02b2fce1c79efd5b66084
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64

KVM_REG_RISCV_FP_D regs are always u64 size. Using kvm_riscv_reg_id() in
RISCV_FP_D_REG() ends up encoding the wrong size if we're running with
TARGET_RISCV32.

Create a new helper that returns a KVM ID with u64 size and use it with
RISCV_FP_D_REG().

Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 10f86d1b845087d14b58d65dd2a6e3411d1b6529
      
https://github.com/qemu/qemu/commit/10f86d1b845087d14b58d65dd2a6e3411d1b6529
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: change timer regs size to u64

KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at
this moment we'll return u32 regs if we're running a RISCV32 target.

Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it.

Reported-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f25974f46af7f936d08ed0bae5b80b1c90b78b25
      
https://github.com/qemu/qemu/commit/f25974f46af7f936d08ed0bae5b80b1c90b78b25
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: add RISCV_CONFIG_REG()

Create a RISCV_CONFIG_REG() macro, similar to what other regs use, to
hide away some of the boilerplate.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: da14fc74d5965c4c22ed637775959b4d21dca813
      
https://github.com/qemu/qemu/commit/da14fc74d5965c4c22ed637775959b4d21dca813
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()

kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32
size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64.

Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll
be in line with the existing kvm_riscv_reg_id_<size>() helpers.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231208183835.2411523-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4c7f4f4f0516ad1bad45b011235202f5be6899de
      
https://github.com/qemu/qemu/commit/4c7f4f4f0516ad1bad45b011235202f5be6899de
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    A hw/nvram/fw_cfg-acpi.c
    M hw/nvram/meson.build
    M hw/riscv/virt-acpi-build.c
    A include/hw/nvram/fw_cfg_acpi.h

  Log Message:
  -----------
  hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location

RISC-V also needs to use the same code to create fw_cfg in DSDT. So,
avoid code duplication by moving the code in arm and riscv to a device
specific file.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-2-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 57ba8436282940b59d9a069cc01a601bbc8036c5
      
https://github.com/qemu/qemu/commit/57ba8436282940b59d9a069cc01a601bbc8036c5
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M hw/virtio/meson.build
    A hw/virtio/virtio-acpi.c
    A include/hw/virtio/virtio-acpi.h

  Log Message:
  -----------
  hw/arm/virt-acpi-build.c: Migrate virtio creation to common location

RISC-V also needs to create the virtio in DSDT in the same way as ARM.
So, instead of duplicating the code, move this function to the device
specific file which is common across architectures.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-3-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8199bf48ea1fdb8e491311a0dc28cea30af18c95
      
https://github.com/qemu/qemu/commit/8199bf48ea1fdb8e491311a0dc28cea30af18c95
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/i386/acpi-microvm.c

  Log Message:
  -----------
  hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT

With common function to add virtio in DSDT created now, update microvm
code also to use it instead of duplicate code.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 68c8b403c78b8f20acbebba3cdc46320853fe5ca
      
https://github.com/qemu/qemu/commit/68c8b403c78b8f20acbebba3cdc46320853fe5ca
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Make few IMSIC macros and functions public

Some macros and static function related to IMSIC are defined in virt.c.
They are required in virt-acpi-build.c. So, make them public.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-5-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0efb12b713338e2be713b689d1c9743f7163f85d
      
https://github.com/qemu/qemu/commit/0efb12b713338e2be713b689d1c9743f7163f85d
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add AIA support in RINTC

Update the RINTC structure in MADT with AIA related fields.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-6-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 66ac45b75975a64aa3fbcaa038aecfbc11ac8547
      
https://github.com/qemu/qemu/commit/66ac45b75975a64aa3fbcaa038aecfbc11ac8547
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT

Add IMSIC structure in MADT when IMSIC is configured.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-7-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7d189186f68b2b249c0bd6c84984f3aad2bcd1ca
      
https://github.com/qemu/qemu/commit/7d189186f68b2b249c0bd6c84984f3aad2bcd1ca
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add APLIC in the MADT

Add APLIC structures for each socket in the MADT when system is configured
with APLIC as the external wired interrupt controller.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-8-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e810a5177c44509e17293d4c7e6cffab8ce197c9
      
https://github.com/qemu/qemu/commit/e810a5177c44509e17293d4c7e6cffab8ce197c9
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add CMO information in RHCT

When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
block size for those extensions need to be communicated via CMO node in
RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-9-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a52aea263e0f25993e368ee682d96f32aff52499
      
https://github.com/qemu/qemu/commit/a52aea263e0f25993e368ee682d96f32aff52499
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add MMU node in RHCT

MMU type information is available via MMU node in RHCT. Add this node in
RHCT.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-10-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8f6a4874887c226b0df35f5b78fa77f197507d96
      
https://github.com/qemu/qemu/commit/8f6a4874887c226b0df35f5b78fa77f197507d96
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/pci-host/gpex-acpi.c
    M hw/pci-host/gpex.c
    M include/hw/pci-host/gpex.h

  Log Message:
  -----------
  hw/pci-host/gpex: Define properties for MMIO ranges

ACPI DSDT generator needs information like ECAM range, PIO range, 32-bit
and 64-bit PCI MMIO range etc related to the PCI host bridge. Instead of
making these values machine specific, create properties for the GPEX
host bridge with default value 0. During initialization, the firmware
can initialize these properties with correct values for the platform.
This basically allows DSDT generator code independent of the machine
specific memory map accesses.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231218150247.466427-11-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e86e95270e2b10e57c69852778452b54b31e1c19
      
https://github.com/qemu/qemu/commit/e86e95270e2b10e57c69852778452b54b31e1c19
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv/virt: Update GPEX MMIO related properties

Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 55ecd83b3697d0e4002c1dfde3265ebe6fa887cc
      
https://github.com/qemu/qemu/commit/55ecd83b3697d0e4002c1dfde3265ebe6fa887cc
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add IO controllers and devices

Add basic IO controllers and devices like PCI, VirtIO and UART in the
ACPI namespace.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-13-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d641da6ed431f497b763a6e6bf30e0b4dc00e0d9
      
https://github.com/qemu/qemu/commit/d641da6ed431f497b763a6e6bf30e0b4dc00e0d9
  Author: Sunil V L <sunilvl@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt-acpi-build.c

  Log Message:
  -----------
  hw/riscv/virt-acpi-build.c: Add PLIC in MADT

Add PLIC structures for each socket in the MADT when system is
configured with PLIC as the external interrupt controller.

Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-14-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ca334e10dcd1f0f3a3c08f8dc3f9945d574d0e6b
      
https://github.com/qemu/qemu/commit/ca334e10dcd1f0f3a3c08f8dc3f9945d574d0e6b
  Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: fix the interrupts-extended property format of PLIC

The interrupts-extended property of PLIC only has 2 * hart number
fields when KVM enabled, copy 4 * hart number fields to fdt will
expose some uninitialized value.

In this patch, I also refactor the code about the setting of
interrupts-extended property of PLIC for improved readability.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231218090543.22353-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b52d49e97fc458f90c2e2f8ee79a20208d68682f
      
https://github.com/qemu/qemu/commit/b52d49e97fc458f90c2e2f8ee79a20208d68682f
  Author: Weiwei Li <liweiwei@iscas.ac.cn>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h
    M target/riscv/insn32.decode
    A target/riscv/insn_trans/trans_rvzacas.c.inc
    M target/riscv/tcg/tcg-cpu.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add support for Zacas extension

Add support for amocas.w/d/q instructions which are part of the ratified
Zacas extension: https://github.com/riscv/riscv-zacas

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231207153842.32401-2-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6c848c192e5c1b0dfb952f0ba4c361baa2750753
      
https://github.com/qemu/qemu/commit/6c848c192e5c1b0dfb952f0ba4c361baa2750753
  Author: Rob Bradford <rbradford@rivosinc.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  disas/riscv: Add amocas.[w,d,q] instructions

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231207153842.32401-3-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 60db7a03c4de5452c87893c01ff834ae883d34b1
      
https://github.com/qemu/qemu/commit/60db7a03c4de5452c87893c01ff834ae883d34b1
  Author: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M docs/system/riscv/virt.rst

  Log Message:
  -----------
  docs/system/riscv: document acpi parameter of virt machine

Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI
table generation. Add it to the documentation.

Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231220193436.25909-1-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ee557ad53125a0b35906d828d04de9bbd6e11cf8
      
https://github.com/qemu/qemu/commit/ee557ad53125a0b35906d828d04de9bbd6e11cf8
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu-qom.h
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: create TYPE_RISCV_VENDOR_CPU

We want to add a new CPU type for bare CPUs that will inherit specific
traits of the 2 existing types:

- it will allow for extensions to be enabled/disabled, like generic
  CPUs;

- it will NOT inherit defaults, like vendor CPUs.

We can make this conditions met by adding an explicit type for the
existing vendor CPUs and change the existing logic to not imply that
"not generic" means vendor CPUs.

Let's add the "vendor" CPU type first.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7fc37962192edfc64aea22130afc2ca8dd15928e
      
https://github.com/qemu/qemu/commit/7fc37962192edfc64aea22130afc2ca8dd15928e
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: do not use "!generic" CPU checks

Our current logic in get/setters of MISA and multi-letter extensions
works because we have only 2 CPU types, generic and vendor, and by using
"!generic" we're implying that we're talking about vendor CPUs. When adding
a third CPU type this logic will break so let's handle it beforehand.

In set_misa_ext_cfg() and set_multi_ext_cfg(), check for "vendor" cpu instead
of "not generic". The "generic CPU" checks remaining are from
riscv_cpu_add_misa_properties() and cpu_add_multi_ext_prop() before
applying default values for the extensions.

This leaves us with:

- vendor CPUs will not allow extension enablement, all other CPUs will;

- generic CPUs will inherit default values for extensions, all others
  won't.

And now we can add a new, third CPU type, that will allow extensions to
be enabled and will not inherit defaults, without changing the existing
logic.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fdcefa91a11073eded85cb73cd7715f072d00f98
      
https://github.com/qemu/qemu/commit/fdcefa91a11073eded85cb73cd7715f072d00f98
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: update priv_ver on user_set extensions

We'll add a new bare CPU type that won't have any default priv_ver. This
means that the CPU will default to priv_ver = 0, i.e. 1.10.0.

At the same we'll allow these CPUs to enable extensions at will, but
then, if the extension has a priv_ver newer than 1.10, we'll end up
disabling it. Users will then need to manually set priv_ver to something
other than 1.10 to enable the extensions they want, which is not ideal.

Change the setter() of extensions to allow user enabled extensions to
bump the priv_ver of the CPU. This will make it convenient for users to
enable extensions for CPUs that doesn't set a default priv_ver.

This change does not affect any existing CPU: vendor CPUs does not allow
extensions to be enabled, and generic CPUs are already set to priv_ver
LATEST.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d379c748a30dce4bc6114111a5d6c0acec9c05a7
      
https://github.com/qemu/qemu/commit/d379c748a30dce4bc6114111a5d6c0acec9c05a7
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu-qom.h
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: add rv64i CPU

We don't have any form of a 'bare bones' CPU. rv64, our default CPUs,
comes with a lot of defaults. This is fine for most regular uses but
it's not suitable when more control of what is actually loaded in the
CPU is required.

A bare-bones CPU would be annoying to deal with if not by profile
support, a way to load a multitude of extensions with a single flag.
Profile support is going to be implemented shortly, so let's add a CPU
for it.

The new 'rv64i' CPU will have only RVI loaded. It is inspired in the
profile specification that dictates, for RVA22U64 [1]:

"RVA22U64 Mandatory Base
 RV64I is the mandatory base ISA for RVA22U64"

And so it seems that RV64I is the mandatory base ISA for all profiles
listed in [1], making it an ideal CPU to use with profile support.

rv64i is a CPU of type TYPE_RISCV_BARE_CPU. It has a mix of features
from pre-existent CPUs:

- it allows extensions to be enabled, like generic CPUs;
- it will not inherit extension defaults, like vendor CPUs.

This is the minimum extension set to boot OpenSBI and buildroot using
rv64i:

./build/qemu-system-riscv64 -nographic -M virt \
    -cpu rv64i,sv39=true,g=true,c=true,s=true,u=true

Our minimal riscv,isa in this case will be:

 # cat /proc/device-tree/cpus/cpu@0/riscv,isa
rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd#

[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cc2bf69a36e05e22a1dca9bf6305ef5e0cad993e
      
https://github.com/qemu/qemu/commit/cc2bf69a36e05e22a1dca9bf6305ef5e0cad993e
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M hw/riscv/virt.c
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h

  Log Message:
  -----------
  target/riscv: add zicbop extension flag

QEMU already implements zicbom (Cache Block Management Operations) and
zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv:
add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for
what would be the instructions for zicbop (Cache Block Prefetch
Operations), which are now no-ops.

The RVA22U64 profile mandates zicbop, which means that applications that
run with this profile might expect zicbop to be present in the riscv,isa
DT and might behave badly if it's absent.

Adding zicbop as an extension will make our future RVA22U64
implementation more in line with what userspace expects and, if/when
cache block prefetch operations became relevant to QEMU, we already have
the extension flag to turn then on/off as needed.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5fe2800b85fc44ffce749fb03c0ace085bd8a7b8
      
https://github.com/qemu/qemu/commit/5fe2800b85fc44ffce749fb03c0ace085bd8a7b8
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_cfg.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: add 'zic64b' support

zic64b is defined in the RVA22U64 profile [1] as a named feature for
"Cache blocks must be 64 bytes in size, naturally aligned in the address
space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64
profile mandates this feature, meaning that applications using this
profile expects 64 bytes cache blocks.

To make the upcoming RVA22U64 implementation complete, we'll zic64b as
a 'named feature', not a regular extension. This means that:

- it won't be exposed to users;
- it won't be written in riscv,isa.

This will be extended to other named extensions in the future, so we're
creating some common boilerplate for them as well.

zic64b is default to 'true' since we're already using 64 bytes blocks.
If any cache block size (cbo{m,p,z}_blocksize) is changed to something
different than 64, zic64b is set to 'false'.

Our profile implementation will then be able to check the current state
of zic64b and take the appropriate action (e.g. throw a warning).

[1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a88154835ac23e1098b3dabc1142253f034c36a6
      
https://github.com/qemu/qemu/commit/a88154835ac23e1098b3dabc1142253f034c36a6
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/riscv-qmp-cmds.c

  Log Message:
  -----------
  riscv-qmp-cmds.c: expose named features in cpu_model_expansion

Named features (zic64b the sole example at this moment) aren't expose to
users, thus we need another way to expose them.

Go through each named feature, get its boolean value, do the needed
conversions (bool to qbool, qbool to QObject) and add it to output dict.

Another adjustment is needed: named features are evaluated during
finalize(), so riscv_cpu_finalize_features() needs to be mandatory
regardless of whether we have an input dict or not. Otherwise zic64b
will always return 'false', which is incorrect: the default values of
cache blocksizes ([cbom/cbop/cboz]_blocksize) are set to 64, satisfying
the conditions for zic64b.

Here's an API usage example after this patch:

 $ ./build/qemu-system-riscv64 -S -M virt -display none
    -qmp tcp:localhost:1234,server,wait=off

 $ ./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50

(QEMU) query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model":
    {"name": "rv64", "props": {... "zic64b": true, ...}}}}

zic64b is set to 'true', as expected, since all cache sizes are 64
bytes by default.

If we change one of the cache blocksizes, zic64b is returned as 'false':

(QEMU) query-cpu-model-expansion type=full 
model={"name":"rv64","props":{"cbom_blocksize":128}}
{"return": {"model":
    {"name": "rv64", "props": {... "zic64b": false, ...}}}}

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3f3618474a3ecd4799be58cafc34eb36f95657a2
      
https://github.com/qemu/qemu/commit/3f3618474a3ecd4799be58cafc34eb36f95657a2
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: add rva22u64 profile definition

The rva22U64 profile, described in:

https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles

Contains a set of CPU extensions aimed for 64-bit userspace
applications. Enabling this set to be enabled via a single user flag
makes it convenient to enable a predictable set of features for the CPU,
giving users more predicability when running/testing their workloads.

QEMU implements all possible extensions of this profile. All the so
called 'synthetic extensions' described in the profile that are cache
related are ignored/assumed enabled (Za64rs, Zic64b, Ziccif, Ziccrse,
Ziccamoa, Zicclsm) since we do not implement a cache model.

An abstraction called RISCVCPUProfile is created to store the profile.
'ext_offsets' contains mandatory extensions that QEMU supports. Same
thing with the 'misa_ext' mask. Optional extensions must be enabled
manually in the command line if desired.

The design here is to use the common target/riscv/cpu.c file to store
the profile declaration and export it to the accelerator files. Each
accelerator is then responsible to expose it (or not) to users and how
to enable the extensions.

Next patches will implement the profile for TCG and KVM.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1a567c5cff36ae3a864fa534bf76711398eba4f1
      
https://github.com/qemu/qemu/commit/1a567c5cff36ae3a864fa534bf76711398eba4f1
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: add 'rva22u64' flag as unavailable

KVM does not have the means to support enabling the rva22u64 profile.
The main reasons are:

- we're missing support for some mandatory rva22u64 extensions in the
  KVM module;

- we can't make promises about enabling a profile since it all depends
  on host support in the end.

We'll revisit this decision in the future if needed. For now mark the
'rva22u64' profile as unavailable when running a KVM CPU:

$ qemu-system-riscv64 -machine virt,accel=kvm -cpu rv64,rva22u64=true
qemu-system-riscv64: can't apply global rv64-riscv-cpu.rva22u64=true:
    'rva22u64' is not available with KVM

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b30ea1677b463fba80daec4e2c6f936e0042cae2
      
https://github.com/qemu/qemu/commit/b30ea1677b463fba80daec4e2c6f936e0042cae2
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: add user flag for profile support

The TCG emulation implements all the extensions described in the
RVA22U64 profile, both mandatory and optional. The mandatory extensions
will be enabled via the profile flag. We'll leave the optional
extensions to be enabled by hand.

Given that this is the first profile we're implementing in TCG we'll
need some ground work first:

- all profiles declared in riscv_profiles[] will be exposed to users.
TCG is the main accelerator we're considering when adding profile
support in QEMU, so for now it's safe to assume that all profiles in
riscv_profiles[] will be relevant to TCG;

- we'll not support user profile settings for vendor CPUs. The flags
will still be exposed but users won't be able to change them;

- profile support, albeit available for all non-vendor CPUs, will be
based on top of the new 'rv64i' CPU. Setting a profile to 'true' means
enable all mandatory extensions of this profile, setting it to 'false'
will disable all mandatory profile extensions of the CPU, which will
obliterate preset defaults. This is not a problem for a bare CPU like
rv64i but it can allow for silly scenarios when using other CPUs. E.g.
an user can do "-cpu rv64,rva22u64=false" and have a bunch of default
rv64 extensions disabled. The recommended way of using profiles is the
rv64i CPU, but users are free to experiment.

For now we'll handle multi-letter extensions only. MISA extensions need
additional steps that we'll take care later. At this point we can boot a
Linux buildroot using rva22u64 using the following options:

-cpu rv64i,rva22u64=true,sv39=true,g=true,c=true,s=true

Note that being an usermode/application profile we still need to
explicitly set 's=true' to enable Supervisor mode to boot Linux.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 21915d16c6fbe857773cc9e10badb3e29cd7194a
      
https://github.com/qemu/qemu/commit/21915d16c6fbe857773cc9e10badb3e29cd7194a
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: add MISA user options hash

We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.

Profile support requires tne need to check for user choice for MISA
extensions, so let's add the corresponding hash now. It works like the
existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits
options in the cpu_set_misa_ext_cfg() callback.

Note that we can't re-use the same hash from multi-letter extensions
because that hash uses cpu->cfg offsets as keys, while for MISA
extensions we're using MISA bits as keys.

After adding the user hash in cpu_set_misa_ext_cfg(), setting default
values with object_property_set_bool() in add_misa_properties() will end
up marking the user choice hash with them. Set the default value
manually to avoid it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-12-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a8c31f935ceb55ab1fa771af44a5f873b65abc77
      
https://github.com/qemu/qemu/commit/a8c31f935ceb55ab1fa771af44a5f873b65abc77
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: add riscv_cpu_write_misa_bit()

We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.

Create a helper to avoid code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231218125334.37184-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3ba8462c4ca55720239fdc6fa30b9870d22a8814
      
https://github.com/qemu/qemu/commit/3ba8462c4ca55720239fdc6fa30b9870d22a8814
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: handle profile MISA bits

The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.

We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.

Now that we're setting profile MISA bits, one can use the rv64i CPU to boot
Linux using the following options:

-cpu rv64i,rva22u64=true,rv39=true,s=true,zifencei=true

In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are
mandatory), is implemented, rv64i will be able to boot Linux loading
rva22s64 and no additional flags.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-14-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5187ba5b3067679f4b9c4bb80e16dfdac3bf61fc
      
https://github.com/qemu/qemu/commit/5187ba5b3067679f4b9c4bb80e16dfdac3bf61fc
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: add hash table insert helpers

Previous patches added several g_hash_table_insert() patterns. Add two
helpers, one for each user hash, to make the code cleaner.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8b3b3451052cd7a115c9352de1bb8c74ee54a62e
      
https://github.com/qemu/qemu/commit/8b3b3451052cd7a115c9352de1bb8c74ee54a62e
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: honor user choice for G MISA bits

RVG behaves like a profile: a single flag enables a set of bits. Right
now we're considering user choice when handling RVG and zicsr/zifencei
and ignoring user choice on MISA bits.

We'll add user warnings for profiles when the user disables its
mandatory extensions in the next patch. We'll do the same thing with RVG
now to keep consistency between RVG and profile handling.

First and foremost, create a new RVG only helper to avoid clogging
riscv_cpu_validate_set_extensions(). We do not want to annoy users with
RVG warnings like we did in the past (see 9b9741c38f), thus we'll only
warn if RVG was user set and the user disabled a RVG extension in the
command line.

For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then
becomes:

- if enabled, do nothing;
- if disabled and not user set, enable it;
- if disabled and user set, throw a warning that it's a RVG mandatory
  extension.

This same logic will be used for profiles in the next patch.

Note that this is a behavior change, where we would error out if the
user disabled either zicsr or zifencei. As long as users are explicitly
disabling things in the command line we'll let them have a go at it, at
least in this step. We'll error out later in the validation if needed.

Other notable changes from the previous RVG code:

- use riscv_cpu_write_misa_bit() instead of manually updating both
  env->misa_ext and env->misa_ext_mask;

- set zicsr and zifencei directly. We're already checking if they
  were user set and priv version will never fail for these
  extensions, making cpu_cfg_ext_auto_update() redundant.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-16-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2af005d6107da71da35299449ee48e2115f1c8db
      
https://github.com/qemu/qemu/commit/2af005d6107da71da35299449ee48e2115f1c8db
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv/tcg: validate profiles during finalize

Enabling a profile and then disabling some of its mandatory extensions
is a valid use. It can be useful for debugging and testing. But the
common expected use of enabling a profile is to enable all its mandatory
extensions.

Add an user warning when mandatory extensions from an enabled profile
are disabled in the command line. We're also going to disable the
profile flag in this case since the profile must include all the
mandatory extensions. This flag can be exposed by QMP to indicate the
actual profile state after the CPU is realized.

After this patch, this will throw warnings:

-cpu rv64,rva22u64=true,zihintpause=false,zicbom=false,zicboz=false

qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
zihintpause
qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
zicbom
qemu-system-riscv64: warning: Profile rva22u64 mandates disabled extension 
zicboz

Note that the following will NOT throw warnings because the profile is
being enabled last, hence all its mandatory extensions will be enabled:

-cpu rv64,zihintpause=false,zicbom=false,zicboz=false,rva22u64=true

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6394b67615e1844dd2c0d616f0d2520533e43746
      
https://github.com/qemu/qemu/commit/6394b67615e1844dd2c0d616f0d2520533e43746
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/riscv-qmp-cmds.c

  Log Message:
  -----------
  riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

Expose all profile flags for all CPUs when executing
query-cpu-model-expansion. This will allow callers to quickly determine
if a certain profile is implemented by a given CPU. This includes vendor
CPUs - the fact that they don't have profile user flags doesn't mean
that they don't implement the profile.

After this change it's possible to quickly determine if our stock CPUs
implement the existing rva22u64 profile. Here's a few examples:

 $ ./build/qemu-system-riscv64 -S -M virt -display none
-qmp tcp:localhost:1234,server,wait=off

 $ ./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50

- As expected, the 'max' CPU implements the rva22u64 profile.

(QEMU) query-cpu-model-expansion type=full model={"name":"max"}
    {"return": {"model":
        {"name": "rv64", "props": {... "rva22u64": true, ...}}}}

- rv64 is missing "zba", "zbb", "zbs", "zkt" and "zfhmin":

query-cpu-model-expansion type=full model={"name":"rv64"}
    {"return": {"model":
        {"name": "rv64", "props": {... "rva22u64": false, ...}}}}

query-cpu-model-expansion type=full model={"name":"rv64",
    "props":{"zba":true,"zbb":true,"zbs":true,"zkt":true,"zfhmin":true}}
    {"return": {"model":
        {"name": "rv64", "props": {... "rva22u64": true, ...}}}}

We have no vendor CPUs that supports rva22u64 (veyron-v1 is the closest
- it is missing just 'zkt').

In short, aside from the 'max' CPU, we have no CPUs that supports
rva22u64 by default.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-18-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fba92a92e39069d7dc648cba1e561f28b7e91df6
      
https://github.com/qemu/qemu/commit/fba92a92e39069d7dc648cba1e561f28b7e91df6
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu-qom.h
    M target/riscv/cpu.c
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add 'rva22u64' CPU

This CPU was suggested by Alistair [1] and others during the profile
design discussions. It consists of the bare 'rv64i' CPU with rva22u64
enabled by default, like an alias of '-cpu rv64i,rva22u64=true'.

Users now have an even easier way of consuming this user-mode profile by
doing '-cpu rva22u64'. Extensions can be enabled/disabled at will on top
of it.

We can boot Linux with this "user-mode" CPU by doing:

-cpu rva22u64,sv39=true,s=true,zifencei=true

[1] 
https://lore.kernel.org/qemu-riscv/CAKmqyKP7xzZ9Sx=-Lbx2Ob0qCfB7Z+JO944FQ2TQ+49mqo0q_Q@mail.gmail.com/

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-19-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 48531f5adb2aede5519d072b9bbc27f46994ce2d
      
https://github.com/qemu/qemu/commit/48531f5adb2aede5519d072b9bbc27f46994ce2d
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_cfg.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: implement svade

'svade' is a RVA22S64 profile requirement, a profile we're going to add
shortly. It is a named feature (i.e. not a formal extension, not defined
in riscv,isa DT at this moment) defined in [1] as:

"Page-fault exceptions are raised when a page is accessed when A bit is
clear, or written when D bit is clear.".

As far as the spec goes, 'svade' is one of the two distinct modes of
handling PTE_A and PTE_D. The other way, i.e. update PTE_A/PTE_D when
they're cleared, is defined by the 'svadu' extension. Checking
cpu_helper.c, get_physical_address(), we can verify that QEMU is
compliant with that: we will update PTE_A/PTE_D if 'svadu' is enabled,
or throw a page-fault exception if 'svadu' isn't enabled.

So, as far as we're concerned, 'svade' translates to 'svadu must be
disabled'.

We'll implement it like 'zic64b': an internal flag that profiles can
enable. The flag will not be exposed to users.

[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-20-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49
      
https://github.com/qemu/qemu/commit/1a7d4fcb3fe9d4215b3d6ead362af379a82c1c49
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add priv ver restriction to profiles

Some profiles, like RVA22S64, has a priv_spec requirement.

Make this requirement explicit for all profiles. We'll validate this
requirement finalize() time and, in case the user chooses an
incompatible priv_spec while activating a profile, a warning will be
shown.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ab77a9d5074f87b7ff3df605b26d87c1909d0c01
      
https://github.com/qemu/qemu/commit/ab77a9d5074f87b7ff3df605b26d87c1909d0c01
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv/cpu.c: finalize satp_mode earlier

Profiles will need to validate satp_mode during their own finalize
methods. This will occur inside riscv_tcg_cpu_finalize_features() for
TCG. Given that satp_mode does not have any pre-req from the accelerator
finalize() method, it's safe to finalize it earlier.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-22-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e7acc1cb934bfada058c726f39548407cfb2a772
      
https://github.com/qemu/qemu/commit/e7acc1cb934bfada058c726f39548407cfb2a772
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv/cpu.c: add riscv_cpu_is_32bit()

Next patch will need to retrieve if a given RISCVCPU is 32 or 64 bit.
The existing helper riscv_is_32bit() (hw/riscv/boot.c) will always check
the first CPU of a given hart array, not any given CPU.

Create a helper to retrieve the info for any given CPU, not the first
CPU of the hart array. The helper is using the same 32 bit check that
riscv_cpu_satp_mode_finalize() was doing.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-23-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 55398025e7dfe0c8e6455e542980d1fc6157543c
      
https://github.com/qemu/qemu/commit/55398025e7dfe0c8e6455e542980d1fc6157543c
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add satp_mode profile support

'satp_mode' is a requirement for supervisor profiles like RVA22S64.
User-mode/application profiles like RVA22U64 doesn't care.

Add 'satp_mode' to the profile description. If a profile requires it,
set it during cpu_set_profile(). We'll also check it during finalize()
to validate if the running config implements the profile.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-24-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 79593ca4b00d01847baa2c710f8a3c1021b96b2f
      
https://github.com/qemu/qemu/commit/79593ca4b00d01847baa2c710f8a3c1021b96b2f
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/riscv: add 'parent' in profile description

Certain S-mode profiles, like RVA22S64 and RVA23S64, mandate all the
mandatory extensions of their respective U-mode profiles. RVA22S64
includes all mandatory extensions of RVA22U64, and the same happens with
RVA23 profiles.

Add a 'parent' field to allow profiles to enable other profiles. This
will allow us to describe S-mode profiles by specifying their parent
U-mode profile, then adding just the S-mode specific extensions.

We're naming the field 'parent' to consider the possibility of other
uses (e.g. a s-mode profile including a previous s-mode profile) in the
future.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-25-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: af651969eb23ecf018bcaa8e0761b58425de550c
      
https://github.com/qemu/qemu/commit/af651969eb23ecf018bcaa8e0761b58425de550c
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: add RVA22S64 profile

The RVA22S64 profile consists of the following:

- all mandatory extensions of RVA22U64;
- priv spec v1.12.0;
- satp mode sv39;
- Ssccptr, a cache related named feature that we're assuming always
  enable since we don't implement a cache;
- Other named features already implemented: Sstvecd, Sstvala,
  Sscounterenw;
- the new Svade named feature that was recently added.

Most of the work is already done, so this patch is enough to implement
the profile.

After this patch, the 'rva22s64' user flag alone can be used with the
rva64i CPU to boot Linux:

-cpu rv64i,rva22s64=true

This is the /proc/cpuinfo with this profile enabled:

 # cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : 
rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
mmu             : sv39

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-26-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: dfa3c4c57e15912962b7d51c9b4099f46af41991
      
https://github.com/qemu/qemu/commit/dfa3c4c57e15912962b7d51c9b4099f46af41991
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu-qom.h
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: add rva22s64 cpu

Add a new profile CPU 'rva22s64' to work as an alias of

-cpu rv64i,rva22s64

Like the existing rva22u64 CPU already does with the RVA22U64 profile.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218125334.37184-27-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 871dad3a19c660e17c412b1bc969195f814933c8
      
https://github.com/qemu/qemu/commit/871dad3a19c660e17c412b1bc969195f814933c8
  Author: Yong-Xuan Wang <yongxuan.wang@sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 
socket

The emulated AIA within the Linux kernel restores the HART index
of the IMSICs according to the configured AIA settings. During
this process, the group setting is used only when the machine
partitions harts into groups. It's unnecessary to set the group
configuration if the machine has only one socket, as its address
space might not contain the group shift.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231218090543.22353-2-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: efb91426af6506e7aa8900b9b1ed845039442030
      
https://github.com/qemu/qemu/commit/efb91426af6506e7aa8900b9b1ed845039442030
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/linux/vhost_types.h
    M include/standard-headers/linux/virtio_config.h
    M include/standard-headers/linux/virtio_pci.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-generic/unistd.h
    A linux-headers/asm-loongarch/bitsperlong.h
    A linux-headers/asm-loongarch/kvm.h
    A linux-headers/asm-loongarch/mman.h
    A linux-headers/asm-loongarch/unistd.h
    M linux-headers/asm-mips/unistd_n32.h
    M linux-headers/asm-mips/unistd_n64.h
    M linux-headers/asm-mips/unistd_o32.h
    M linux-headers/asm-powerpc/unistd_32.h
    M linux-headers/asm-powerpc/unistd_64.h
    M linux-headers/asm-riscv/kvm.h
    M linux-headers/asm-s390/unistd_32.h
    M linux-headers/asm-s390/unistd_64.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/iommufd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/psp-sev.h
    M linux-headers/linux/stddef.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h
    M linux-headers/linux/vhost.h

  Log Message:
  -----------
  linux-headers: Update to Linux v6.7-rc5

We'll add a new RISC-V linux-header file, but first let's update all
headers.

Headers for 'asm-loongarch' were added in this update.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218204321.75757-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1583ca8aa61e1648d1f340c9a6ae3cd7ba3a82ae
      
https://github.com/qemu/qemu/commit/1583ca8aa61e1648d1f340c9a6ae3cd7ba3a82ae
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    A linux-headers/asm-riscv/ptrace.h
    M scripts/update-linux-headers.sh

  Log Message:
  -----------
  linux-headers: riscv: add ptrace.h

KVM vector support for RISC-V requires the linux-header ptrace.h.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218204321.75757-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0d71f0a34938a6ac11953ae3dbec40113d2838a1
      
https://github.com/qemu/qemu/commit/0d71f0a34938a6ac11953ae3dbec40113d2838a1
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()

Linux RISC-V vector documentation (Document/arch/riscv/vector.rst)
mandates a prctl() in order to allow an userspace thread to use the
Vector extension from the host.

This is something to be done in realize() time, after init(), when we
already decided whether we're using RVV or not. We don't have a
realize() callback for KVM yet, so add kvm_cpu_realize() and enable RVV
for the thread via PR_RISCV_V_SET_CONTROL.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218204321.75757-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 3ca78c0689d504366d7c8dc516e7144940aa7c0c
      
https://github.com/qemu/qemu/commit/3ca78c0689d504366d7c8dc516e7144940aa7c0c
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/kvm/kvm-cpu.c

  Log Message:
  -----------
  target/riscv/kvm: add RVV and Vector CSR regs

Add support for RVV and Vector CSR KVM regs vstart, vl and vtype.

Support for vregs[] requires KVM side changes and an extra reg (vlenb)
and will be added later.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231218204321.75757-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e0299f71b34cb511257bcb0d2ed698b7c2a42ef4
      
https://github.com/qemu/qemu/commit/e0299f71b34cb511257bcb0d2ed698b7c2a42ef4
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M docs/system/riscv/sifive_u.rst

  Log Message:
  -----------
  docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions

Currently, the documentation outlines the process for building the
S-mode U-Boot image using `make menuconfig` and manual actions within
the menuconfig UI. However, this approach is fragile due to Kconfig
options potentially changing across different releases. For example,
CONFIG_OF_PRIOR_STAGE has been replaced by CONFIG_BOARD since v2022.01
release, and CONFIG_TEXT_BASE has been moved to the 'General setup'
menu from the 'Boot options' menu in v2024.01 release.

This update aims to make the S-mode U-Boot image build instructions
future-proof. It leverages the 'config' script provided in the U-Boot
source tree to edit the .config file, followed by a `make olddefconfig`.

Validated with U-Boot v2024.01 release.

Signed-off-by: Bin Meng <bmeng@tinylab.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240104071523.273702-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2abf0da22cbe7152940a2a90e7a4b7ba70ef04e7
      
https://github.com/qemu/qemu/commit/2abf0da22cbe7152940a2a90e7a4b7ba70ef04e7
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi

  Log Message:
  -----------
  roms/opensbi: Upgrade from v1.3.1 to v1.4

Upgrade OpenSBI from v1.3.1 to v1.4 and the pre-built bios images.

The v1.4 release includes the following commits:

1a398d9 lib: sbi: Add Zicntr as a HART ISA extension
669089c lib: sbi: Add Zihpm as a HART ISA extension
72b9c8f lib: sbi: Alphabetically sort HART ISA extensions
5359fc6 lib: sbi: Rename hart_pmu_get_allowed_bits() function
976895c lib: sbi: Fix Priv spec version for [m|s]counteren and mcountinhibit 
CSRs
6053917 lib: sbi: Fix how print gets flags
35ef182 lib: sbi: print not fill '0' when left-aligned
40dac06 lib: sbi: Add '+' flags for print
458fa74 lib: sbi: Add ' ' '\'' flags for print
05cbb6e lib: sbi: implifying the parameters of printi
fe08281 lib: sbi: print add 'o' type
c6ee5ae lib: sbi: Fix printi
3b6fcdd lib: sbi: Simplify prints
cc89fa7 lib: sbi: Fix printc
ff43168 lib: sbi: Fix timing of clearing tbuf
a73982d lib: sbi: Fix missing '\0' when buffer szie equal 1
ea6533a lib: utils/gpio: Fix RV32 compile error for designware GPIO driver
c3b98c6 include: sbi: Add macro definitions for mseccfg CSR
1c099c4 lib: sbi: Add functions to manipulate PMP entries
6c202c5 include: sbi: Add Smepmp specific access flags for PMP entries
cbcfc7b lib: sbi: Add smepmp in hart extensions
d72f5f1 lib: utils: Add detection of Smepmp from ISA string in FDT
4a42a23 lib: sbi: Grant SU R/W/X permissions to whole memory
f3fdd04 lib: sbi: Change the order of PMP initialization
5dd8db5 lib: sbi: Add support for Smepmp
6e44ef6 lib: sbi: Add functions to map/unmap shared memory
0ad8660 lib: sbi: Map/Unmap debug console shared memory buffers
057eb10 lib: utils/gpio: Fix RV32 compile error for designware GPIO driver
0e2111e libfdt: fix SPDX license identifiers
e05a9cf lib: sbi: Update system suspend to spec
5e20d25 include: sbi: fix CSR define of mseccfg
44c5151 include: sbi_utils: Remove driver pointer from struct i2c_adapter
14a35b0 lib: utils/regmap: Add generic regmap access library
8e97275 lib: utils/regmap: Add simple FDT based regmap framework
f21d8f7 lib: utils/regmap: Add simple FDT based syscon regmap driver
4a344a9 lib: utils/reset: Add syscon based reboot and poweroff
c2e6027 lib: utils/reset: Remove SiFive Test reset driver
f536e0b gitignore: allow gitignore to ignore most dot file
c744ed7 lib: sbi_pmu: Enable noncontigous hpm event and counters
6259b2e lib: utils/fdt: Fix fdt_parse_isa_extensions() implementation
f46a564 lib: sbi: Fix typo for finding fixed event counter
94197a8 fw_base.S: Fix assembler error with clang 16+
c104c60 lib: sbi: Add support for smcntrpmf
7aabeee Makefile: Fix grep warning
e7e73aa platform: generic: allwinner: correct mhpmevent count
ee1f83c lib: sbi_pmu: remove mhpm_count field in hart feature
a9cffd6 firmware: payload: test: Change to SBI v2.0 DBCN ecalls
b20bd47 lib: sbi: improve the definition of SBI_IPI_EVENT_MAX
664692f lib: sbi_pmu: ensure update hpm counter before starting counting
c9a296d platform: generic: allwinner: fix OF process for T-HEAD c9xx pmu
901d3d7 lib: sbi_pmu: keep overflow interrupt of stopped hpm counter disabled
cacfba3 platform: Allow platforms to specify the size of tlb fifo
5bd9694 lib: sbi: alloc tlb fifo by sbi_malloc
130e65d lib: sbi: Implement SET_FS_DIRTY() to make sure the mstatus FS dirty is 
set
d1e4dff lib: sbi: Introduce HART index in sbi_scratch
e6125c3 lib: sbi: Remove sbi_platform_hart_index/invalid() functions
296e70d lib: sbi: Extend sbi_hartmask to support both hartid and hartindex
e632cd7 lib: sbi: Use sbi_scratch_last_hartindex() in remote TLB managment
78c667b lib: sbi: Prefer hartindex over hartid in IPI framework
22d6ff8 lib: sbi: Remove sbi_scratch_last_hartid() macro
112daa2 lib: sbi: Maximize the use of HART index in sbi_domain
9560fb3 include: sbi: Remove sbi_hartmask_for_each_hart() macro
b8fb96e include: sbi_domain: Fix permission test macros
bff27c1 lib: sbi: Factor-out Smepmp configuration as separate function
5240d31 lib: sbi: Don't clear mseccfg.MML bit in sbi_hart_smepmp_configure()
2b51a9d lib: sbi: Fix pmp_flags for Smepmp read-only shared region
73aea28 lib: sbi: Populate M-only Smepmp entries before setting mseccfg.MML
e8bc162 lib: utils/serial: Add shared regions for serial drivers
b7e9d34 lib: utils/regmap: Mark syscon region as shared read-write
3669153 platform: generic: thead: fix stale TLB entries for th1520/sg2042
de525ac firmware: Remove ALIGN in .rela.dyn in linker script
2a6d725 firmware: Remove handling of R_RISCV_{32,64}
6ed125a Makefile: Add --exclude-libs ALL to avoid .dynsym
e21901d doc: Fix fw_payload.md
a125423 lib: utils/serial: Ensure proper allocation of PMP entries for uart8250
d36709f lib: utils: timer/ipi: Update memregion flags for PLMT and PLICSW
8197c2f lib: sbi: fix sbi_domain_get_assigned_hartmask()
9da30f6 lib: utils/fdt: simplify dt_parse_isa_extensions
942aca2 lib: utils: Simplify SET_ISA_EXT_MAP()
f831b93 lib: sbi_pmu: check for index overflows
d891cae gpio/starfive: redundant readl() call
e8114c6 docs: platform: update platform_requirements.md
3632f2b lib: sbi: Add support for mconfigptr
ec0559e lib: sbi_misaligned_ldst: Fix handling of C.SWSP and C.SDSP
cbdd869 include: sbi: Change spec version to 2.0
5d0ed1b lib: sbi: simplify sanitize_domain()
c1a6987 platform: generic: thead: move to thead c9xx header to vendor specific 
postion
8e941e7 platform: generic: thead: separate implement of T-HEAD c9xx pmu
492d9b1 platform: generic: thead: separate implement of T-HEAD c9xx errata
3e21b96 platform: generic: thead: initialize PMU by default in thead generic 
platform
a140a4e lib: sbi: Correctly limit flushes to a single ASID/VMID
88ae718 platform: generic: thead: improve tlb flush errata
52fd64b platform: Uses hart count as the default size of tlb info
07f2ccd lib: utils/serial: Optimize semihosting_putc implementation
fccdf41 firmware: fw_base.S: Fix boot hart status synchronization
d1e0f7f utils/reset: Remove fdt_reset_thead
896d2c9 lib: utils/timer: Allow ACLINT MTIMER driver to setup quirks
accafb1 lib: utils/timer: mtimer: add separate T-Head C9xx CLINT mtimer 
compatible
98bc25f lib: utils/ipi: mswi: add separate T-Head C9xx CLINT mswi compatible
5b2f55d lib: sbi: separate the swap operation of domain region
3b03cdd lib: sbi: Add regions merging when sanitizing domain region
2bfdb9e platform: generic: Add Sophgo sg2042 platform support
280f7ae include: sbi: macros for mseccfg.sseed and .useed
efcac33 lib: sbi: Add Zkr in hart extensions
6e5b0cf lib: sbi: enable seed access in S-mode
6602e11 lib: sbi: change sbi_hart_features.extensions as an array
3aaed4f lib: sbi: Make console_puts/console_putc interchangeable
dc0bb19 lib: utils/serial: remove semihosting_putc
16bb930 lib: sbi: Fix PMP granularity handling in sbi_hart_map_saddr()
574b9c8 lib: sbi_pmu: avoid buffer overflow
791704c lib: utils/irqchip: Avoid redundant writes to APLIC CLRIE register
f520256 lib: sbi: Allow relaxed MMIO writes in device ipi_send() callback
b70d628 lib: sbi: Allow relaxed MMIO writes in device ipi_clear() callback
bd74931 lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
291403f sbi: sbi_pmu: Improve sbi_pmu_init() error handling
090fa99 lib: sbi: Add XAndesPMU in hart extensions
a48f2cf sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
51ec60c platform: include: andes45: Add PMU related CSR defines
effd89a platform: generic: Introduce pmu_init() platform override
1b9e743 platform: andes: Add Andes custom PMU support
2e50c24 platform: andes: Enable Andes PMU for AE350
535c661 platform: rzfive: Enable Andes PMU for RZ/Five
0b3262e lib: utils: fdt_fixup: Allow preserving PMU properties
009ae4e platform: andes: Factor out is_andes() helper
0308f93 lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable
e19d419 lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table
d162009 docs: pmu: Add Andes PMU node example
6b9a849 lib: sbi: Remove xchg/cmpxchg implemented via lr/sc
11bf49b lib: sbi: Fix __atomic_op_bit_ord and comments
8839869 lib: sbi: Replace __atomic_op_bit_ord with __atomic intrinsics
07419ec lib: sbi: Prevent redundant sbi_ipi_process
93da66b lib: sbi_hart: Store PMP granularity as log base 2
ee72517 lib: sbi_pmu: Add PMU snapshot definitions
11a0ba5 lib: sbi_pmu: Fix the counter info function
0696810 firmware: fix section types
a25fc74 lib: sbi_hsm: Put the resume_pending hart in the interruptible hart mask
87aa306 platform: recalculate heap size to support new tlb entry number
a2e254e lib: sbi: skip wait_for_coldboot when coolboot done
6112d58 lib: utils/fdt: Allow to use reg-names when parsing ACLINT
35cba92 lib: sbi_tlb: Check tlb_range_flush_limit only once per request
a894187 lib: sbi_ipi: Do not ignore errors from sbi_ipi_send()
446fa65 lib: sbi_ipi: Process self-IPIs in sbi_ipi_send()
2707250 lib: sbi_ipi: Drop unnecessary ipi_process check
925ce14 lib: sbi: Simplify the initialization of root_hmask in sbi_domain_init
2c8be56 lib: sbi: Improve the code of privilege mode and extensions detection
056fe6f lib: sbi: Refactor the code for enable extensions in menvfg CSR
776770d lib: sbi: Using one array to define the name of extensions
3daac8f lib: sbi: Detect extensions from the ISA string in DT
416ceb3 lib: sbi_tlb: Reduce size of struct sbi_tlb_info
80169b2 platform: generic: Fine tune fw_platform_calculate_heap_size()
cdebae2 lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
3284bea lib: sbi: Allow ecall handlers to directly update register state
5a57e8c lib: sbi: Remove the SBI_ETRAP error code
2b80b92 lib: sbi: Do not enter OpenSBI with mseccfg.MML == 1
63e09ad lib: sbi: Fix shift bug in sbi_system_reset
ba29293 lib: utils/timer: mtimer: only use regname for aclint
bbd065d lib: sbi: Detect Zicntr extension only based on traps
a2b255b include: Bump-up version to 1.4

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20240102151153.133896-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1a25e59c621f77cf21ad7dd9a86606170ff6e4b6
      
https://github.com/qemu/qemu/commit/1a25e59c621f77cf21ad7dd9a86606170ff6e4b6
  Author: Ivan Klokov <ivan.klokov@syntacore.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: pmp: Ignore writes when RW=01 and MML=0

This patch changes behavior on writing RW=01 to pmpcfg with MML=0.
RWX filed is form of collective WARL with the combination of
pmpcfg.RW=01 remains reserved for future standard use.

According to definition of WARL writing the CSR has no other side
effect. But current implementation change architectural state and
change system behavior. After writing we will get unreadable-unwriteble
region regardless on the previous state.

On the other side WARL said that we should read legal value and nothing
says about what we should write. Current behavior change system state
regardless of whether we read this register or not.

Fixes: ac66f2f0 ("target/riscv: pmp: Ignore writes when RW=01")

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231220153205.11072-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9a7c6da4cd8458c76f619d84542f91d308ecb15f
      
https://github.com/qemu/qemu/commit/9a7c6da4cd8458c76f619d84542f91d308ecb15f
  Author: Alistair Francis <alistair23@gmail.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Assert that the CSR numbers will be correct

The CSRs will always be between either CSR_MHPMCOUNTER3 and
CSR_MHPMCOUNTER31 or CSR_MHPMCOUNTER3H and CSR_MHPMCOUNTER31H.

So although ctr_index can't be negative, Coverity doesn't know this and
it isn't obvious to human readers either. Let's add an assert to ensure
that Coverity knows the values will be within range.

To simplify the code let's also change the RV32 adjustment.

Fixes: Coverity CID 1523910
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-2-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1525d8aa3a56610e1c72f5dd305ec86ebad41769
      
https://github.com/qemu/qemu/commit/1525d8aa3a56610e1c72f5dd305ec86ebad41769
  Author: Alistair Francis <alistair23@gmail.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Don't adjust vscause for exceptions

We have been incorrectly adjusting both the interrupt and exception
cause when using the hypervisor extension and trapping to VS-mode. This
patch changes the conditional to ensure we only adjust the cause for
interrupts and not exceptions.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1708
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 71b76da33a1558bcd59100188f5753737ef6fa21
      
https://github.com/qemu/qemu/commit/71b76da33a1558bcd59100188f5753737ef6fa21
  Author: Alistair Francis <alistair23@gmail.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Ensure mideleg is set correctly on reset

Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is
enabled. We currently only set them on accesses to mideleg, but they
aren't correctly set on reset. Let's ensure they are always the correct
value.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1617
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240108001328.280222-4-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: eb7b9b29135983cbf98da0853cf22f49d928260b
      
https://github.com/qemu/qemu/commit/eb7b9b29135983cbf98da0853cf22f49d928260b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M include/qemu/fifo8.h
    M util/fifo8.c

  Log Message:
  -----------
  Merge tag 'qemu-sparc-20240110' of https://github.com/mcayland/qemu into 
staging

qemu-sparc queue

# -----BEGIN PGP SIGNATURE-----
#
# iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmWeQHgeHG1hcmsuY2F2
# ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIffQgH/jbg3YfDy6IjCeTp
# /R40dSCTodlDt2W8pT9wjXM+wJiVpz6tGVMdxrgdxM5cEyaga2d2EXDYu/FkxqS5
# 3kvF84IaIRFF0Zbc9Dg3Dl9mybyIyby/+QVDQlaaLaluvDc+EpX9ANBhZPyHRF+f
# iy/jhYK2hChjOvmTBe/mVlLiOKLkOEgigG4eyk9azTztVzcm2t+PYC4YLVKOoeCl
# Sq0MfDHYdzW+2Vp3F+6sizqIAdpNAaKlcnLPx7BunP6z2iUxqu5ka0WQpOEtfsRj
# z4pt1KJhar6jbhP6++GM7FlQzPyzEZhToR1fVPlmFLl4ep1iTMIxnoGmdHWuHVE5
# YaRZS2Q=
# =jg1P
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 10 Jan 2024 07:00:08 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" 
[full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* tag 'qemu-sparc-20240110' of https://github.com/mcayland/qemu:
  util/fifo8: Introduce fifo8_peek_buf()
  util/fifo8: Allow fifo8_pop_buf() to not populate popped length

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 34eac35f893664eb8545b98142e23d9954722766
      
https://github.com/qemu/qemu/commit/34eac35f893664eb8545b98142e23d9954722766
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M disas/riscv.c
    M docs/system/riscv/sifive_u.rst
    M docs/system/riscv/virt.rst
    M hw/arm/virt-acpi-build.c
    M hw/i386/acpi-microvm.c
    A hw/nvram/fw_cfg-acpi.c
    M hw/nvram/meson.build
    M hw/pci-host/gpex-acpi.c
    M hw/pci-host/gpex.c
    M hw/riscv/Kconfig
    M hw/riscv/virt-acpi-build.c
    M hw/riscv/virt.c
    M hw/virtio/meson.build
    A hw/virtio/virtio-acpi.c
    A include/hw/nvram/fw_cfg_acpi.h
    M include/hw/pci-host/gpex.h
    M include/hw/riscv/virt.h
    A include/hw/virtio/virtio-acpi.h
    M include/standard-headers/drm/drm_fourcc.h
    M include/standard-headers/linux/pci_regs.h
    M include/standard-headers/linux/vhost_types.h
    M include/standard-headers/linux/virtio_config.h
    M include/standard-headers/linux/virtio_pci.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-generic/unistd.h
    A linux-headers/asm-loongarch/bitsperlong.h
    A linux-headers/asm-loongarch/kvm.h
    A linux-headers/asm-loongarch/mman.h
    A linux-headers/asm-loongarch/unistd.h
    M linux-headers/asm-mips/unistd_n32.h
    M linux-headers/asm-mips/unistd_n64.h
    M linux-headers/asm-mips/unistd_o32.h
    M linux-headers/asm-powerpc/unistd_32.h
    M linux-headers/asm-powerpc/unistd_64.h
    M linux-headers/asm-riscv/kvm.h
    A linux-headers/asm-riscv/ptrace.h
    M linux-headers/asm-s390/unistd_32.h
    M linux-headers/asm-s390/unistd_64.h
    M linux-headers/asm-x86/unistd_32.h
    M linux-headers/asm-x86/unistd_64.h
    M linux-headers/asm-x86/unistd_x32.h
    M linux-headers/linux/iommufd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/psp-sev.h
    M linux-headers/linux/stddef.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h
    M linux-headers/linux/vhost.h
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi
    M scripts/update-linux-headers.sh
    M target/riscv/cpu-qom.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_cfg.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvv.c.inc
    A target/riscv/insn_trans/trans_rvzacas.c.inc
    M target/riscv/insn_trans/trans_xthead.c.inc
    M target/riscv/kvm/kvm-cpu.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/riscv-qmp-cmds.c
    M target/riscv/tcg/tcg-cpu.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20240110' of 
https://github.com/alistair23/qemu into staging

RISC-V PR for 9.0

* Make vector whole-register move (vmv) depend on vtype register
* Fix th.dcache.cval1 priviledge check
* Don't allow write mstatus_vs without RVV
* Use hwaddr instead of target_ulong for RV32
* Fix machine IDs QOM getters\
* Fix KVM reg id sizes
* ACPI: Enable AIA, PLIC and update RHCT
* Fix the interrupts-extended property format of PLIC
* Add support for Zacas extension
* Add amocas.[w,d,q] instructions
* Document acpi parameter of virt machine
* RVA22 profiles support
* Remove group setting of KVM AIA if the machine only has 1 socket
* Add RVV CSRs to KVM
* sifive_u: Update S-mode U-Boot image build instructions
* Upgrade OpenSBI from v1.3.1 to v1.4
* pmp: Ignore writes when RW=01 and MML=0
* Assert that the CSR numbers will be correct
* Don't adjust vscause for exceptions
* Ensure mideleg is set correctly on reset

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmWeW8kACgkQr3yVEwxT
# gBMB3BAAtpb7dC/NqDOjo/LjGf81wYUnF0KcfJUIbuHEM9S03mKJEvngV/sUhg+A
# fzsoJazijQZk2+Y02WLT/o+ppRDegb4P6n54Nn13xr024Dn2jf45+EKDLI+vtU5y
# lhwp/LH3SEo2MM/Qr0njl8+jJ7W9adhZeK6x+NFaLaQJ291xupbcwEnScdv2bPAo
# gvbM6yrfUoZ25MsQKIDGssozdGRwOD/keAT0q8C0gKDamqXBDrI80BOVhRms+uLm
# R33DXsAegPKluJTa9gfaWFI0eK34WHXRvSIjE36nZlGNNgqLAVdM2/QozMVz4cKA
# Ymz1nzqB9HeSn1pM4KCK/Y3LH89qLGWtyHYgldiDXA/wSyKajwkbXSWFOT9gPDqV
# i+5BRDvU0zIeMIt+ROqNKgx1Hry6U2aycMNsdHTmygJbGEpiTaXuES5tt+LKsyHe
# w/7a6wPd/kh9LQhXYQ4qbn7L534tWvn8zWyvKLZLxmYPcOn6SdjFbKWmk5ARky2W
# sx9ojn9ANlYaLfzQ3TMRcIhWD6n8Si3KFNiQ3353E8xkRkyfu0WHyXAy8/kIc5UT
# nScO2YD68XkdkcLF6uLUKuGiVZXFWXRY1Ttz9tvEmBckVsg6TIkoMONHeUWNP7ly
# A0bJwN5qEOk6XIYKHWwX5UzvkcfUpOb5VmuLuv3gRoNX0A7/+fc=
# =5K9J
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 10 Jan 2024 08:56:41 GMT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu: (65 
commits)
  target/riscv: Ensure mideleg is set correctly on reset
  target/riscv: Don't adjust vscause for exceptions
  target/riscv: Assert that the CSR numbers will be correct
  target/riscv: pmp: Ignore writes when RW=01 and MML=0
  roms/opensbi: Upgrade from v1.3.1 to v1.4
  docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions
  target/riscv/kvm: add RVV and Vector CSR regs
  target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()
  linux-headers: riscv: add ptrace.h
  linux-headers: Update to Linux v6.7-rc5
  target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 
socket
  target/riscv: add rva22s64 cpu
  target/riscv: add RVA22S64 profile
  target/riscv: add 'parent' in profile description
  target/riscv: add satp_mode profile support
  target/riscv/cpu.c: add riscv_cpu_is_32bit()
  target/riscv/cpu.c: finalize satp_mode earlier
  target/riscv: add priv ver restriction to profiles
  target/riscv: implement svade
  target/riscv: add 'rva22u64' CPU
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/9468484fe904...34eac35f8936



reply via email to

[Prev in Thread] Current Thread [Next in Thread]