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[Qemu-commits] [qemu/qemu] f7f578: hw/arm: add cache controller for Free


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] f7f578: hw/arm: add cache controller for Freescale i.MX6
Date: Thu, 11 Jan 2024 03:06:12 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: f7f5784af19155df658237d1aae04297d371402b
      
https://github.com/qemu/qemu/commit/f7f5784af19155df658237d1aae04297d371402b
  Author: Nikita Ostrenkov <n.ostrenkov@gmail.com>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/fsl-imx6.c

  Log Message:
  -----------
  hw/arm: add cache controller for Freescale i.MX6

Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231219105510.4907-1-n.ostrenkov@gmail.com
[PMM: fixed stray whitespace]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 04a7c7b130c3b9d2b97912de76dc7c6ffc6742cf
      
https://github.com/qemu/qemu/commit/04a7c7b130c3b9d2b97912de76dc7c6ffc6742cf
  Author: Inès Varhol <ines.varhol@telecom-paris.fr>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M MAINTAINERS
    M hw/arm/Kconfig
    M hw/arm/meson.build
    A hw/arm/stm32l4x5_soc.c
    A include/hw/arm/stm32l4x5_soc.h

  Log Message:
  -----------
  hw/arm: Add minimal support for the STM32L4x5 SoC

This patch adds a new STM32L4x5 SoC, it is necessary to add support for
the B-L475E-IOT01A board.
The implementation is derived from the STM32F405 SoC.
The implementation contains no peripherals, only memory regions are
implemented.

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240108135849.351719-2-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 41581f13619d0d66593a75c5299c8d546710cc9e
      
https://github.com/qemu/qemu/commit/41581f13619d0d66593a75c5299c8d546710cc9e
  Author: Inès Varhol <ines.varhol@telecom-paris.fr>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M MAINTAINERS
    M configs/devices/arm-softmmu/default.mak
    A docs/system/arm/b-l475e-iot01a.rst
    M docs/system/arm/stm32.rst
    M docs/system/target-arm.rst
    M hw/arm/Kconfig
    A hw/arm/b-l475e-iot01a.c
    M hw/arm/meson.build

  Log Message:
  -----------
  hw/arm: Add minimal support for the B-L475E-IOT01A board

This commit adds a new B-L475E-IOT01A board using the STM32L475VG SoC
as well as a dedicated documentation file.
The implementation is derived from the Netduino Plus 2 machine.
There are no peripherals implemented yet, only memory regions.

Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240108135849.351719-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d09923ad19fc3d653693ee81f1742fb8d29c5730
      
https://github.com/qemu/qemu/commit/d09923ad19fc3d653693ee81f1742fb8d29c5730
  Author: Samuel Tardieu <sam@rfc1149.net>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: add "num-prio-bits" property

Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.

This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.

Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240106181503.1746200-2-sam@rfc1149.net
Suggested-by: Anton Kochkov <anton.kochkov@proton.me>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 33995902b462cf1c4ba1177ee758713dd8d4ec0d
      
https://github.com/qemu/qemu/commit/33995902b462cf1c4ba1177ee758713dd8d4ec0d
  Author: Samuel Tardieu <sam@rfc1149.net>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/armv7m.h

  Log Message:
  -----------
  hw/arm/armv7m: alias the NVIC "num-prio-bits" property

A SoC will not have a direct access to the NVIC embedded in its ARM
core. By aliasing the "num-prio-bits" property similarly to what is
done for the "num-irq" one, a SoC can easily configure it on its
armv7m instance.

Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240106181503.1746200-3-sam@rfc1149.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59
      
https://github.com/qemu/qemu/commit/4a04655c6bdeb1043a4b7477f54f76a3d6a3ec59
  Author: Samuel Tardieu <sam@rfc1149.net>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/arm/stellaris.c
    M hw/arm/stm32f100_soc.c
    M hw/arm/stm32f205_soc.c
    M hw/arm/stm32f405_soc.c
    M hw/arm/stm32l4x5_soc.c

  Log Message:
  -----------
  hw/arm/socs: configure priority bits for existing SOCs

Update the number of priority bits for a number of existing
SoCs according to their technical documentation:

- STM32F100/F205/F405/L4x5: 4 bits
- Stellaris (Sandstorm/Fury): 3 bits

Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240106181503.1746200-4-sam@rfc1149.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f503bc4b6b38d1840d41922875fffc88d67dd17a
      
https://github.com/qemu/qemu/commit/f503bc4b6b38d1840d41922875fffc88d67dd17a
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/arm/msf2-som.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/olimex-stm32-h405.c
    M hw/arm/stm32vldiscovery.c

  Log Message:
  -----------
  hw/arm: Add missing QOM parent for v7-M SoCs

QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240104141159.53883-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3d65b958c5463a1c06cac51b6474097ecdbb576e
      
https://github.com/qemu/qemu/commit/3d65b958c5463a1c06cac51b6474097ecdbb576e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU

The CTR_EL0 register has some bits which allow the implementation to
tell the guest that it does not need to do cache maintenance for
data-to-instruction coherence and instruction-to-data coherence.
QEMU doesn't emulate caches and so our cache maintenance insns are
all NOPs.

We already have some models of specific CPUs where we set these bits
(e.g.  the Neoverse V1), but the 'max' CPU still uses the settings it
inherits from Cortex-A57.  Set the bits for 'max' as well, so the
guest doesn't need to do unnecessary work.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 82a65e3188abebb509510b391726711606aca642
      
https://github.com/qemu/qemu/commit/82a65e3188abebb509510b391726711606aca642
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers

The hypervisor can deliver (virtual) LPIs to a guest by setting up a
list register to have an intid which is an LPI.  The GIC has to treat
these a little differently to standard interrupt IDs, because LPIs
have no Active state, and so the guest will only EOI them, it will
not also deactivate them.  So icv_eoir_write() must do two things:

 * if the LPI ID is not in any list register, we drop the
   priority but do not increment the EOI count
 * if the LPI ID is in a list register, we immediately deactivate
   it, regardless of the split-drop-and-deactivate control

This can be seen in the VirtualWriteEOIR0() and VirtualWriteEOIR1()
pseudocode in the GICv3 architecture specification.

Without this fix, potentially a hypervisor guest might stall because
LPIs get stuck in a bogus Active+Pending state.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 67e55c73c3488762eb732f9e33f352f39093f831
      
https://github.com/qemu/qemu/commit/67e55c73c3488762eb732f9e33f352f39093f831
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu-features.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV

FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT.  When the
feature is enabled, allow these bits to be written, and flush the
TLBs for the bits which affect page table interpretation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 572597791555c544169e49b9a5c3a4043ea4949b
      
https://github.com/qemu/qemu/commit/572597791555c544169e49b9a5c3a4043ea4949b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HCR_EL2.AT handling

The FEAT_NV HCR_EL2.AT bit enables trapping of some address
translation instructions from EL1 to EL2.  Implement this behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: e37e98b7f9f69240f73ed7050cd182466ddf3629
      
https://github.com/qemu/qemu/commit/e37e98b7f9f69240f73ed7050cd182466ddf3629
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Enable trapping of ERET for FEAT_NV

When FEAT_NV is turned on via the HCR_EL2.NV bit, ERET instructions
are trapped, with the same syndrome information as for the existing
FEAT_FGT fine-grained trap (in the pseudocode this is handled in
AArch64.CheckForEretTrap()).

Rename the DisasContext and tbflag bits to reflect that they are
no longer exclusively for FGT traps, and set the tbflag bit when
FEAT_NV is enabled as well as when the FGT is enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: b9377d1c5f366e3c914fb32ca13a2178ea901b2d
      
https://github.com/qemu/qemu/commit/b9377d1c5f366e3c914fb32ca13a2178ea901b2d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/tcg/op_helper.c

  Log Message:
  -----------
  target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set

The HCR_EL2.TSC trap for trapping EL1 execution of SMC instructions
has a behaviour change for FEAT_NV when EL3 is not implemented:

 * in older architecture versions TSC was required to have no
   effect (i.e. the SMC insn UNDEFs)
 * with FEAT_NV, when HCR_EL2.NV == 1 the trap must apply
   (i.e. SMC traps to EL2, as it already does in all cases when
   EL3 is implemented)
 * in newer architecture versions, the behaviour either without
   FEAT_NV or with FEAT_NV and HCR_EL2.NV == 0 is relaxed to
   an IMPDEF choice between UNDEF and trap-to-EL2 (i.e. it is
   permitted to always honour HCR_EL2.TSC) for AArch64 only

Add the condition to honour the trap bit when HCR_EL2.NV == 1.  We
leave the HCR_EL2.NV == 0 case with the existing (UNDEF) behaviour,
as our IMPDEF choice (both because it avoids a behaviour change
for older CPU models and because we'd have to distinguish AArch32
from AArch64 if we opted to trap to EL2).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 29a15a61679dd35d8e2f4ea2c5fca77e476324db
      
https://github.com/qemu/qemu/commit/29a15a61679dd35d8e2f4ea2c5fca77e476324db
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Allow use of upper 32 bits of TBFLAG_A64

The TBFLAG_A64 TB flag bits go in flags2, which for AArch64 guests
we know is 64 bits. However at the moment we use FIELD_EX32() and
FIELD_DP32() to read and write these bits, which only works for
bits 0 to 31. Since we're about to add a flag that uses bit 32,
switch to FIELD_EX64() and FIELD_DP64() so that this will work.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 6f53b1267bb68b55bde65248212bcc071a15848f
      
https://github.com/qemu/qemu/commit/6f53b1267bb68b55bde65248212bcc071a15848f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Record correct opcode fields in cpreg for E2H aliases

For FEAT_VHE, we define a set of register aliases, so that for instance:
 * the SCTLR_EL1 either accesses the real SCTLR_EL1, or (if E2H is 1)
   SCTLR_EL2
 * a new SCTLR_EL12 register accesses SCTLR_EL1 if E2H is 1

However when we create the 'new_reg' cpreg struct for the SCTLR_EL12
register, we duplicate the information in the SCTLR_EL1 cpreg, which
means the opcode fields are those of SCTLR_EL1, not SCTLR_EL12.  This
is a problem for code which looks at the cpreg opcode fields to
determine behaviour (e.g.  in access_check_cp_reg()). In practice
the current checks we do there don't intersect with the *_EL12
registers, but for FEAT_NV this will become a problem.

Write the correct values from the encoding into the new_reg struct.
This restores the invariant that the cpreg that you get back
from the hashtable has opcode fields that match the key you used
to retrieve it.

When we call the readfn or writefn for the target register, we
pass it the cpreg struct for that target register, not the one
for the alias, in case the readfn/writefn want to look at the
opcode fields to determine behaviour. This means we need to
interpose custom read/writefns for the e12 aliases.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: e730287cef2a0c2889ed819fc158e21117cd84f8
      
https://github.com/qemu/qemu/commit/e730287cef2a0c2889ed819fc158e21117cd84f8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0

The alias registers like SCTLR_EL12 only exist when HCR_EL2.E2H
is 1; they should UNDEF otherwise. We weren't implementing this.
Add an intercept of the accessfn for these aliases, and implement
the UNDEF check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 83aea11db036f18e60cb2bb10383e4bcdb1e4b08
      
https://github.com/qemu/qemu/commit/83aea11db036f18e60cb2bb10383e4bcdb1e4b08
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/debug_helper.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses

FEAT_NV and FEAT_NV2 will allow EL1 to attempt to access cpregs that
only exist at EL2. This means we're going to want to run their
accessfns when the CPU is at EL1. In almost all cases, the behaviour
we want is "the accessfn returns OK if at EL1".

Mostly the accessfn already does the right thing; in a few cases we
need to explicitly check that the EL is not 1 before applying various
trap controls, or split out an accessfn used both for an _EL1 and an
_EL2 register into two so we can handle the FEAT_NV case correctly
for the _EL2 register.

There are two registers where we want the accessfn to trap for
a FEAT_NV EL1 access: VSTTBR_EL2 and VSTCR_EL2 should UNDEF
an access from NonSecure EL1, not trap to EL2 under FEAT_NV.
The way we have written sel2_access() already results in this
behaviour.

We can identify the registers we care about here because they
all have opc1 == 4 or 5.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 44572fc984b5fb80a2fe05f22e7146d55733eed1
      
https://github.com/qemu/qemu/commit/44572fc984b5fb80a2fe05f22e7146d55733eed1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check

In handle_sys() we don't do the check for whether the register is
marked as needing an FPU/SVE/SME access check until after we've
handled the special cases covered by ARM_CP_SPECIAL_MASK.  This is
conceptually the wrong way around, because if for example we happen
to implement an FPU-access-checked register as ARM_CP_NOP, we should
do the access check first.

Move the access checks up so they are with all the other access
checks, not sandwiched between the special-case read/write handling
and the normal-case read/write handling. This doesn't change
behaviour at the moment, because we happen not to define any
cpregs with both ARM_CPU_{FPU,SVE,SME} and one of the cases
dealt with by ARM_CP_SPECIAL_MASK.

Moving this code also means we have the correct place to put the
FEAT_NV/FEAT_NV2 access handling, which should come after the access
checks and before we try to do any read/write action.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 67d10fc4737a44366524295ea6049841e5e593e6
      
https://github.com/qemu/qemu/commit/67d10fc4737a44366524295ea6049841e5e593e6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/cpu.h
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Trap sysreg accesses for FEAT_NV

For FEAT_NV, accesses to system registers and instructions from EL1
which would normally UNDEF there but which work in EL2 need to
instead be trapped to EL2. Detect this both for "we know this will
UNDEF at translate time" and "we found this UNDEFs at runtime", and
make the affected registers trap to EL2 instead.

The Arm ARM defines the set of registers that should trap in terms
of their names; for our implementation this would be both awkward
and inefficent as a test, so we instead trap based on the opc1
field of the sysreg. The regularity of the architectural choice
of encodings for sysregs means that in practice this captures
exactly the correct set of registers.

Regardless of how we try to define the registers this trapping
applies to, there's going to be a certain possibility of breakage
if new architectural features introduce new registers that don't
follow the current rules (FEAT_MEC is one example already visible
in the released sysreg XML, though not yet in the Arm ARM). This
approach seems to me to be straightforward and likely to require
a minimum of manual overrides.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: b7ecc3da6c87f8a57805acfc46922684f8a26eea
      
https://github.com/qemu/qemu/commit/b7ecc3da6c87f8a57805acfc46922684f8a26eea
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Make NV reads of CurrentEL return EL2

FEAT_NV requires that when HCR_EL2.NV is set reads of the CurrentEL
register from EL1 always report EL2 rather than the real EL.
Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 29eda9cd1987d69b089ed5413c8e39aecd618e17
      
https://github.com/qemu/qemu/commit/29eda9cd1987d69b089ed5413c8e39aecd618e17
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Set SPSR_EL1.M correctly when nested virt is enabled

FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,0} and an exception
is taken from EL1 to EL1 then the reported EL in SPSR_EL1.M should be
EL2, not EL1.  Implement this behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: ad4e2d4db13e17726cd68908f5c4043bf82051f8
      
https://github.com/qemu/qemu/commit/ad4e2d4db13e17726cd68908f5c4043bf82051f8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1}

When HCR_EL2.{NV,NV1} is {1,1} we must trap five extra registers to
EL2: VBAR_EL1, ELR_EL1, SPSR_EL1, SCXTNUM_EL1 and TFSR_EL1.
Implement these traps.

This trap does not apply when FEAT_NV2 is implemented and enabled;
include the check that HCR_EL2.NV2 is 0 here, to save us having
to come back and add it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 7fda076357684b643e1abc0553a1622b25c43a05
      
https://github.com/qemu/qemu/commit/7fda076357684b643e1abc0553a1622b25c43a05
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Always use arm_pan_enabled() when checking if PAN is enabled

Currently the code in target/arm/helper.c mostly checks the PAN bits
in env->pstate or env->uncached_cpsr directly when it wants to know
if PAN is enabled, because in most callsites we know whether we are
in AArch64 or AArch32. We do have an arm_pan_enabled() function, but
we only use it in a few places where the code might run in either an
AArch32 or AArch64 context.

For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled
even when the PSTATE.PAN bit is set, the "is PAN enabled" test
becomes more complicated. Make all places that check for PAN use
arm_pan_enabled(), so we have a place to put the FEAT_NV test.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: f11440b4261fd5db888c300936c0c4537543aed6
      
https://github.com/qemu/qemu/commit/f11440b4261fd5db888c300936c0c4537543aed6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}

For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled
even when the PSTATE.PAN bit is set. Implement this by having
arm_pan_enabled() return false in this situation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 2e9b1e50bdf61cadff91ba16f6fc92ef4317803f
      
https://github.com/qemu/qemu/commit/2e9b1e50bdf61cadff91ba16f6fc92ef4317803f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/tcg/hflags.c

  Log Message:
  -----------
  target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1

FEAT_NV requires (per I_JKLJK) that when HCR_EL2.{NV,NV1} is {1,1} the
unprivileged-access instructions LDTR, STTR etc behave as normal
loads and stores. Implement the check that handles this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: dea9104a4f85388a1419701a18eb33c354f5658f
      
https://github.com/qemu/qemu/commit/dea9104a4f85388a1419701a18eb33c354f5658f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Handle FEAT_NV page table attribute changes

FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,1} the handling
of some of the page table attribute bits changes for the EL1&0
translation regime:

 * for block and page descriptors:
  - bit [54] holds PXN, not UXN
  - bit [53] is RES0, and the effective value of UXN is 0
  - bit [6], AP[1], is treated as 0
 * for table descriptors, when hierarchical permissions are enabled:
  - bit [60] holds PXNTable, not UXNTable
  - bit [59] is RES0
  - bit [61], APTable[0] is treated as 0

Implement these changes to the page table attribute handling.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 1274a47fbd9739b628835936dbefa0294d9dd32c
      
https://github.com/qemu/qemu/commit/1274a47fbd9739b628835936dbefa0294d9dd32c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu.c
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs

Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the
Neoverse N2 and Neoverse V1 CPUs.  We continue to downgrade FEAT_NV2
support to FEAT_NV for the latter two CPU types.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa
      
https://github.com/qemu/qemu/commit/a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu-features.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits

FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the
feature is enabled, allow this bit to be written in HCR_EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: b5ba6c99a81a2f57fb004709169679e552bdabdb
      
https://github.com/qemu/qemu/commit/b5ba6c99a81a2f57fb004709169679e552bdabdb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement VNCR_EL2 register

For FEAT_NV2, a new system register VNCR_EL2 holds the base
address of the memory which nested-guest system register
accesses are redirected to. Implement this register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: ef8a4a8816d166102545e3404a00c4e50b4496ee
      
https://github.com/qemu/qemu/commit/ef8a4a8816d166102545e3404a00c4e50b4496ee
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2

With FEAT_NV2, the condition for when SPSR_EL1.M should report that
an exception was taken from EL2 changes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: c35da11df40678d606064f75a7c2d747efa1b302
      
https://github.com/qemu/qemu/commit/c35da11df40678d606064f75a7c2d747efa1b302
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2

Under FEAT_NV2, when HCR_EL2.{NV,NV2} == 0b11 at EL1, accesses to the
registers SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 and TFSR_EL2 (which
would UNDEF without FEAT_NV or FEAT_NV2) should instead access the
equivalent EL1 registers SPSR_EL1, ELR_EL1, ESR_EL1, FAR_EL1 and
TFSR_EL1.

Because there are only five registers involved and the encoding for
the EL1 register is identical to that of the EL2 register except
that opc1 is 0, we handle this by finding the EL1 register in the
hash table and using it instead.

Note that traps that apply to direct accesses to the EL1 register,
such as active fine-grained traps or other trap bits, do not trigger
when it is accessed via the EL2 encoding in this way.  However, some
traps that are defined by the EL2 register may apply.  We therefore
call the EL2 register's accessfn first.  The only one of the five
which has such traps is TFSR_EL2: make sure its accessfn correctly
handles both FEAT_NV (where we trap to EL2 without checking ATA bits)
and FEAT_NV2 (where we check ATA bits and then redirect to TFSR_EL1).

(We don't need the NV1 tbflag bit until the next patch, but we
introduce it here to avoid putting the NV, NV1, NV2 bits in an
odd order.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: daf9b4a00fd19dcab8df9091080367889befa4c2
      
https://github.com/qemu/qemu/commit/daf9b4a00fd19dcab8df9091080367889befa4c2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h
    M target/arm/cpu.h
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Implement FEAT_NV2 redirection of sysregs to RAM

FEAT_NV2 requires that when HCR_EL2.{NV,NV2} == 0b11 then accesses by
EL1 to certain system registers are redirected to RAM.  The full list
of affected registers is in the table in rule R_CSRPQ in the Arm ARM.
The registers may be normally accessible at EL1 (like ACTLR_EL1), or
normally UNDEF at EL1 (like HCR_EL2).  Some registers redirect to RAM
only when HCR_EL2.NV1 is 0, and some only when HCR_EL2.NV1 is 1;
others trap in both cases.

Add the infrastructure for identifying which registers should be
redirected and turning them into memory accesses.

This code does not set the correct syndrome or arrange for the
exception to be taken to the correct target EL if the access via
VNCR_EL2 faults; we will do that in the next commit.

Subsequent commits will mark up the relevant regdefs to set their
nv2_redirect_offset, and if relevant one of the two flags which
indicates that the redirect happens only for a particular value of
HCR_EL2.NV1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 674e5345275d42581ed859acfb1ef14ebf98f9d6
      
https://github.com/qemu/qemu/commit/674e5345275d42581ed859acfb1ef14ebf98f9d6
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/syndrome.h
    M target/arm/tcg/tlb_helper.c
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Report VNCR_EL2 based faults correctly

If FEAT_NV2 redirects a system register access to a memory offset
from VNCR_EL2, that access might fault.  In this case we need to
report the correct syndrome information:
 * Data Abort, from same-EL
 * no ISS information
 * the VNCR bit (bit 13) is set

and the exception must be taken to EL2.

Save an appropriate syndrome template when generating code; we can
then use that to:
 * select the right target EL
 * reconstitute a correct final syndrome for the data abort
 * report the right syndrome if we take a FEAT_RME granule protection
   fault on the VNCR-based write

Note that because VNCR is bit 13, we must start keeping bit 13 in
template syndromes, by adjusting ARM_INSN_START_WORD2_SHIFT.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: dfe8a9ee6a8896c642b0ec0af4b484328249619a
      
https://github.com/qemu/qemu/commit/dfe8a9ee6a8896c642b0ec0af4b484328249619a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mark up VNCR offsets (offsets 0x0..0xff)

Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets below 0x100; all of these
registers are redirected to memory regardless of the value of
HCR_EL2.NV1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: bb7b95b070e3439eb46066963e6b870697344904
      
https://github.com/qemu/qemu/commit/bb7b95b070e3439eb46066963e6b870697344904
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/debug_helper.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mark up VNCR offsets (offsets 0x100..0x160)

Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM.  This commit covers offsets 0x100 to 0x160.

Many (but not all) of the registers in this range have _EL12 aliases,
and the slot in memory is shared between the _EL12 version of the
register and the _EL1 version.  Where we programmatically generate
the regdef for the _EL12 register, arrange that its
nv2_redirect_offset is set up correctly to do this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 46932cf26eae239193c465e08234c41d9df7d3d8
      
https://github.com/qemu/qemu/commit/46932cf26eae239193c465e08234c41d9df7d3d8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8)

Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM.  This commit covers offsets 0x168 to 0x1f8.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: f5bd261a61b8d30bb6ead9dce2125576d3bdc626
      
https://github.com/qemu/qemu/commit/f5bd261a61b8d30bb6ead9dce2125576d3bdc626
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC)

Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM.  This covers all the remaining offsets at 0x200 and
above, except for the GIC ICH_* registers.

(Note that because we don't implement FEAT_SPE, FEAT_TRF,
FEAT_MPAM, FEAT_BRBE or FEAT_AMUv1p1 we don't implement any
of the registers that use offsets at 0x800 and above.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: b1b7a2b555a5a88f7277e32d250589f9ad216c9b
      
https://github.com/qemu/qemu/commit/b1b7a2b555a5a88f7277e32d250589f9ad216c9b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers

Mark up the cpreginfo structs for the GIC CPU registers to indicate
the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ
in the Arm ARM.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: bde0e60be4f0d1bef6dfb8fea102d42cf98a1bff
      
https://github.com/qemu/qemu/commit/bde0e60be4f0d1bef6dfb8fea102d42cf98a1bff
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps

When interpreting CPU dumps where FEAT_NV and FEAT_NV2 are in use,
it's helpful to include the values of HCR_EL2.{NV,NV1,NV2} in the CPU
dump format, as a way of distinguishing when we are in EL1 as part of
executing guest-EL2 and when we are just in normal EL1.

Add the bits to the end of the log line that shows PSTATE and similar
information:

PSTATE=000003c9 ---- EL2h  BTYPE=0 NV NV2

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 3b32140e706b586a0b17050f99ffc812c8849bd0
      
https://github.com/qemu/qemu/commit/3b32140e706b586a0b17050f99ffc812c8849bd0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry

We already print various lines of information when we take an
exception, including the ELR and (if relevant) the FAR. Now
that FEAT_NV means that we might report something other than
the old PSTATE to the guest as the SPSR, it's worth logging
this as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: e2862554c257e908a3833265e38365e794abd362
      
https://github.com/qemu/qemu/commit/e2862554c257e908a3833265e38365e794abd362
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/cpu.c
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs

Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for
the Neoverse N2 and Neoverse V1 CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>


  Commit: 64708db302edfe57474239a51d4dad4466fac44a
      
https://github.com/qemu/qemu/commit/64708db302edfe57474239a51d4dad4466fac44a
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: convert add/sub of 128 to sub/add of -128

Extend the existing conditional that generates INC/DEC, to also swap an
ADD for a SUB and vice versa when the immediate is 128.  This facilitates
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120514.70205-1-pbonzini@redhat.com>
[rth: Use a switch on C]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: afa37be4b4b0cd36150db7d62ab68f2673f7589a
      
https://github.com/qemu/qemu/commit/afa37be4b4b0cd36150db7d62ab68f2673f7589a
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates

In the case where OR or XOR has an 8-bit immediate between 128 and 255,
we can operate on a low-byte register and shorten the output by two or
three bytes (two if a prefix byte is needed for REX.B).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20231228120524.70239-1-pbonzini@redhat.com>
[rth: Incorporate into switch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ca5bed07d0e7e0530c2cafbc134c4f74e582ac50
      
https://github.com/qemu/qemu/commit/ca5bed07d0e7e0530c2cafbc134c4f74e582ac50
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/tcg.c

  Log Message:
  -----------
  tcg/ppc: Use new registers for LQ destination

LQ has a constraint that RTp != RA, else SIGILL.
Therefore, force the destination of INDEX_op_qemu_*_ld128 to be a
new register pair, so that it cannot overlap the input address.

This requires new support in process_op_defs and tcg_reg_alloc_op.

Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240102013456.131846-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1d513e06d96697f44de4a1b85c6ff627c443e306
      
https://github.com/qemu/qemu/commit/1d513e06d96697f44de4a1b85c6ff627c443e306
  Author: Natanael Copa <ncopa@alpinelinux.org>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M util/cpuinfo-ppc.c

  Log Message:
  -----------
  util: fix build with musl libc on ppc64le

Use PPC_FEATURE2_ISEL and PPC_FEATURE2_VEC_CRYPTO from linux headers
instead of the GNU specific PPC_FEATURE2_HAS_ISEL and
PPC_FEATURE2_HAS_VEC_CRYPTO. This fixes build with musl libc.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1861
Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Fixes: 63922f467a ("tcg/ppc: Replace HAVE_ISEL macro with a variable")
Fixes: 68f340d4cd ("tcg/ppc: Enable Altivec detection")
Message-Id: <20231219105236.7059-1-ncopa@alpinelinux.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: af09421f0d732527a1743e2b71a2abad049c9110
      
https://github.com/qemu/qemu/commit/af09421f0d732527a1743e2b71a2abad049c9110
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M tcg/i386/tcg-target.c.inc
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/tcg.c
    M util/cpuinfo-ppc.c

  Log Message:
  -----------
  Merge tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu into staging

tcg/i386: Use more 8-bit immediate forms for add, sub, or, xor
tcg/ppc: Use new registers for LQ destination
util: fix build with musl libc on ppc64le

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# gpg: Signature made Wed 10 Jan 2024 21:50:34 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20240111' of https://gitlab.com/rth7680/qemu:
  util: fix build with musl libc on ppc64le
  tcg/ppc: Use new registers for LQ destination
  tcg/i386: use 8-bit OR or XOR for unsigned 8-bit immediates
  tcg/i386: convert add/sub of 128 to sub/add of -128

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f614acb7450282a119d85d759f27eae190476058
      
https://github.com/qemu/qemu/commit/f614acb7450282a119d85d759f27eae190476058
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M MAINTAINERS
    M configs/devices/arm-softmmu/default.mak
    A docs/system/arm/b-l475e-iot01a.rst
    M docs/system/arm/emulation.rst
    M docs/system/arm/stm32.rst
    M docs/system/target-arm.rst
    M hw/arm/Kconfig
    M hw/arm/armv7m.c
    A hw/arm/b-l475e-iot01a.c
    M hw/arm/fsl-imx6.c
    M hw/arm/meson.build
    M hw/arm/msf2-som.c
    M hw/arm/netduino2.c
    M hw/arm/netduinoplus2.c
    M hw/arm/olimex-stm32-h405.c
    M hw/arm/stellaris.c
    M hw/arm/stm32f100_soc.c
    M hw/arm/stm32f205_soc.c
    M hw/arm/stm32f405_soc.c
    A hw/arm/stm32l4x5_soc.c
    M hw/arm/stm32vldiscovery.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/armv7m_nvic.c
    M include/hw/arm/armv7m.h
    A include/hw/arm/stm32l4x5_soc.h
    M target/arm/cpregs.h
    M target/arm/cpu-features.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/debug_helper.c
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/syndrome.h
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/hflags.c
    M target/arm/tcg/op_helper.c
    M target/arm/tcg/tlb_helper.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20240111' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Emulate FEAT_NV, FEAT_NV2
 * add cache controller for Freescale i.MX6
 * Add minimal support for the B-L475E-IOT01A board
 * Allow SoC models to configure M-profile CPUs with correct number
   of NVIC priority bits
 * Add missing QOM parent for v7-M SoCs
 * Set CTR_EL0.{IDC,DIC} for the 'max' CPU
 * hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers

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# gpg: Signature made Thu 11 Jan 2024 11:01:39 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240111' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (41 commits)
  target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs
  target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry
  target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps
  hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers
  target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC)
  target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8)
  target/arm: Mark up VNCR offsets (offsets 0x100..0x160)
  target/arm: Mark up VNCR offsets (offsets 0x0..0xff)
  target/arm: Report VNCR_EL2 based faults correctly
  target/arm: Implement FEAT_NV2 redirection of sysregs to RAM
  target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2
  target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2
  target/arm: Implement VNCR_EL2 register
  target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits
  target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs
  target/arm: Handle FEAT_NV page table attribute changes
  target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1
  target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1}
  target/arm: Always use arm_pan_enabled() when checking if PAN is enabled
  target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1}
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/34eac35f8936...f614acb74502



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