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[Qemu-commits] [qemu/qemu] 604927: target/xtensa: fix OOB TLB entry acce


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 604927: target/xtensa: fix OOB TLB entry access
Date: Sat, 27 Jan 2024 05:00:38 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 604927e357c2b292c70826e4ce42574ad126ef32
      
https://github.com/qemu/qemu/commit/604927e357c2b292c70826e4ce42574ad126ef32
  Author: Max Filippov <jcmvbkbc@gmail.com>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/xtensa/mmu_helper.c

  Log Message:
  -----------
  target/xtensa: fix OOB TLB entry access

r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register
by the guest. The host uses 3 bits of the index for ITLB indexing and 4
bits for DTLB, but there's only 7 entries in the ITLB array and 10 in
the DTLB array, so a malicious guest may trigger out-of-bound access to
these arrays.

Change split_tlb_entry_spec return type to bool to indicate whether TLB
way passed to it is valid. Change get_tlb_entry to return NULL in case
invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that
requested TLB way and entry indices are valid. Add checks to the
[rwi]tlb helpers that requested TLB way is valid and return 0 or do
nothing when it's not.

Cc: qemu-stable@nongnu.org
Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6b504a01c17de92f2851d63f181210eff97191d0
      
https://github.com/qemu/qemu/commit/6b504a01c17de92f2851d63f181210eff97191d0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/tcg/tlb_helper.c

  Log Message:
  -----------
  target/arm: Fix VNCR fault detection logic

In arm_deliver_fault() we check for whether the fault is caused
by a data abort due to an access to a FEAT_NV2 sysreg in the
memory pointed to by the VNCR. Unfortunately part of the
condition checks the wrong argument to the function, meaning
that it would spuriously trigger, resulting in some instruction
aborts being taken to the wrong EL and reported incorrectly.

Use the right variable in the condition.

Fixes: 674e5345275d425 ("target/arm: Report VNCR_EL2 based faults correctly")
Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-id: 20240116165605.2523055-1-peter.maydell@linaro.org


  Commit: 4859da572b41d93339b2dbfc80a70ab9cd9aea7d
      
https://github.com/qemu/qemu/commit/4859da572b41d93339b2dbfc80a70ab9cd9aea7d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt.c: Remove newline from error_report() string

error_report() strings should not include trailing newlines; remove
the newline from the error we print when devices won't fit into the
address space of the CPU.

This commit also fixes the accidental hardcoded tabs that were in
this line, since we have to touch the line anyway.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240118131649.2726375-1-peter.maydell@linaro.org


  Commit: ff7888dcc6c7011abae67f02279b837a20fdd96f
      
https://github.com/qemu/qemu/commit/ff7888dcc6c7011abae67f02279b837a20fdd96f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()

Convert the musicpal key input device to use
qemu_add_kbd_event_handler().  This lets us simplify it because we no
longer need to track whether we're in the middle of a PS/2 multibyte
key sequence.

In the conversion we move the keyboard handler registration from init
to realize, because devices shouldn't disturb the state of the
simulation by doing things like registering input handlers until
they're realized, so that device objects can be introspected
safely.

The behaviour where key-repeat is permitted for the arrow-keys only
is intentional (added in commit 7c6ce4baedfcd0c), so we retain it,
and add a comment to that effect.

This is a migration compatibility break for musicpal.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20231103182750.855577-1-peter.maydell@linaro.org


  Commit: 58aa3a0b90909717a4679c195082da75926c6794
      
https://github.com/qemu/qemu/commit/58aa3a0b90909717a4679c195082da75926c6794
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/allwinner-a10.c

  Log Message:
  -----------
  hw/arm/allwinner-a10: Unconditionally map the USB Host controllers

The USB Controllers are part of the chipset, thus are
always present and mapped in memory.

This is a migration compatibility break for the cubieboard
machine started with the '-usb none' option.

Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240119215106.45776-2-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b8e2d3f86c79f164683b80f16ca55f093a816ab3
      
https://github.com/qemu/qemu/commit/b8e2d3f86c79f164683b80f16ca55f093a816ab3
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/nseries.c

  Log Message:
  -----------
  hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller

The TUSB6010 USB controller is soldered on the N800 and N810
tablets, thus is always present.

This is a migration compatibility break for the n800/n810
machines started with the '-usb none' option.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240119215106.45776-3-philmd@linaro.org
[PMM: fixed commit message typo]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 43eef24f52def75df9d491788db90e11098b1f7b
      
https://github.com/qemu/qemu/commit/43eef24f52def75df9d491788db90e11098b1f7b
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M docs/system/arm/bananapi_m2u.rst
    M hw/arm/Kconfig
    M hw/arm/allwinner-r40.c
    M include/hw/arm/allwinner-r40.h

  Log Message:
  -----------
  hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board

Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI
host controller and a USB 1.1 OHCI host controller. Add support for both
of them.

If machine USB support is not enabled, create unimplemented devices
for the USB memory ranges to avoid crashes when booting Linux.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240115182757.1095012-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2a02da74f286349c2d39c8a6102388219f476d8c
      
https://github.com/qemu/qemu/commit/2a02da74f286349c2d39c8a6102388219f476d8c
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M docs/system/arm/bananapi_m2u.rst
    M hw/arm/Kconfig
    M hw/arm/allwinner-r40.c
    M include/hw/arm/allwinner-r40.h

  Log Message:
  -----------
  hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board

Allwinner R40 supports an AHCI compliant SATA controller.
Add support for it.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20240115182757.1095012-3-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2af71d28e796a8cbf3e661c7650be3f0197f404f
      
https://github.com/qemu/qemu/commit/2af71d28e796a8cbf3e661c7650be3f0197f404f
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M docs/system/arm/bananapi_m2u.rst
    M hw/arm/Kconfig
    M hw/arm/allwinner-r40.c
    M include/hw/arm/allwinner-r40.h

  Log Message:
  -----------
  hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board

Add watchdog timer support to Allwinner-H40 and Bananapi.
The watchdog timer is added as an overlay to the Timer
module memory map.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Message-id: 20240115182757.1095012-4-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fd8d2bba5d56a850e81d8335e1cc18e3908c2a45
      
https://github.com/qemu/qemu/commit/fd8d2bba5d56a850e81d8335e1cc18e3908c2a45
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  hw/arm/exynos4210: Include missing 'exec/tswap.h' header

hw/arm/exynos4210.c calls tswap32() which is declared
in "exec/tswap.h". Include it in order to avoid when
refactoring unrelated headers:

  hw/arm/exynos4210.c:499:22: error: call to undeclared function 'tswap32';
  ISO C99 and later do not support implicit function declarations 
[-Wimplicit-function-declaration]
          smpboot[n] = tswap32(smpboot[n]);
                       ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c143edaaee774be87b6ea3102934ff66d16f287e
      
https://github.com/qemu/qemu/commit/c143edaaee774be87b6ea3102934ff66d16f287e
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header

hw/arm/xilinx_zynq.c calls tswap32() which is declared
in "exec/tswap.h". Include it in order to avoid when
refactoring unrelated headers:

  hw/arm/xilinx_zynq.c:103:31: error: call to undeclared function 'tswap32';
  ISO C99 and later do not support implicit function declarations 
[-Wimplicit-function-declaration]
          board_setup_blob[n] = tswap32(board_setup_blob[n]);
                                ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7b31c2db804733c30d15ffcd0d3dc39c76e27420
      
https://github.com/qemu/qemu/commit/7b31c2db804733c30d15ffcd0d3dc39c76e27420
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/smmuv3-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Include missing 'hw/registerfields.h' header

hw/arm/smmuv3-internal.h uses the REG32() and FIELD()
macros defined in "hw/registerfields.h". Include it in
order to avoid when refactoring unrelated headers:

  In file included from ../../hw/arm/smmuv3.c:34:
  hw/arm/smmuv3-internal.h:36:28: error: expected identifier
  REG32(IDR0,                0x0)
                             ^
  hw/arm/smmuv3-internal.h:37:5: error: expected function body after function 
declarator
      FIELD(IDR0, S2P,         0 , 1)
      ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5b5f41696356d10474e711be9d8cfe5eb01a7e89
      
https://github.com/qemu/qemu/commit/5b5f41696356d10474e711be9d8cfe5eb01a7e89
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: Include missing 'cpu.h' header

include/hw/arm/xlnx-versal.h uses the ARMCPU structure which
is defined in the "target/arm/cpu.h" header. Include it in
order to avoid when refactoring unrelated headers:

  In file included from hw/arm/xlnx-versal-virt.c:20:
  include/hw/arm/xlnx-versal.h:62:23: error: array has incomplete element type 
'ARMCPU' (aka 'struct ArchCPU')
              ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
                        ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5eb815c19acf39e3fc9fa60705e15f7ebf00258d
      
https://github.com/qemu/qemu/commit/5eb815c19acf39e3fc9fa60705e15f7ebf00258d
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpu-features.h

  Log Message:
  -----------
  target/arm/cpu-features: Include missing 'hw/registerfields.h' header

target/arm/cpu-features.h uses the FIELD_EX32() macro
defined in "hw/registerfields.h". Include it in order
to avoid when refactoring unrelated headers:

  target/arm/cpu-features.h:44:12: error: call to undeclared function 
'FIELD_EX32';
  ISO C99 and later do not support implicit function declarations 
[-Wimplicit-function-declaration]
      return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
             ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 35d44e3f9302fc37b36819b193d35de2118597aa
      
https://github.com/qemu/qemu/commit/35d44e3f9302fc37b36819b193d35de2118597aa
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h

  Log Message:
  -----------
  target/arm/cpregs: Include missing 'hw/registerfields.h' header

target/arm/cpregs.h uses the FIELD() macro defined in
"hw/registerfields.h". Include it in order to avoid when
refactoring unrelated headers:

  target/arm/cpregs.h:347:30: error: expected identifier
  FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
                               ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7f31b2f56b69c9257d13f124485807d380c86e28
      
https://github.com/qemu/qemu/commit/7f31b2f56b69c9257d13f124485807d380c86e28
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpregs.h

  Log Message:
  -----------
  target/arm/cpregs: Include missing 'kvm-consts.h' header

target/arm/cpregs.h uses the CP_REG_ARCH_* definitions
from "target/arm/kvm-consts.h". Include it in order to
avoid when refactoring unrelated headers:

  target/arm/cpregs.h:191:18: error: use of undeclared identifier 
'CP_REG_ARCH_MASK'
      if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
                   ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 750245ed7ce2a426a4eaf026f1af3a21fbdc19dc
      
https://github.com/qemu/qemu/commit/750245ed7ce2a426a4eaf026f1af3a21fbdc19dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/npcm7xx.c
    M hw/arm/sbsa-ref.c
    M hw/arm/virt.c
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Rename arm_cpu_mp_affinity

Rename to arm_build_mp_affinity.  This frees up the name for
other usage, and emphasizes that the cpu object is not involved.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c4380f7bcdcb68fdfca876db366782a807fab8f7
      
https://github.com/qemu/qemu/commit/c4380f7bcdcb68fdfca876db366782a807fab8f7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/arm/xlnx-versal-virt.c
    M hw/misc/xlnx-versal-crl.c
    M target/arm/arm-powerctl.c
    M target/arm/cpu.h
    M target/arm/hvf/hvf.c
    M target/arm/tcg/psci.c

  Log Message:
  -----------
  target/arm: Create arm_cpu_mp_affinity

Wrapper to return the mp affinity bits from the cpu.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e2d8cf9b5312ada63ffa7460dec7cf89cf0bd61e
      
https://github.com/qemu/qemu/commit/e2d8cf9b5312ada63ffa7460dec7cf89cf0bd61e
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/arm/xlnx-versal-virt.c
    M hw/misc/xlnx-versal-crl.c
    M target/arm/arm-powerctl.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/hvf/hvf.c
    A target/arm/multiprocessing.h
    M target/arm/tcg/psci.c

  Log Message:
  -----------
  target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header

Declare arm_cpu_mp_affinity() prototype in the new
 "target/arm/multiprocessing.h" header so units in
hw/arm/ can use it without having to include the huge
target-specific "cpu.h".

File list to include the new header generated using:

  $ git grep -lw arm_cpu_mp_affinity

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9ab3ac5ab63efb497c535b60e4e52b63eaf1a104
      
https://github.com/qemu/qemu/commit/9ab3ac5ab63efb497c535b60e4e52b63eaf1a104
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpu-qom.h
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'

Missed in commit 2d56be5a29 ("target: Declare
FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See
it for more details.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3896b6ffffe97aa387631a62948a51913f12f7e5
      
https://github.com/qemu/qemu/commit/3896b6ffffe97aa387631a62948a51913f12f7e5
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/cpu/a9mpcore.c
    M hw/cpu/meson.build

  Log Message:
  -----------
  hw/cpu/a9mpcore: Build it only once

hw/cpu/a9mpcore.c doesn't require "cpu.h" anymore.
By removing it, the unit become target agnostic:
we can build it once. Update meson.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-13-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8b2c5fb7c7bb3aee2bc56827802425906e4a2f9c
      
https://github.com/qemu/qemu/commit/8b2c5fb7c7bb3aee2bc56827802425906e4a2f9c
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/misc/xlnx-versal-crl.c
    M include/hw/misc/xlnx-versal-crl.h

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'

"target/arm/cpu.h" is target specific, any file including it
becomes target specific too, thus this is the same for any file
including "hw/misc/xlnx-versal-crl.h".

"hw/misc/xlnx-versal-crl.h" doesn't require any target specific
definition however, only the target-agnostic QOM definitions
from "target/arm/cpu-qom.h". Include the latter header to avoid
tainting unnecessary objects as target-specific.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-14-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3e283646e7524e3f0346431c27d03aa53198c8ad
      
https://github.com/qemu/qemu/commit/3e283646e7524e3f0346431c27d03aa53198c8ad
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/misc/meson.build
    M hw/misc/xlnx-versal-crl.c

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: Build it only once

hw/misc/xlnx-versal-crl.c doesn't require "cpu.h"
anymore.  By removing it, the unit become target
agnostic: we can build it once. Update meson.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-15-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 22036ae5773ab46eeee412c0aa3ec2eb1e4008e7
      
https://github.com/qemu/qemu/commit/22036ae5773ab46eeee412c0aa3ec2eb1e4008e7
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpu-qom.h
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Expose M-profile register bank index definitions

The ARMv7M QDev container accesses the QDev SysTickState
by its secure/non-secure bank index. In order to make
the "hw/intc/armv7m_nvic.h" header target-agnostic in
the next commit, first move the M-profile bank index
definitions to "target/arm/cpu-qom.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-16-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9ab1cf655867dafb132ccd17db360fa1d606981b
      
https://github.com/qemu/qemu/commit/9ab1cf655867dafb132ccd17db360fa1d606981b
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header

Now than we can access the M-profile bank index
definitions from the target-agnostic "cpu-qom.h"
header, we don't need the huge "cpu.h" anymore
(except in hw/arm/armv7m.c). Reduce its inclusion
to the source unit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-17-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d780d056f8acdee73a1c34d95733851d58aecd60
      
https://github.com/qemu/qemu/commit/d780d056f8acdee73a1c34d95733851d58aecd60
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/allwinner-a10.c
    M hw/arm/allwinner-h3.c
    M hw/arm/allwinner-r40.c
    M hw/arm/armv7m.c
    M hw/arm/aspeed_ast2400.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/bcm2836.c
    M hw/arm/exynos4210.c
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx31.c
    M hw/arm/fsl-imx6.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c
    M hw/arm/highbank.c
    M hw/arm/integratorcp.c
    M hw/arm/musicpal.c
    M hw/arm/npcm7xx.c
    M hw/arm/omap1.c
    M hw/arm/omap2.c
    M hw/arm/realview.c
    M hw/arm/sbsa-ref.c
    M hw/arm/strongarm.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-versal.c
    M hw/arm/xlnx-zynqmp.c
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header

The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO
IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init()
handler. To allow non-ARM code to raise interrupt on ARM cores,
move they to 'target/arm/cpu-qom.h' which is non-ARM specific and
can be included by any hw/ file.

File list to include the new header generated using:

  $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)'

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-18-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 32b3a0c90095f4b5b453e72c2a3a25964ef04640
      
https://github.com/qemu/qemu/commit/32b3a0c90095f4b5b453e72c2a3a25964ef04640
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Move e2h_access() helper around

e2h_access() was added in commit bb5972e439 ("target/arm:
Add VHE timer register redirection and aliasing") close to
the generic_timer_cp_reginfo[] array, but isn't used until
vhe_reginfo[] definition. Move it closer to the other e2h
helpers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-19-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f4f318b41abe76a68ec1d616744ab9d6ec839abc
      
https://github.com/qemu/qemu/commit/f4f318b41abe76a68ec1d616744ab9d6ec839abc
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/allwinner-h3.c
    M hw/arm/allwinner-r40.c
    M hw/arm/bcm2836.c
    M hw/arm/sbsa-ref.c
    M hw/arm/virt.c
    M hw/arm/xlnx-versal.c
    M hw/arm/xlnx-zynqmp.c
    M hw/cpu/a15mpcore.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    A target/arm/gtimer.h
    M target/arm/helper.c
    M target/arm/hvf/hvf.c
    M target/arm/kvm.c
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Move GTimer definitions to new 'gtimer.h' header

Move Arm A-class Generic Timer definitions to the new
"target/arm/gtimer.h" header so units in hw/ which don't
need access to ARMCPU internals can use them without
having to include the huge "cpu.h".

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-20-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9404dcdeaaca3680f6abe17a50e7cd519d66ba9e
      
https://github.com/qemu/qemu/commit/9404dcdeaaca3680f6abe17a50e7cd519d66ba9e
  Author: Philippe Mathieu-Daudé <philmd@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/collie.c
    M hw/arm/gumstix.c
    M hw/arm/integratorcp.c
    M hw/arm/mainstone.c
    M hw/arm/meson.build
    M hw/arm/musicpal.c
    M hw/arm/omap2.c
    M hw/arm/omap_sx1.c
    M hw/arm/palm.c
    M hw/arm/spitz.c
    M hw/arm/strongarm.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/z2.c

  Log Message:
  -----------
  hw/arm: Build various units only once

Various files in hw/arm/ don't require "cpu.h" anymore.
Except virt-acpi-build.c, all of them don't require any
ARM specific knowledge anymore and can be build once as
target agnostic units. Update meson accordingly.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240118200643.29037-21-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b0d1021ed948601a7e53e5e30b36a787040d77cf
      
https://github.com/qemu/qemu/commit/b0d1021ed948601a7e53e5e30b36a787040d77cf
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/fsl-imx6ul.c
    M include/hw/arm/fsl-imx6ul.h

  Log Message:
  -----------
  fsl-imx6ul: Add various missing unimplemented devices

Add MMDC, OCOTP, SQPI, CAAM, and USBMISC as unimplemented devices.

This allows operating systems such as Linux to run emulations such as
mcimx6ul-evk.

Before commit 0cd4926b85 ("Refactor i.MX6UL processor code"), the affected
memory ranges were covered by the unimplemented DAP device. The commit
reduced the DAP address range from 0x100000 to 4kB, and the emulation
thus no longer covered the various unimplemented devices in the affected
address range.

Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code")
Cc: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240120005356.2599547-1-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1acf21599859cf2a23a7c9a839f8be7ad555e351
      
https://github.com/qemu/qemu/commit/1acf21599859cf2a23a7c9a839f8be7ad555e351
  Author: Gustavo Romero <gustavo.romero@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M docs/system/arm/virt.rst

  Log Message:
  -----------
  docs/system/arm/virt.rst: Add note on CPU features off by default

Add a note on CPU features that are off by default in `virt` machines.
Some CPU features will remain off even if a CPU-capable CPU (e.g.,
`-cpu max`) is selected because they require support in both the CPU
itself and in the wider system. Therefore, the user, besides selecting a
CPU that supports such features, must also turn on the feature using a
machine option.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240122211215.95073-1-gustavo.romero@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 988f244297199402dc4a0230b7aed208e85a918e
      
https://github.com/qemu/qemu/commit/988f244297199402dc4a0230b7aed208e85a918e
  Author: Rayhan Faizel <rayhan.faizel@gmail.com>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/char/imx_serial.c
    M include/hw/char/imx_serial.h

  Log Message:
  -----------
  hw/char/imx_serial: Implement receive FIFO and ageing timer

This patch implements a 32 half word FIFO as per imx serial device
specifications.  If a non empty FIFO is below the trigger level, an
ageing timer will tick for a duration of 8 characters.  On expiry,
AGTIM will be set triggering an interrupt.  AGTIM timer resets when
there is activity in the receive FIFO.

Otherwise, RRDY is set when trigger level is exceeded.  The receive
trigger level is 8 in newer kernel versions and 1 in older ones.

This change will break migration compatibility for the imx boards.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tidyups]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6fffc8378562c7fea6290c430b4f653f830a4c1a
      
https://github.com/qemu/qemu/commit/6fffc8378562c7fea6290c430b4f653f830a4c1a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Fix A64 scalar SQSHRN and SQRSHRN

In commit 1b7bc9b5c8bf374dd we changed handle_vec_simd_sqshrn() so
that instead of starting with a 0 value and depositing in each new
element from the narrowing operation, it instead started with the raw
result of the narrowing operation of the first element.

This is fine in the vector case, because the deposit operations for
the second and subsequent elements will always overwrite any higher
bits that might have been in the first element's result value in
tcg_rd.  However in the scalar case we only go through this loop
once.  The effect is that for a signed narrowing operation, if the
result is negative then we will now return a value where the bits
above the first element are incorrectly 1 (because the narrowfn
returns a sign-extended result, not one that is truncated to the
element size).

Fix this by using an extract operation to get exactly the correct
bits of the output of the narrowfn for element 1, instead of a
plain move.

Cc: qemu-stable@nongnu.org
Fixes: 1b7bc9b5c8bf374dd3 ("target/arm: Avoid tcg_const_ptr in 
handle_vec_simd_sqshrn")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2089
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240123153416.877308-1-peter.maydell@linaro.org


  Commit: 18281b257801947bb0b23c02df87d6acd92c6910
      
https://github.com/qemu/qemu/commit/18281b257801947bb0b23c02df87d6acd92c6910
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M include/qemu/bswap.h

  Log Message:
  -----------
  bswap.h: Fix const_le64() macro

The const_le64() macro introduced in commit 845d80a8c7b187 turns out
to have a bug which means that on big-endian systems the compiler
complains if the argument isn't already a 64-bit type. This hasn't
caused a problem yet, because there are no in-tree uses, but it
means it's not possible for anybody to add one without it failing CI.

This example is from an attempted use of it with the argument '0',
from the s390 CI runner's gcc:

../block/blklogwrites.c: In function ‘blk_log_writes_co_do_log’:
../include/qemu/bswap.h:148:36: error: left shift count >= width of
type [-Werror=shift-count-overflow]
148 | ((((_x) & 0x00000000000000ffU) << 56) | \
| ^~
../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’
409 | .nr_entries = const_le64(0),
| ^~~~~~~~~~
../include/qemu/bswap.h:149:36: error: left shift count >= width of
type [-Werror=shift-count-overflow]
149 | (((_x) & 0x000000000000ff00U) << 40) | \
| ^~
../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’
409 | .nr_entries = const_le64(0),
| ^~~~~~~~~~
cc1: all warnings being treated as errors

Fix this by making all the constants in the macro have the ULL
suffix.  This will cause them all to be 64-bit integers, which means
the result of the logical & will also be an unsigned 64-bit type,
even if the input to the macro is a smaller type, and so the shifts
will be in range.

Fixes: 845d80a8c7b187 ("qemu/bswap: Add const_le64()")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Message-id: 20240122173735.472951-1-peter.maydell@linaro.org


  Commit: ee0a2e3c9d2991a11c13ffadb15e4d0add43c257
      
https://github.com/qemu/qemu/commit/ee0a2e3c9d2991a11c13ffadb15e4d0add43c257
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M target/arm/cpu-features.h

  Log Message:
  -----------
  target/arm: Fix incorrect aa64_tidcp1 feature check

A typo in the implementation of isar_feature_aa64_tidcp1() means we
were checking the field in the wrong ID register, so we might have
provided the feature on CPUs that don't have it and not provided
it on CPUs that should have it. Correct this bug.

Cc: qemu-stable@nongnu.org
Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1"
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240123160333.958841-1-peter.maydell@linaro.org


  Commit: 5e6be95ed1578c7cfac2082b39384d99fd912508
      
https://github.com/qemu/qemu/commit/5e6be95ed1578c7cfac2082b39384d99fd912508
  Author: Nikita Ostrenkov <n.ostrenkov@gmail.com>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/fsl-imx6.c
    M include/hw/arm/fsl-imx6.h

  Log Message:
  -----------
  hw/arm: add PCIe to Freescale i.MX6

Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Message-id: 20240108140325.1291-1-n.ostrenkov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7a1dc45af581d2b643cdbf33c01fd96271616fbd
      
https://github.com/qemu/qemu/commit/7a1dc45af581d2b643cdbf33c01fd96271616fbd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M docs/system/arm/bananapi_m2u.rst
    M docs/system/arm/virt.rst
    M hw/arm/Kconfig
    M hw/arm/allwinner-a10.c
    M hw/arm/allwinner-h3.c
    M hw/arm/allwinner-r40.c
    M hw/arm/armv7m.c
    M hw/arm/aspeed_ast2400.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/bcm2836.c
    M hw/arm/collie.c
    M hw/arm/exynos4210.c
    M hw/arm/fsl-imx25.c
    M hw/arm/fsl-imx31.c
    M hw/arm/fsl-imx6.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c
    M hw/arm/gumstix.c
    M hw/arm/highbank.c
    M hw/arm/integratorcp.c
    M hw/arm/mainstone.c
    M hw/arm/meson.build
    M hw/arm/musicpal.c
    M hw/arm/npcm7xx.c
    M hw/arm/nseries.c
    M hw/arm/omap1.c
    M hw/arm/omap2.c
    M hw/arm/omap_sx1.c
    M hw/arm/palm.c
    M hw/arm/realview.c
    M hw/arm/sbsa-ref.c
    M hw/arm/smmuv3-internal.h
    M hw/arm/spitz.c
    M hw/arm/strongarm.c
    M hw/arm/versatilepb.c
    M hw/arm/vexpress.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/arm/xilinx_zynq.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M hw/arm/xlnx-zynqmp.c
    M hw/arm/z2.c
    M hw/char/imx_serial.c
    M hw/cpu/a15mpcore.c
    M hw/cpu/a9mpcore.c
    M hw/cpu/meson.build
    M hw/misc/meson.build
    M hw/misc/xlnx-versal-crl.c
    M include/hw/arm/allwinner-r40.h
    M include/hw/arm/fsl-imx6.h
    M include/hw/arm/fsl-imx6ul.h
    M include/hw/arm/xlnx-versal.h
    M include/hw/char/imx_serial.h
    M include/hw/intc/armv7m_nvic.h
    M include/hw/misc/xlnx-versal-crl.h
    M include/qemu/bswap.h
    M target/arm/arm-powerctl.c
    M target/arm/cpregs.h
    M target/arm/cpu-features.h
    M target/arm/cpu-qom.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    A target/arm/gtimer.h
    M target/arm/helper.c
    M target/arm/hvf/hvf.c
    M target/arm/kvm.c
    M target/arm/machine.c
    A target/arm/multiprocessing.h
    M target/arm/tcg/psci.c
    M target/arm/tcg/tlb_helper.c
    M target/arm/tcg/translate-a64.c
    M target/xtensa/mmu_helper.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20240126' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix VNCR fault detection logic
 * Fix A64 scalar SQSHRN and SQRSHRN
 * Fix incorrect aa64_tidcp1 feature check
 * hw/arm/virt.c: Remove newline from error_report() string
 * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
 * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
 * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
 * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
 * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
 * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
 * arm: various include header cleanups
 * cleanups to allow some files to be built only once
 * fsl-imx6ul: Add various missing unimplemented devices
 * docs/system/arm/virt.rst: Add note on CPU features off by default
 * hw/char/imx_serial: Implement receive FIFO and ageing timer
 * target/xtensa: fix OOB TLB entry access
 * bswap.h: Fix const_le64() macro
 * hw/arm: add PCIe to Freescale i.MX6

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# gpg: Signature made Fri 26 Jan 2024 14:32:59 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240126' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  hw/arm: add PCIe to Freescale i.MX6
  target/arm: Fix incorrect aa64_tidcp1 feature check
  bswap.h: Fix const_le64() macro
  target/arm: Fix A64 scalar SQSHRN and SQRSHRN
  hw/char/imx_serial: Implement receive FIFO and ageing timer
  docs/system/arm/virt.rst: Add note on CPU features off by default
  fsl-imx6ul: Add various missing unimplemented devices
  hw/arm: Build various units only once
  target/arm: Move GTimer definitions to new 'gtimer.h' header
  target/arm: Move e2h_access() helper around
  target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
  hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
  target/arm: Expose M-profile register bank index definitions
  hw/misc/xlnx-versal-crl: Build it only once
  hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
  hw/cpu/a9mpcore: Build it only once
  target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
  target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
  target/arm: Create arm_cpu_mp_affinity
  target/arm: Rename arm_cpu_mp_affinity
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/b9c4a2018aa9...7a1dc45af581



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